TWI266394B - Semiconductor device and method of fabricating the same - Google Patents

Semiconductor device and method of fabricating the same

Info

Publication number
TWI266394B
TWI266394B TW094102223A TW94102223A TWI266394B TW I266394 B TWI266394 B TW I266394B TW 094102223 A TW094102223 A TW 094102223A TW 94102223 A TW94102223 A TW 94102223A TW I266394 B TWI266394 B TW I266394B
Authority
TW
Taiwan
Prior art keywords
base member
semiconductor
constructing body
semiconductor device
semiconductor substrate
Prior art date
Application number
TW094102223A
Other languages
English (en)
Other versions
TW200531237A (en
Inventor
Ichiro Mihara
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of TW200531237A publication Critical patent/TW200531237A/zh
Application granted granted Critical
Publication of TWI266394B publication Critical patent/TWI266394B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • C—CHEMISTRY; METALLURGY
    • C02—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F1/00—Treatment of water, waste water, or sewage
    • C02F1/42—Treatment of water, waste water, or sewage by ion-exchange
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • C—CHEMISTRY; METALLURGY
    • C02—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
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    • C02F2201/00—Apparatus for treatment of water, waste water or sewage
    • C02F2201/002—Construction details of the apparatus
    • C02F2201/004—Seals, connections
    • C—CHEMISTRY; METALLURGY
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    • C02F—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Hydrology & Water Resources (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Environmental & Geological Engineering (AREA)
  • Water Supply & Treatment (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
TW094102223A 2004-01-27 2005-01-26 Semiconductor device and method of fabricating the same TWI266394B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004018536A JP4093186B2 (ja) 2004-01-27 2004-01-27 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW200531237A TW200531237A (en) 2005-09-16
TWI266394B true TWI266394B (en) 2006-11-11

Family

ID=34792546

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094102223A TWI266394B (en) 2004-01-27 2005-01-26 Semiconductor device and method of fabricating the same

Country Status (5)

Country Link
US (2) US7112469B2 (zh)
JP (1) JP4093186B2 (zh)
KR (1) KR100595890B1 (zh)
CN (1) CN100383965C (zh)
TW (1) TWI266394B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI497618B (zh) * 2009-06-03 2015-08-21 Shibaura Mechatronics Corp Lead connection device for semiconductor structure and connection method thereof

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7485489B2 (en) * 2002-06-19 2009-02-03 Bjoersell Sten Electronics circuit manufacture
JP3945483B2 (ja) * 2004-01-27 2007-07-18 カシオ計算機株式会社 半導体装置の製造方法
JP4093186B2 (ja) 2004-01-27 2008-06-04 カシオ計算機株式会社 半導体装置の製造方法
JP4398305B2 (ja) * 2004-06-02 2010-01-13 カシオ計算機株式会社 半導体装置およびその製造方法
JP2006173232A (ja) * 2004-12-14 2006-06-29 Casio Comput Co Ltd 半導体装置およびその製造方法
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
US7393770B2 (en) 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
JP4659534B2 (ja) * 2005-07-04 2011-03-30 三菱電機株式会社 半導体装置
US7307348B2 (en) 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
JP4609317B2 (ja) * 2005-12-28 2011-01-12 カシオ計算機株式会社 回路基板
US7939368B2 (en) * 2006-03-07 2011-05-10 Stats Chippac Ltd. Wafer level chip scale package system with a thermal dissipation structure
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
US7446424B2 (en) * 2006-07-19 2008-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for semiconductor package
SG139594A1 (en) * 2006-08-04 2008-02-29 Micron Technology Inc Microelectronic devices and methods for manufacturing microelectronic devices
JP2008210933A (ja) 2007-02-26 2008-09-11 Casio Comput Co Ltd 半導体装置
JP2009043857A (ja) * 2007-08-08 2009-02-26 Casio Comput Co Ltd 半導体装置およびその製造方法
KR101161061B1 (ko) * 2007-08-08 2012-07-02 가부시키가이샤 테라미크로스 반도체 장치 제조방법
TW200935572A (en) * 2008-02-01 2009-08-16 Yu-Nung Shen Semiconductor chip packaging body and its packaging method
TWI453877B (zh) * 2008-11-07 2014-09-21 Advanced Semiconductor Eng 內埋晶片封裝的結構及製程
KR101015704B1 (ko) * 2008-12-01 2011-02-22 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
US20100133682A1 (en) 2008-12-02 2010-06-03 Infineon Technologies Ag Semiconductor device
FR2946795B1 (fr) * 2009-06-12 2011-07-22 3D Plus Procede de positionnement des puces lors de la fabrication d'une plaque reconstituee
US8987896B2 (en) * 2009-12-16 2015-03-24 Intel Corporation High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
KR20120026855A (ko) 2010-09-10 2012-03-20 삼성전기주식회사 임베디드 볼 그리드 어레이 기판 및 그 제조 방법
US8546922B2 (en) * 2010-09-30 2013-10-01 Ibiden Co., Ltd. Wiring board
US8466553B2 (en) * 2010-10-12 2013-06-18 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package having the same
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8766422B2 (en) * 2010-12-30 2014-07-01 Stmicroelectronics Pte Ltd. Through hole via filling using electroless plating
US8487426B2 (en) 2011-03-15 2013-07-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with embedded die and manufacturing methods thereof
US8552540B2 (en) * 2011-05-10 2013-10-08 Conexant Systems, Inc. Wafer level package with thermal pad for higher power dissipation
US9112007B2 (en) * 2012-09-14 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Through via structure and method
US9595482B2 (en) * 2015-03-16 2017-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for die probing
US9728498B2 (en) * 2015-06-30 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure
US9520372B1 (en) * 2015-07-20 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package (WLP) and method for forming the same
KR101973431B1 (ko) * 2016-09-29 2019-04-29 삼성전기주식회사 팬-아웃 반도체 패키지
US10665522B2 (en) * 2017-12-22 2020-05-26 Intel IP Corporation Package including an integrated routing layer and a molded routing layer
JP2022014750A (ja) * 2020-07-07 2022-01-20 キオクシア株式会社 半導体装置およびその製造方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323436B1 (en) * 1997-04-08 2001-11-27 International Business Machines Corporation High density printed wiring board possessing controlled coefficient of thermal expansion with thin film redistribution layer
JP2001015640A (ja) * 1999-07-01 2001-01-19 Toshiba Corp 半導体集積回路装置
JP2001118959A (ja) 1999-08-06 2001-04-27 Toppan Printing Co Ltd 接続端子及びそれを用いた半導体装置
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
JP2001168226A (ja) * 1999-12-14 2001-06-22 Shinko Electric Ind Co Ltd 半導体パッケージ及び半導体装置
JP3813402B2 (ja) * 2000-01-31 2006-08-23 新光電気工業株式会社 半導体装置の製造方法
JP2001257239A (ja) 2000-03-13 2001-09-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP3606785B2 (ja) * 2000-05-26 2005-01-05 日本特殊陶業株式会社 配線基板の製造方法
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
EP1213952A3 (en) * 2000-12-05 2004-06-30 Matsushita Electric Industrial Co., Ltd. Circuit substrate and manufacturing method thereof
JP4033639B2 (ja) 2000-12-15 2008-01-16 イビデン株式会社 多層プリント配線板
JP4869488B2 (ja) 2000-12-15 2012-02-08 イビデン株式会社 多層プリント配線板の製造方法
JP4587593B2 (ja) * 2001-04-12 2010-11-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR100920535B1 (ko) * 2001-08-31 2009-10-08 스미토모 베이클리트 컴퍼니 리미티드 수지 조성물, 프리프레그, 적층판 및 반도체 패키지
JP2003298005A (ja) 2002-02-04 2003-10-17 Casio Comput Co Ltd 半導体装置およびその製造方法
TW577160B (en) * 2002-02-04 2004-02-21 Casio Computer Co Ltd Semiconductor device and manufacturing method thereof
US6770971B2 (en) * 2002-06-14 2004-08-03 Casio Computer Co., Ltd. Semiconductor device and method of fabricating the same
JP3888302B2 (ja) * 2002-12-24 2007-02-28 カシオ計算機株式会社 半導体装置
EP1636842B1 (en) * 2003-06-03 2011-08-17 Casio Computer Co., Ltd. Stackable semiconductor device and method of manufacturing the same
JP4269806B2 (ja) * 2003-06-30 2009-05-27 カシオ計算機株式会社 半導体装置およびその製造方法
JP4012496B2 (ja) * 2003-09-19 2007-11-21 カシオ計算機株式会社 半導体装置
US7489032B2 (en) * 2003-12-25 2009-02-10 Casio Computer Co., Ltd. Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same
JP3945483B2 (ja) * 2004-01-27 2007-07-18 カシオ計算機株式会社 半導体装置の製造方法
JP4093186B2 (ja) * 2004-01-27 2008-06-04 カシオ計算機株式会社 半導体装置の製造方法
JP4055717B2 (ja) * 2004-01-27 2008-03-05 カシオ計算機株式会社 半導体装置およびその製造方法
JP3925503B2 (ja) * 2004-03-15 2007-06-06 カシオ計算機株式会社 半導体装置
JP3925809B2 (ja) * 2004-03-31 2007-06-06 カシオ計算機株式会社 半導体装置およびその製造方法
JP4398305B2 (ja) * 2004-06-02 2010-01-13 カシオ計算機株式会社 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI497618B (zh) * 2009-06-03 2015-08-21 Shibaura Mechatronics Corp Lead connection device for semiconductor structure and connection method thereof

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US7112469B2 (en) 2006-09-26
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US20050161803A1 (en) 2005-07-28
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US7550843B2 (en) 2009-06-23
US20060244136A1 (en) 2006-11-02
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