TWI250568B - Method of producing a semiconductor device - Google Patents

Method of producing a semiconductor device Download PDF

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Publication number
TWI250568B
TWI250568B TW090113022A TW90113022A TWI250568B TW I250568 B TWI250568 B TW I250568B TW 090113022 A TW090113022 A TW 090113022A TW 90113022 A TW90113022 A TW 90113022A TW I250568 B TWI250568 B TW I250568B
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Taiwan
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wafer
groove
split
forming
splitting
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TW090113022A
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English (en)
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Seiji Ichikawa
Tatsuo Tokue
Nobuo Nagano
Fumie Ogihara
Taku Sato
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Nippon Electric Co
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67092Apparatus for mechanical treatment
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B28WORKING CEMENT, CLAY, OR STONE
    • B28DWORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0005Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing
    • B28D5/0011Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing with preliminary treatment, e.g. weakening by scoring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043Making grooves, e.g. cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09036Recesses or grooves in insulating substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/0909Preformed cutting or breaking line
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15Position of the PCB during processing
    • H05K2203/1572Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/302Bending a rigid substrate; Breaking rigid substrates by bending
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T225/00Severing by tearing or breaking
    • Y10T225/10Methods
    • Y10T225/12With preliminary weakening
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T225/00Severing by tearing or breaking
    • Y10T225/30Breaking or tearing apparatus
    • Y10T225/307Combined with preliminary weakener or with nonbreaking cutter
    • Y10T225/321Preliminary weakener
    • Y10T225/325With means to apply moment of force to weakened work

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Dicing (AREA)

Description

1250568 五、發明説明(1 ) 發明背景 本發明揭示一種製造半導體封裝之方法,在封裝基 體上使得用於無引線晶圓載體封裝之多層晶圓分裂。 用於上述應用之多層晶圓習慣上在其相對主表面內 形成對齊V型槽溝。劈裂力量施加在晶圓上使得其 在封裝基體上分裂。明確地,當劈裂力量作用在具有 晶體構造之晶圓上時,晶圓分裂之方向中不一定 (constant)。在晶圓內所形成槽溝作爲保持上述方向 一疋° 然而,槽溝以半切來形成在晶圓內而不是全切。如 此產生問題在如果槽溝沒有精確地對齊,則分裂裝備 可能無法沿著連接槽溝之線來使得晶圓分裂。明確地 ’可能地晶圓自一槽溝來分裂,但是失誤其他槽溝。 結果,在所獲得之晶片上出現毛邊,且使得晶片無法 精確地安裝。 相關於本發明之技術發表在日本專利公報第6 1 -2 5 3 83 0號及1 1 -224 8 6 5號、日本專利公報及第6-H071號及日本專利第2,74 8,3 5 5及2,780,618號。 發明之槪述 本發明之目的在提供製造半導體裝置之方法,能夠 在封裝基體上具有最小毛邊來分裂用於無引線晶片載 體封裝之多層晶圓。 製造本發明半導體裝置之方法可應用在無引線載體 封裝之多層晶圓,而使得其在封裝基體上分裂。本發 121娜8 五、 發明說明 (2) 明 開 始步驟 在晶圓厚 度之方向中晶圓的一主表面內 形 成 大 至女V形 槽溝。脆 弱劈裂部份對齊槽溝形成在晶 圓 之 另 一主表 面內。劈 裂力量施加在晶圓,因而在劈 裂 部 份 形成分 裂,使得 晶圓產生自槽溝朝向晶圓厚度 方 向 中 之劈裂 部份來分 裂。劈裂部份可以強固非劈裂 部 份 來 替代, 在本情形 中’因爲劈裂力量差異,分裂 形 成 在 非劈裂 部份及晶 圓間之介面內。 附 圖 單 說明 本 發明上 述及其他 目的、特徵及優點由下文詳細 說 明 連 同附圖 將變得顯 而易見,其中 第 1 A圖爲平面圖 ’表示以製造半導體裝置之習用方 法 來 斷裂多 層晶圓; 第 1 B圖是剖面圖 ’表示第1A圖圓A晶圓部份; 第 2A圖是平面圖 ,表示以根據本發明製造半導體裝 置 之 方法的 第一實施 例來斷裂多層晶圓; 第 2B圖是剖面圖 ,表示第1 A圖圓A晶圓部份; 第 3圖是 對應第2B圖的剖面圖,表示本發明第二 :實 施 例 > 第 4圖也 是對應第 2B圖的剖面圖,表示本發明第三 實 施 例;及 第 5圖是 剖面圖, 表示可應用於所揭示任一實施 例 之 特 定斷裂 裝備。 -4- 1250568 五、發明説明(3 ) 較佳實施例之說明 爲更佳地理解本發明,將簡略地參考製造半導體裝 置之習用方法,如第1 A及第1 B圖所示。所述方法 用在:^衣基體上使得無引線晶片載體封裝之多層晶 圓分裂。如圖示,多層晶圓丨具有前表面la及後表 面lb。切割刀片(未圖示)大致在前表面ia及後表面 lb內分別地形成v形槽溝。形成具有槽溝2a及2b 之晶圓通過分裂裝備(未圖示),其包括一對滾輪。滾 輪在晶圓1之槽溝2a及2b施加劈裂力量,因而使得 在封裝基體上之晶圓1分裂。 當分裂裝備使得晶圓1分裂時,使得前表面1 a之 槽溝2a在右及左方向中開啓之力量的力量如第iB 圖中箭頭Y所示地作用在槽溝2a。同時,槽溝2a及 2b允許晶圓1在預設方向中分裂。 槽溝2a及2b以半切割而不是全切割地形成在晶圓 1內。如果槽溝2a及2b沒有精確地對齊,則其產生 問題在於分裂裝備可能不能沿著連接槽溝1 a及1 b之 線來使得晶圓1分裂。明確地,可能晶圓1沿著第 1 B圖所示自槽溝i a延伸之虛點線2c來切割,而誤 失槽溝2b。結果,毛邊2d出現在所獲得晶片上,而 使得晶片沒有精確地安裝。 本發明第一至第三較佳實施例沒有上述問題,將参 照第2 A、2 B、3、4及5圖來詳細說明。第2 A圖表 示多層晶圓1,圖示實施例詳細說明。第2 B、3及4 1250568 五、發明説明(4) 圖分別表示是第一、第二及第三實施例之剖面圖。 簡略地,第一至第三實施各在封裝基體上使得用於 無引線晶片載體封裝P之晶圓分裂。大致v形槽溝 1 a形成在晶圓1之其一主表面或前表面。槽溝1 a在 晶圓1之厚度方向中延伸,即個別封裝P之切割端 P 1。弱劈裂部份形成在晶圓1之另一主表面或後表 面lb內’而且面對槽溝2a。如第5圖所示,劈裂力 量施加到晶圓1,使得在劈裂部份形成分裂。隨後, 晶圓1在晶圓1之厚度方向中自槽溝2a向劈裂部份 來分裂。 第5圖表示特定分裂裝備,包括一對滾輪6a及滾 輪6b。當晶圓1傳送在滾輪6a及滾輪6b間時,滾 輪6a及6b在箭頭γ所示方向中施加劈裂力量到晶 圓上。當然第5圖所示分裂裝備不是限定,而僅是圖 示說明。 明確地,在第2 B圖之第一實施例中,以槽溝3來 實施之劈裂部份,具有相對大寬度包括對槽溝2a之 對;in吳差如第5圖所示,當劈裂力量作用到晶圓i 時’其使得槽溝3裂開。然而,槽溝或劈裂部份3夠 弱且寬來形成裂隙3a,使得晶圓 裂隙^及槽溝2a之線來分裂。 〇者連接 在第3圖所示第二實施例中,劈裂部份以多數槽溝 相及413來實施,其大致和槽溝2a之形狀完全相同 ' 及4 b以鋸齒形式地邊靠邊來定位。再次如 1250568 j、發明説明(5 ) 第5圖所示,作用到晶圓1之 及4b裂開。然而,以槽溝4a 份夠弱而形成切口 4 c ’使得晶 裂隙4c及槽溝2a之線來分裂 進一步地,在第4圖所示第 以不同於晶圓1之熱膨脹係數 裂裝備使得晶圓1分裂時’熱 數之差異而作用在晶圓1及帶 ,在介面內形成裂隙5 a。因此 隙5 a及槽溝2 a之線來分裂。 如上所述,在第一至第三實 到晶圓1面對槽溝2a之弱劈藝 在劈裂部份內形成裂隙。裂隙 厚度方向中定位在槽溝2a之倡 圓1在預選方向中分裂且獲得 如果期望,第4圖所示帶部5 貫施。明確地,如第4圖所示 對齊槽溝2a而定位在晶圓1 5 中’如第5圖所示作用到晶圓 圓1及非劈裂帶部7間的介面 糸吉$ ’晶圓確實地沿著連接裂 分裂。在替代性架構中,非劈 0 ° Itt #劈裂部份也可以具有 係數之材料來替代,如果期望 劈裂力量使得槽溝4a 及4b來實施之劈裂部 圓1確實地沿著連接 〇 三實施例中,劈裂部份 的帶部5來實施。當分 應力因爲上述熱膨脹係 部5間的介面處。結果 ,晶圓可沿著連接裂 施例中,劈裂力量作用 ί部份,因而,確實地 因此精確地在晶圓1之 ί想延伸部。其允許晶 晶片沒有毛邊。 可以強且非劈裂部份來 ,強且非劈裂帶部7可 :後表面1 b上。本情形 1之劈裂力量集中在晶 ,因而形成裂隙7a。 隙7 a及槽溝2 a之線來 裂部份比較晶圓1更堅 不同於晶圓1之熱膨脹 如此。 l25〇568 i、發明説明(6 ) 如上述,在圖示實施例之修改例中,當劈裂力量作 用到晶圓1時,因爲在非劈裂部份及晶圓間之劈裂力 量的差異,而在強且非劈裂部份及晶圓i間之介面內形 成切口。因此,晶圓1精確地在預選方向中沿著封裝 p之切割點p 1自槽溝2 a向裂隙7 a來分裂。 總之,可見本發明提供一種製造半導體晶片之方法 ,能夠在預選方向中自其一主表面內所形成V形槽 溝向在另一主表面內所形成裂隙來使得晶圓分裂。 在理解本說明書之要旨後,擅於本技術者變成|胃 施各種修改例而沒有脫離本發明之範圍。 參考符號說明 1.....晶圓 1 a.....前表面 lb.....後表面 2 a , 2 b , 4 a,4 b.....槽溝 2 c.....虛點線 2d.....毛邊 4 c.....切口 6a,6b.....滾輪 7,5.....帶咅β 7a,3a.....裂隙 P.....封裝 PI.....切割端

Claims (1)

125^68 V六、申請專利範圍 第9 0 1 1 3 0 2 2號「製造半導體裝置的方法」專利案 (91年8月30日修正) 六申請專利範圍: 1 . 一種製造半導體裝置的方法,在封裝基體上使得用於 無引線晶片載體封裝之多層晶圓來分裂,該方法包含 下列步驟: 在該晶圓之厚度方向中,形成大致V形槽溝在該晶 圓的相對主表面之一內; @在該晶圓之另一主表面內形成對齊該槽溝的弱劈裂 部份;及 施加劈裂力量到該晶圓,因而在該劈裂部內形成裂 隙,因而使得該晶圓在該晶圓之厚度方向中自該槽溝 向該劈裂部來分裂,其中該劈裂部份包含槽溝,具有 相當大寬度包括相對該槽溝之對齊誤差。 2.—種製.造半導體裝置的方^法,在封裝基體上使得用於 無引線晶片載體封裝之多層晶圓來分裂,該方法包含 下列步驟: 在該晶圓之厚度方向中,形成大致V形槽溝在該晶 圓的相對主表面之一內; 在該晶圓之另一主表面內形成對齊該槽溝的弱劈裂 部份;及 施加劈裂力量到該晶圓,因而在該劈裂部內形成裂 隙,因而使得該晶圓在該晶圓之厚度方向中自該槽溝 1250568 六、申請專利範圍 向該劈裂部來分裂,其中該劈裂部份包含多數槽溝, 以鋸齒形式邊靠邊地來定位。 3 . —種製造半導體裝置的方法,在封裝基體上使得用於 無引線晶片載體封裝之多層晶圓來分裂,該方法包含 下列步驟: 在該晶圓之厚度方向中,形成大致V形槽溝在該晶 圓的相對主表面之一'內; 在該晶圓之另一主表面內形成對齊該槽溝的弱劈裂 部份;及 施加劈裂力量到該晶圓,因而在該劈裂部內形成裂 隙,因而使得該晶圓在該晶圓之厚度方向中自該槽溝 向該劈裂部來分裂,其中該劈裂部份包含不同於該晶 圓之熱膨脹係數的帶部。 4 · 一種製造半導體裝置的方法,在封裝基體使得用於無 引線晶片載體封裝之多層晶圓分裂,該方法包含下列 步驟: 在該晶圓之厚度方向中,形成大致V形槽溝在該晶 圓相對主表面之其一內; 在對齊該槽溝之晶圓另一主表面內形成強且非劈裂 部份;及 施加劈裂力量到該晶圓,因而,因爲該非劈裂部份 及該晶圓間之劈裂力量的差異,使得在該非劈裂部份 及該晶圓間之介面分裂,因而在該晶圓之厚度方向中
1250568 六、申請專利範圍 使得該晶圓自該槽溝向該非劈裂部份來分裂。 5 .如申請專利範圍第4項之方法,其中該非劈裂部份 包含比較該晶圓更強固之帶部。
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