TWI824936B - 半導體裝置的製造方法 - Google Patents

半導體裝置的製造方法 Download PDF

Info

Publication number
TWI824936B
TWI824936B TW112104840A TW112104840A TWI824936B TW I824936 B TWI824936 B TW I824936B TW 112104840 A TW112104840 A TW 112104840A TW 112104840 A TW112104840 A TW 112104840A TW I824936 B TWI824936 B TW I824936B
Authority
TW
Taiwan
Prior art keywords
wafer
semiconductor elements
groove
boundary
blade
Prior art date
Application number
TW112104840A
Other languages
English (en)
Other versions
TW202335076A (zh
Inventor
立花文人
Θ茶雅史
南雲裕司
Original Assignee
日商電裝股份有限公司
日商豐田自動車股份有限公司
日商未來瞻科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商電裝股份有限公司, 日商豐田自動車股份有限公司, 日商未來瞻科技股份有限公司 filed Critical 日商電裝股份有限公司
Publication of TW202335076A publication Critical patent/TW202335076A/zh
Application granted granted Critical
Publication of TWI824936B publication Critical patent/TWI824936B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/784—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/02—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills
    • B28D5/022—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills by cutting with discs or wheels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • Dicing (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Bipolar Transistors (AREA)
  • Perforating, Stamping-Out Or Severing By Means Other Than Cutting (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

在一種半導體裝置的製造方法中，製備其中形成有多個半導體元件(3)並且具有彼此對向的第一表面(2a)和第二表面(2b)之晶圓(2)，以及沿著該多個半導體元件中相鄰半導體元件之間的邊界(4)在該晶圓的該第一表面上形成凹槽(11)。以該晶圓的該第一表面面向支撐板(31)的方式將該晶圓附接到該支撐板，以及沿著該邊界將劃線刀片(33)壓靠在該晶圓的該第二表面上以沿著該邊界在該晶圓內側形成垂直裂縫(5)。然後，沿著該邊界將斷開刀片(34)壓靠在該晶圓上以沿著該邊界劈開該晶圓。

Description

半導體裝置的製造方法
本揭露係有關一種半導體裝置的製造方法。
半導體裝置的製造方法包含從其中形成有多個半導體元件的晶圓單獨切出半導體元件的製程。通常，晶圓已經被沿著相鄰半導體元件之間的邊界切割(切塊)。然而，近年來，開始採用稱為劃線和斷開製程的方法。
在劃線和斷開製程中，首先，沿著相鄰的半導體元件的邊界按壓劃線刀片(圓盤刀片)，以沿著該邊界在晶圓內部產生裂縫。由於裂縫在垂直於晶圓表面的方向上延伸，因此以下將裂縫稱為垂直裂縫。隨後，沿著邊界按壓斷開刀片以沿著邊界劈開晶圓。與傳統的切塊製程相比，劃線和斷開製程可以減小晶圓中相鄰半導體元件之間的寬度。
在劃線製程中，劃線刀片被強力壓靠在被附接在支撐板上的晶圓上。因此，如果異物存在於晶圓的後表面和支撐板之間，則晶圓可能被夾在異物和劃線刀片之間，並且晶圓可能非常局部地被強烈擠壓並損壞。本揭露提供一種即使異物進入晶圓和支撐板之間也限制或減少晶圓在劃線製程中的損壞的技術。
在根據本揭露的一個方面的半導體裝置的製造方法中，製備其中形成有多個半導體元件並且具有彼此對向的第一表面和第二表面之晶圓，以及沿著該多個半導體元件中相鄰半導體元件之間的邊界在該晶圓的該第一表面上形成凹槽。以該晶圓的該第一表面面向該支撐板的方式將該晶圓附接到支撐板，以及沿著該邊界將劃線刀片壓靠在該晶圓的該第二表面上以沿著該邊界在該晶圓內側形成垂直裂縫。然後，沿著該邊界將斷開刀片壓靠在該晶圓上以沿著該邊界劈開該晶圓。
在上述製造方法中，在與被劃線刀片按壓的第二表面對向的第一表面上形成凹槽。在劃線期間，即使異物直接進入相鄰半導體元件之間的邊界下方，異物也會進入凹槽。因此，晶圓不會牢固地被夾在劃線刀片和異物之間。即使晶圓與支撐板之間有異物進入，晶圓在劃線製程中也不會受到損傷(至少減少了損傷)。
可以藉由形成用於實現作為半導體元件(等)的功能之結構的製程來形成上述凹槽。例如，可以藉由在要形成半導體元件的區域中蝕刻而形成溝槽的製程來形成凹槽。氧化矽膜可以形成在凹槽的內表面上，並且可以在半導體元件上形成氧化矽膜的製程中形成氧化矽膜。可以在半導體元件上形成樹脂層的製程中形成凹槽。
將參照圖式描述實施方式的一種製造方法。圖1是晶圓2的平面視圖，其中多個半導體元件3被形成在 格柵圖案中。在圖1中，半導體元件3由實線矩形示意性地表示。一些實線矩形已省略了標號「3」。為了便於說明，作為相鄰的半導體元件3之間的邊界並且在稍後將晶圓2分割成單獨的半導體元件3時所使用的分界線被稱為劃線4。在圖1中，劃線4由長短交替的虛線表示。從晶圓2分離的每個半導體元件3對應於一個半導體裝置。半導體元件3是電晶體、二極體等具有功能的元件。
晶圓2的材料可以是SiC或GaN等半導體材料，但較佳是形成晶面的半導體材料。晶圓2被形成為使得晶面垂直於晶圓2的表面。半導體元件3被形成為使得劃線4(即，相鄰的半導體元件3之間的邊界)與在晶圓的平面圖中的晶面重合。
半導體裝置(即，半導體元件3)的製造方法將參考圖2至圖8進行描述，圖2至圖8繪示出沿著圖1的線II-II所截取的橫截面。為了便於說明，在半導體元件3中，將圖1中線II-II的左側上的半導體元件標記為3a，將位在圖1中線II的右側上的半導體元件標記為3b。本實施方式的製造方法包含凹槽形成製程、劃線製程、和斷開製程。
(凹槽形成製程)
將參照圖2至圖5描述凹槽形成製程。晶圓2具有彼此對向的第一表面2a與第二表面2b。在第一表面2a的表面部分中，形成有半導體元件3a和3b的主要結構，諸如閘極電極和通道之類。
在圖2的晶圓2的橫截面中，左虛線的左側上的區域是半導體元件3a，以及右虛線的右側上的區域是半導體元件3b。在半導體元件3a和3b中所形成的通道和閘極電極等主要結構(即，實現半導體元件3的功能所需的結構中的主要結構)未示出。上述劃線4位於半導體元件3a和半導體元件3b之間。劃線4在圖2和後續圖式中由交替的長短虛線指示。
在凹槽形成製程中，在晶圓2的形成有半導體元件3的第一表面2a中，沿著相鄰的半導體元件3a和3b的邊界(即，劃線4)形成凹槽11。圖2顯示了在形成凹槽11之前晶圓2的橫截面。在晶圓2的第一表面2a上進行諸如乾蝕刻的製程以沿著劃線4形成凹槽11(圖3)。用於形成凹槽11的乾蝕刻製程可以是用於在半導體元件3a和3b的區域中形成用於實現作為半導體元件3的功能的結構(例如，溝槽)的製程之一。因此，在半導體元件3a和3b的多個區域也形成有多個凹槽11。
接著，在第一表面2a上形成氧化矽膜21(圖4)。由於氧化矽膜21還具有半導體元件3a和3b的功能之一，所以氧化矽膜21也形成在半導體元件3a和3b上。半導體元件3a和3b的多個區域中的氧化矽膜21是為了使半導體元件3a和3b的多個表面層絕緣而設置的。氧化矽膜21也形成在凹槽11的內表面和底表面上。
接著，在氧化矽膜21上形成樹脂層22(圖5)。由於樹脂層22具有保護半導體元件3a和3b的表面的功能，所以樹脂層22也形成在半導體元件3a和3b上。然而，樹脂層22僅形成在凹槽11的外側。樹脂層22例如是聚醯亞胺或聚醯亞胺層。
靠近晶圓2的第一表面2a所形成的凹槽11具有大約10至100微米的寬度和大約5至50微米的深度。凹槽11的底表面是平坦的。
用於實現作為半導體元件3的功能之結構的製程來形成氧化矽膜21和樹脂層22。如上所述，氧化矽膜21被形成在凹槽11的內表面上。該氧化矽膜21可以在半導體元件3a和3b上形成氧化矽膜的製程中被形成。凹槽11的深度因樹脂層22而增加，以及樹脂層22可以在半導體元件3a和3b上形成樹脂層的製程中被形成。
(劃線製程)
在凹槽形成製程之後執行劃線製程。將參照圖6描述劃線製程。在劃線製程中，晶圓2以第一表面2a面向支撐板31的方式被附接到支撐板31。劃線刀片33沿著劃線4被壓靠在晶圓2的第二表面2b上，以在晶圓2內部沿著劃線4形成垂直裂縫5。
固定片32夾在晶圓2和支撐板31之間。當劃線刀片33沿著劃線4移動時，夾持固定片32以限制晶圓2移動。
劃線刀片33是圓盤狀的組件，並且由支撐設備(未顯示)樞軸支撐。劃線刀片33在壓靠在晶圓2上的同時沿著劃線4移動。在移動期間中，劃線刀片33像輪胎在路面上滾動一樣，在晶圓2上滾動而不滑動。雖然劃線刀片33具有鋒利的周邊邊緣，但劃線刀片33並不切割晶圓2，而僅壓靠在晶圓2的第二表面2b上。如上所述，劃線4沿著晶圓2的晶面延伸，以及當劃線刀片33強力壓靠在晶圓2上時，沿著劃線4在晶圓2內部產生垂直裂縫5。「垂直裂縫」是指垂直於晶圓2的表面2a、2b而延伸的裂縫。換句話說，垂直裂縫5沿著晶圓2的晶面延伸。
當用固定片32將晶圓2附接到支撐板31時，諸如灰塵的異物100可能會夾在晶圓2和支撐板31(固定片32)之間。如果在異物100夾在其間的狀態下將劃線刀片33用力壓靠在晶圓2上，則在異物100和劃線刀片33之間的晶圓2上會局部地集中極強的應力，並且可能損壞晶圓2。然而，在本實施方式的製造方法中，在晶圓2的面向支撐板31的第一表面2a上沿著劃線4形成凹槽11。因此，如圖6所顯示，異物100進入凹槽11。因此，晶圓2不會牢固地夾在劃線刀片33和異物100之間，並且可以限制晶圓2被嚴重損壞。
凹槽11的底表面的平整度也有助於減少對晶圓2的損傷。由於凹槽11的底表面是平坦的，所以晶圓2不會牢固地夾在已經進入的異物100和劃線刀片33之間。因此，可以限制晶圓2被嚴重損壞。當凹槽為V形時，凹槽的底部具有銳角。因此，如果在按壓劃線板33時異物接觸到凹槽的底部，則有可能從V形凹槽的底部產生新的裂縫。
(斷開製程)
斷開製程在劃線製程之後被執行。將參考圖7和圖8來描述斷開製程。在斷開製程中，斷開刀片34沿著劃線4被按壓以沿著劃線4劈開晶圓2。圖7顯示出了在斷開刀片34被按壓之前的橫截面。壓靠在晶圓2上的斷開刀片34由假想線(一長兩短交替的點劃線)畫出。圖8示出了在斷開刀片34被按壓並且被分成靠近半導體元件3a的區域和靠近半導體元件3b的區域之後沿著劃線4所劈開的晶圓2的橫截面。
斷開刀片34的長度等於晶圓2的直徑並且在劃線4的整個長度上壓靠在晶圓2上方。沿著晶圓2內部的劃線4形成垂直裂縫5。當斷開刀片34被強力壓靠在晶圓2上時，垂直裂縫5進一步擴展並且晶圓2沿著劃線4被劈開(見圖8)。在圖8中，垂直裂縫5的裂縫由標號「5a」表示。
注意，斷開刀片34壓靠在晶圓2的第二表面2b上。換句話說，斷開刀片34被壓靠在凹槽11的底表面上。
在斷開製程中，將晶圓2暫時從支撐板31上取下，並以第二表面2b面向支撐板31的方式貼附。此時，另一個固定片35夾在晶圓2和支撐板31之間(見圖7和圖8)。在斷開刀片34壓靠在晶圓2上時限制晶圓2從支撐板31上滑落。
如上所述，根據本實施方式的製造方法，凹槽11沿著劃線4被形成到晶圓2的第一表面2a，並且劃線刀片33在形成有凹槽11的第一表面2a面對支撐板31的狀態下壓靠在晶圓2上。藉由引入凹槽11，當劃線刀片33強力壓靠在晶圓2上時，不會發生由異物100所造成的損壞(至少減少了對晶圓2的損壞)。
請注意，劃線刀片33和斷開刀片34都不切割晶圓2。劃線刀片33在晶圓2內部產生垂直裂縫5，而斷開刀片34劈開晶圓2。
可以省略氧化矽膜21和樹脂層22中的至少一者或兩者。但是，形成凹槽11的製程、形成氧化矽膜21的製程、形成樹脂層22的製程都是製造半導體元件3的必要製程(用於實現如半導體元件3的功能之結構的製造製程)。因此，在以往的製造方法中追加沿著劃線4形成凹槽11的製程和形成氧化矽膜21及樹脂層22的製程，成本僅略有增加。
將描述關於本實施方式的技術的注意點。在本實施方式的製造方法中，在斷開製程中斷開刀片34被壓靠在第一表面2a上。斷開刀片34可被壓靠在第二表面2b上。劃線刀片33和斷開刀片34可由任何材質所製成和具有任何形狀只要能夠實現上述功能即可。
由於已經進入凹槽11的異物100被具有黏性的固定片32獲取，所以當固定片32從晶圓2上剝離時，異物100與固定片32一起從晶圓2上被移除。
垂直裂縫5可能到達晶圓2的第一表面2a和第二表面2b中的一個。
儘管上面已經詳細描述了本揭露的具體示例，但是這些僅僅是示例並且不限制請求項的範圍。本說明書中所描述的技術包含上述具體示例的各種變形。本說明書或圖式中所記載的技術元件單獨或以各種組合發揮技術上的有用性，並不限於申請時的本說明書中記載的組合。另外，本說明書或圖式所說明的技術可以同時實現多個目的，實現其中一個目的本身就具有技術上的實用性。
2:晶圓 2a:第一表面 2b:第二表面 3:半導體元件 3a:半導體元件 3b:半導體元件 4:劃線 5:垂直裂縫 5a:裂縫 11:凹槽 21:氧化矽膜 22:樹脂層 31:支撐板 32:固定片 33:劃線刀片 34:斷開刀片 35:固定片 100:異物
本揭露的上述及其他目的、特徵和優點，藉由參照附隨圖式進行的以下詳細描述，將變得更加明顯。在圖式中：[圖1]是晶圓的平面視圖；[圖2]是繪示凹槽形成製程的一部分的圖；[圖3]是繪示繼圖2所繪示的該部分之後的凹槽形成製程的一部分的圖；[圖4]是繪示繼圖3所繪示的該部分之後的凹槽形成製程的一部分的圖；[圖5]是繪示繼圖4所繪示的該部分之後的凹槽形成製程的一部分的圖；[圖6]是繪示劃線製程的圖；[圖7]是繪示斷開製程的一部分的圖；以及[圖8]是繪示繼圖7所繪示的該部分之後的斷開製程的一部分的圖。
2:晶圓 2a:第一表面 2b:第二表面 3a:半導體元件 3b:半導體元件 4:劃線 5:垂直裂縫 21:氧化矽膜 22:樹脂層 31:支撐板 32:固定片 33:劃線刀片 100:異物

Claims (4)

  1. 一種半導體裝置的製造方法，包括：製備其中形成有複數個半導體元件(3)並且具有彼此對向的第一表面(2a)和第二表面之晶圓(2)，以及沿著該複數個半導體元件中相鄰半導體元件之間的邊界(4)在該晶圓的該第一表面上形成凹槽(11)；以該晶圓的該第一表面面向支撐板(31)的方式將該晶圓附接到該支撐板，以及沿著該邊界將劃線刀片(33)壓靠在該晶圓的該第二表面上以沿著該邊界在該晶圓內側形成垂直裂縫(5)；以及沿著該邊界將斷開刀片(34)壓靠在該晶圓上以沿著該邊界劈開該晶圓，其中該形成該凹槽是在形成用於實現作為該複數個半導體元件的功能之結構的製程中所執行的。
  2. 如請求項1之製造方法，其中該形成該凹槽是藉由在其中該複數個半導體元件被形成的區域中蝕刻來形成溝槽的製程中所執行的。
  3. 如請求項1之製造方法，進一步包括在形成在該複數個半導體元件上的氧化矽膜(21)的製程中，在該凹槽的內表面上形成該氧化矽膜。
  4. 如請求項1之製造方法，其中該形成該凹槽是在該複數個半導體元件上形成樹脂層(22)的製程中所執行的。
TW112104840A 2022-02-24 2023-02-10 半導體裝置的製造方法 TWI824936B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022027109A JP2023123189A (ja) 2022-02-24 2022-02-24 半導体装置の製造方法
JP2022-027109 2022-02-24

Publications (2)

Publication Number Publication Date
TW202335076A TW202335076A (zh) 2023-09-01
TWI824936B true TWI824936B (zh) 2023-12-01

Family

ID=87574497

Family Applications (1)

Application Number Title Priority Date Filing Date
TW112104840A TWI824936B (zh) 2022-02-24 2023-02-10 半導體裝置的製造方法

Country Status (4)

Country Link
US (1) US20230268230A1 (zh)
JP (1) JP2023123189A (zh)
CN (1) CN116646243A (zh)
TW (1) TWI824936B (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140017837A1 (en) * 2012-07-13 2014-01-16 Samsung Electronics Co., Ltd. Method of cutting silicon substrate having light-emitting element package
TW201603981A (zh) * 2014-06-26 2016-02-01 Mitsuboshi Diamond Ind Co Ltd 脆性基板之切斷方法及劃線裝置
TW201941365A (zh) * 2014-05-30 2019-10-16 日商三星鑽石工業股份有限公司 脆性基板之裂縫線之形成方法及脆性基板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140017837A1 (en) * 2012-07-13 2014-01-16 Samsung Electronics Co., Ltd. Method of cutting silicon substrate having light-emitting element package
TW201941365A (zh) * 2014-05-30 2019-10-16 日商三星鑽石工業股份有限公司 脆性基板之裂縫線之形成方法及脆性基板
TW201603981A (zh) * 2014-06-26 2016-02-01 Mitsuboshi Diamond Ind Co Ltd 脆性基板之切斷方法及劃線裝置

Also Published As

Publication number Publication date
TW202335076A (zh) 2023-09-01
CN116646243A (zh) 2023-08-25
JP2023123189A (ja) 2023-09-05
US20230268230A1 (en) 2023-08-24

Similar Documents

Publication Publication Date Title
KR101160316B1 (ko) 점진적인 트리밍 방법
TWI484544B (zh) 使半導體片變薄的方法
US20110108957A1 (en) Semiconductor substrate, semiconductor device and method of manufacturing the same
JP4198966B2 (ja) 半導体装置の製造方法
JP2861991B2 (ja) 窒化ガリウム系化合物半導体チップの製造方法
TW201630065A (zh) 半導體物件之製造方法
US20080227234A1 (en) Method of manufacturing a semiconductor device
JP3395620B2 (ja) 半導体発光素子及びその製造方法
TWI824936B (zh) 半導體裝置的製造方法
TWI696228B (zh) 基板之分斷方法及分斷裝置
JP4258099B2 (ja) 半導体圧力センサの製造方法
JPH07142763A (ja) 窒化ガリウム系化合物半導体チップの製造方法
JP3276506B2 (ja) 半導体装置の製造方法
US20230268185A1 (en) Manufacturing method of semiconductor device
JPH11233459A (ja) 半導体装置の製造方法
JP2008034875A (ja) 半導体装置及びその製造方法
US20240162092A1 (en) Manufacturing method of semiconductor device
US20240030056A1 (en) Manufacturing method of semiconductor device
US11646392B2 (en) Method of manufacturing light-emitting device
US20240112928A1 (en) Trimming method
JP6175156B2 (ja) 基板の分断装置
JPH03159153A (ja) 半導体基板の分割方法
CN117476740A (zh) 半导体装置及其制造方法
JP2004273737A (ja) 半導体チップの製造方法
JPH03214757A (ja) 半導体装置の製造方法