TWI244682B - A method for forming a sublithographic opening in a semiconductor process - Google Patents

A method for forming a sublithographic opening in a semiconductor process Download PDF

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Publication number
TWI244682B
TWI244682B TW092124742A TW92124742A TWI244682B TW I244682 B TWI244682 B TW I244682B TW 092124742 A TW092124742 A TW 092124742A TW 92124742 A TW92124742 A TW 92124742A TW I244682 B TWI244682 B TW I244682B
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layer
opening
lithographic
lithographic opening
sacrificial
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TW092124742A
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TW200416818A (en
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Gian Sharma
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Silicon Storage Tech Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Description

1244682 一微影開口生出妖 、， 少 战於可犧牲層的第一層中而在其中形成一微 影開口。與第_ ,, 〜—材料不同之第二層的第二材料係貼附地沉 積在第一層上。哲— 弟二層的第二材料隨後被異向性蝕刻，直 至!抵達第—層為止。這在第一層的開口中生成了由第二材 5 =製成的間隔件。第一層的開 口中之間隔件係減小開口的 尺寸2以生成一次微影開口。隨後使用第一層的第一材料 連同第二材料的間隔件作為一遮罩層，以在可供第一層沉 積之層中生成次微影開口。譬如請見usp 6,362，117號。然 而此製需要使用兩層不同材料來形成一可犧牲遮罩 i有關於在半導體結構中生成次微影結構之方法亦請見 ’，451，M13,8G2 ; 6,429，125及6,423,475號。 【】 發明概要 15 μ旦， 導體製程中用於在第—層的第—材料中形成 之方法係包含在第-層上生成-微影開口。微 二二:所需要的次微影開口位置上方。微影開口中的 也”精地移除。將—可犧牲層對於第-層輪靡貼附 第上方，包括微影開口上方。可犧牲層亦由 -卿Η πΓ可犧牲層及第—層被異向性侧直到來自 -人値衫開口的所有材料 成次微影開口。 — 4除為止’以在微影開口内形 元件中用於在第一層 。此方法中，將一可 一微影開口生成於可 本發明亦有關於另-種在半導體 的第一材料中形成次微影開口之方法 犧牲層的第—材料沉積在第—層上。 20 !244682 斗斗^1* I** Q ^ 山々 ^ 曰 饿Θ開口定位在所需要的次微影開口位置上 t °在微影開口中移除第一材料。藉由使第一材料轉換成 第二材料今筮 7乐〜材料隨後側向擴張，故將微影開口的尺寸 減小至一次微影開口。隨後利用第二材料作為一遮罩層來 蝕刻第層，以在第一層中形成次微影開口。 圖式簡單說明 第1a-ig圖為本發明之一種在半導體製程中用於在第 層的第材料中形成次微影開口之方法的橫剖視圖； 10 15 20 第2a 2f圖為本發明之另一種在半導體製程中用於在第 S的第#料中形成次微影開口之方法的橫剖視圖。 C實冷式】 較佳實施例之詳細說明 “、、第’顯示—通常由單晶⑦製成之半導體基材 10的橫剖視圖。其 ^ 土材10中故置有特定數量的淺溝道隔離部 _…第1a lg圖描述用於形成次微影開Π之製程，圖中 :Γ浮間形成於基材10上方。然而，熟習該技術者瞭解 /明不限於形成浮間。而是，用於形成次微影開口之本 务明可由任何材料 將第Μ 顿離部12是否存在無關。 將弟-層的氣化石夕或二氧 材10的一第一表 （0矣左右)形成於基 、貝表面）上。譬如可藉由 Α 藉由將矽熱性轉換成二氧化矽 予軋相沉積或 氧化石夕層14(下文用（ 纽作用。最後，（二） 為_合氧化物。將第層及二氣化石夕)作 左右)沉積在㈡氧切 日日轉晶外(6〇〇埃 曰。言如，可藉由電黎增強沉 1244682 積法或藉由將石夕的化合物還輪之 用。如下文所使用，將以多晶亀非晶作 5 10 15 埃左右)貼附地㈣在Π:6 如二二=_增強， 卜 4夕的化合物及如ΝΗ3等其他氣體 鼠化石夕層18之高溫方法來達成此彻。所有 4 皆為=技術_知。所產生的結構顯示於第㈣^積製程 -的—層的多晶抑⑽埃左右攸積在第la圖所 =?，層18的頂部上。所產生的結構顯示於 田可猎由諸如將石夕的氣態化合物予以還原等傳統 習知技術來沉積第二層20的多晶矽。 、 隨後將光阻2 2施加橫越第！ b圖的結構且在其中形 影開口 2 4。微影開° 2 4係形成於終將在第-層i 6多晶㈣ 構成次«f扣之位置巾。_熟知的纽暴光及移除技 術’形成微影開口 24。所產生的結構顯示於第1(：圖中。 利用光阻22作為遮罩，隨後使用諸如以氮化石夕作為餘 刻阻止部之RIE異向性姓刻等熟知的技術來移除開口 24中 暴硌之第一層多晶矽20。第二層20多晶矽繼續進行異向性 姓刻’直到氮化矽層18暴露為止。所產生的結構顯示於 弟1 d圖中。 隨後移除光阻22。這導致了具有微影開口 24之第二層 多晶矽20。所產生的此結構顯示於第le圖中。 第le圖所示的結構隨後係氧化或放置在諸如單獨存在 的〇2或Η?與Ο:的混合物等氧化大氣中。這造成第二層20多 20 1244682 ==(Γ氧7。如同熟知般地，因為(二咖 、土成大的刀子尺寸，多㈣2G轉換成㈡氧化石夕將 k成間隔或開口 24收縮。這是 ,^ ^ 由於一）虱化矽在形成時的側 向擴張所致。結果’隨後生 構顯示於第lf圖中。成一人“開口。所產生的結 利用（一)乳化石夕層20作為遮罩層，然後使用異向性钱刻 來關氮切層18及多晶Μ.所產生的結構顯示於第 lg圖中，其中將次微影開口生成在氮切層财多晶抑 16中。 日 1〇隨後，可移除㈡氧化石夕⑽的遮罩層，亦可移除氮化 石夕層…導致具有次微影開ϋ24之第_層16多晶石夕。 m2a圖，顯示另一種在半導體製程中用於在—材 料中生成-次微影開口之方法的第一步驟之橫剖視圖。類 似於第la圖所示的橫剖視圖，此製程開始時係為具有溝槽 15隔離部12之單晶矽10的一半導體基材。並且，然而，溝道 隔離部12只供示範使用，目時第2以圖顯示在一鋪覆於淺 溝道隔離部12區上方之結構中生成一多晶矽浮閘之製程。 然而，本發明的方法不在此限且可用來在一半導體製程中 對於任何目的在任何材料中生成次微影開口。 20 第一層的（二）氧化矽14隨後沉積在基材10的表面上。這 可為50埃左右的一層且可由諸如化學氣相沉積或高溫熱沉 積等熟知的傳統技術製成。所產生的結構顯示於第2b圖中。 第一層20的多晶矽隨後貼附地沉積在第2b圖所示的結 構輪廓上方。第一層的多晶矽2〇a可由諸如化學氣相沉積等 1244682 傳統技術加以沉積且可沉積至1000埃的厚度。所產生的結 構顯示於第2c圖中。 利用習知的光阻22(如第lc及Id圖所示），一微影開口 24 生成在第一層20a的多晶矽中。然而，第一層的多晶矽20a 5 未完全地自微影開口 24移除或從蝕刻。在較佳實施例中， 從開口 24移除多晶矽20a的約90%厚度。在第一多晶矽層20a 中生成一微影開口 24之製程係導致微影開口 24中殘留的多 晶石夕，如第2d圖所示。 與第一層20a具有相同材料之第二層20b多晶矽隨後係 10 貼附地沉積至弟-^層20a多晶碎的輪靡。弟》一層20b的多晶 矽係為450埃左右且可由化學氣相沉積予以沉積。沉積製程 的結果係為第2e圖所示的結構。隨後，第2e圖所示的結構 係異向性蝕刻直到從開口 24蝕刻所有多晶矽為止。此蝕刻 製程係造成多晶矽20a以及來自於沉積在微影開口 24中之 15 第二層20b的多晶矽被移除。然而，將一數量多晶矽20b繼 續襯墊於開口 24的側壁以生成一次微影開口 24。所產生的 結構顯示於第2f圖中。 【圖式簡單說明】 第la-lg圖為本發明之一種在半導體製程中用於在第 20 —層的第一材料中形成次微影開口之方法的橫剖視圖； 第2a-2f圖為本發明之另一種在半導體製程中用於在第 一層的第一材料中形成次微影開口之方法的橫剖視圖。 10 1244682 【圖式之主要元件代表符號表】 10…半導體基材 12…淺溝道隔離部 14…第一層的氧化矽或二氧化矽 16…第一層的多晶石夕或非晶石夕 18…氮化石夕層 20···第二層的多晶矽 20a…第一層的多晶石夕 20b…第二層的多晶矽 22···光阻 24···開口
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Claims (1)

  1. !244682 拾、申請專利範圍： 1.=種在半導體製程中用於在—第—層的—第一材料中 形成一次微影開口之方法，該方法包含： 在邊第-層中生成-微影開口，該微影開口位於該 所需要的次微影開口的位置上方； 在该微影開口中部份地移除該第一材料； 一可犧牲層對於該第—層輪廓職地沉積在該第 -層上方’包括該微影開口上方；該可犧牲層由該第一 材料製成；及 異向性餘刻該可犧牲層及該第一層以在該微影開 口内形成該次微影開口。 2·如申請專利範圍第1項之方法，其中該生成步驟進 包含： 15 20 將一層光阻沉積在該第一層上； 暴光该層光阻以在該所需要的次微影開口的位置 上方形成-包含一潛在微影開口之潛在影像；及 在該微影開口 一層。 中完全地移除該光阻，藉以暴露該第 3·如申請專利範圍第2項之方法，進—步包含： ^亥礼移除步驟之後及該可犧牲層的該沉積步 驟之前，移除所有該光阻。 其中該第一材料為多晶 4·如申請專利範圍第3項之方法 矽或非晶矽。 5. -種在半導體製財料在m第—材料中 12 1244682 形成一次微影開口之方法，該方法包含： 在該第一層上沉積—可犧牲層的一第一可犧牲材 料； 5 在該所需要的次微影開口的位置上方； 在該微影開口中移除該第—可犧牲材料； …將β第可犧牲材料轉換成—第二可犧牲材料令 乂第可犧牲材料側向擴張，故使該微影開口的尺寸 小至一次微影開口；及 / 10 利用該第二可犧牲材料作為—遮罩層來㈣該第 ^以在4第-層中形成該次微影開口。 6. 2請專利範圍第5項之方法，其中該生成步驟進-步 15 上方=該^阻以在該所需要的次微影開口的位置 方:成：包含—潛在微影開口之潛在影像，·及 層。 “亥先阻，糟以暴露該可犧牲 7.如申請專利範圍第6項之方法，進—步包含·· 20 在該移除步驟之後及該擴 光阻。 之則，移除所有該 8_如申請專利範圍第7項之方法 為石夕、多晶石夕或非晶石夕。…弟-可犧牲材料 9·如申請專利範圍第8項之方法， 化該第—可犧牲材料以產生㈡氧步驟包含氧 13 1244682 10.如申請專利範圍第9項之方法，其中該第一層為一包含 一層多晶矽及一層氮化矽之複合層，且使該氮化矽緊鄰 該可犧牲層。
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TW092124742A 2002-09-18 2003-09-08 A method for forming a sublithographic opening in a semiconductor process TWI244682B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/247,400 US6756284B2 (en) 2002-09-18 2002-09-18 Method for forming a sublithographic opening in a semiconductor process

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TW200416818A TW200416818A (en) 2004-09-01
TWI244682B true TWI244682B (en) 2005-12-01

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US (1) US6756284B2 (zh)
JP (1) JP2004111970A (zh)
KR (1) KR20040025613A (zh)
CN (2) CN1326211C (zh)
TW (1) TWI244682B (zh)

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US6806204B1 (en) * 2003-06-30 2004-10-19 Intel Corporation Semiconductor etch speed modification
US7151040B2 (en) * 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7910288B2 (en) * 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7655387B2 (en) * 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7115525B2 (en) * 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
US7253118B2 (en) * 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7390746B2 (en) * 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
US7120046B1 (en) * 2005-05-13 2006-10-10 Micron Technology, Inc. Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US7371627B1 (en) 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7695632B2 (en) * 2005-05-31 2010-04-13 Lam Research Corporation Critical dimension reduction and roughness control
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7396781B2 (en) * 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7541632B2 (en) * 2005-06-14 2009-06-02 Micron Technology, Inc. Relaxed-pitch method of aligning active area to digit line
US7888721B2 (en) * 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) * 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7413981B2 (en) * 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US8123968B2 (en) * 2005-08-25 2012-02-28 Round Rock Research, Llc Multiple deposition for integration of spacers in pitch multiplication process
US7816262B2 (en) * 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7696567B2 (en) * 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7829262B2 (en) * 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7759197B2 (en) 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7687342B2 (en) * 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7776744B2 (en) * 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7572572B2 (en) * 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7557032B2 (en) * 2005-09-01 2009-07-07 Micron Technology, Inc. Silicided recessed silicon
US7416943B2 (en) * 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US7476933B2 (en) * 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7842558B2 (en) * 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
US7902074B2 (en) 2006-04-07 2011-03-08 Micron Technology, Inc. Simplified pitch doubling process flow
US8003310B2 (en) 2006-04-24 2011-08-23 Micron Technology, Inc. Masking techniques and templates for dense semiconductor fabrication
US7488685B2 (en) * 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
US7795149B2 (en) 2006-06-01 2010-09-14 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US7723009B2 (en) 2006-06-02 2010-05-25 Micron Technology, Inc. Topography based patterning
US7611980B2 (en) 2006-08-30 2009-11-03 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7517804B2 (en) 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
US7666578B2 (en) 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8563229B2 (en) 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US20090102023A1 (en) * 2007-10-19 2009-04-23 Stephan Wege Method for Manufacturing a Structure, Semiconductor Device and Structure on a Substrate
US7737039B2 (en) 2007-11-01 2010-06-15 Micron Technology, Inc. Spacer process for on pitch contacts and related structures
US7659208B2 (en) 2007-12-06 2010-02-09 Micron Technology, Inc Method for forming high density patterns
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US8030218B2 (en) 2008-03-21 2011-10-04 Micron Technology, Inc. Method for selectively modifying spacing between pitch multiplied structures
US8076208B2 (en) 2008-07-03 2011-12-13 Micron Technology, Inc. Method for forming transistor with high breakdown voltage using pitch multiplication technique
US8119528B2 (en) * 2008-08-19 2012-02-21 International Business Machines Corporation Nanoscale electrodes for phase change memory devices
US8101497B2 (en) 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
US8492282B2 (en) 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
CN102044497B (zh) * 2009-10-13 2013-07-17 中芯国际集成电路制造(上海)有限公司 分立栅存储器件的形成方法
US8728859B2 (en) * 2010-08-12 2014-05-20 International Business Machines Corporation Small footprint phase change memory cell
FR2998417A1 (fr) * 2012-11-16 2014-05-23 St Microelectronics Rousset Procede de realisation d'un element pointu de circuit integre, et circuit integre correspondant

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5004703A (en) * 1989-07-21 1991-04-02 Motorola Multiple trench semiconductor structure method
JP2641781B2 (ja) * 1990-02-23 1997-08-20 シャープ株式会社 半導体素子分離領域の形成方法
JP2608513B2 (ja) * 1991-10-02 1997-05-07 三星電子株式会社 半導体装置の製造方法
US5372968A (en) * 1993-09-27 1994-12-13 United Microelectronics Corporation Planarized local oxidation by trench-around technology
US5378646A (en) * 1994-07-07 1995-01-03 United Microelectronics Corporation Process for producing closely spaced conductive lines for integrated circuits
US5605864A (en) * 1994-08-02 1997-02-25 Micron Technology, Inc. Method for forming a semiconductor buried contact with a removable spacer
KR100190010B1 (ko) * 1995-12-30 1999-06-01 윤종용 반도체 소자의 소자분리막 형성방법
US5821160A (en) * 1996-06-06 1998-10-13 Motorola, Inc. Method for forming a laser alterable fuse area of a memory cell using an etch stop layer
US5843625A (en) * 1996-07-23 1998-12-01 Advanced Micro Devices, Inc. Method of reducing via and contact dimensions beyond photolithography equipment limits
US6316807B1 (en) * 1997-12-05 2001-11-13 Naoto Fujishima Low on-resistance trench lateral MISFET with better switching characteristics and method for manufacturing same
US6271577B1 (en) * 1997-12-17 2001-08-07 Texas Instruments Incorporated Transistor and method
US6040214A (en) * 1998-02-19 2000-03-21 International Business Machines Corporation Method for making field effect transistors having sub-lithographic gates with vertical side walls
US6362117B1 (en) * 1998-08-04 2002-03-26 Texas Instruments Incorporated Method of making integrated circuit with closely spaced components
US6423475B1 (en) * 1999-03-11 2002-07-23 Advanced Micro Devices, Inc. Sidewall formation for sidewall patterning of sub 100 nm structures
US6232229B1 (en) * 1999-11-19 2001-05-15 Micron Technology, Inc. Microelectronic device fabricating method, integrated circuit, and intermediate construction
US6271094B1 (en) * 2000-02-14 2001-08-07 International Business Machines Corporation Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

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