TWI242238B - Manufacturing method for dual gate oxide layer - Google Patents

Abstract

This invention provides a manufacturing method for dual gate oxide layer including the steps of: providing a substrate with an isolated structure to define an active area; forming a first insulated layer on the substrate; forming a patterned photoresist layer to cover the isolated structure and the first area section of the first insulated layer, exposing the second area section of the first insulated layer; removing the second area section to expose the substrate by using photoresist layer as mask; exposing the first area section and the isolated structure by removing the photoresist layer; forming a second insulated layer and a conductive layer in order on the substrate and the first area section; and etching the conductive layer and the second insulated layer to form a gate structure on the substrate. This invention can improve the excessive etching of the insulated structure, reduce the loss of substrate and decrease the probability of leakage current.

Description

1242238 V. Description of the invention (1) Field of the invention The invention relates to a semiconductor system related to the manufacturing method of a double gate oxide layer (dua ^ element; specifically gate ox i de). Background of the invention The device (loglc device) and the peripheral device (PeriPheral device) are respectively formed on different wafers and then set on the same stack. However, the structures of logic elements and peripheral elements formed on different wafers often cannot guarantee the high speed. In order to improve the operating speed of components, logic components and peripheral components are often mixed and manufactured on the same chip. Such mixed-set components are called embedded semiconductor devices «^ eRAM (embedded Random Access Memory) ° Generally, The gate oxide layer of the transistor in the logic element area needs to be thinner to improve the driving ability of the transistor, while the transistor in the peripheral element area, such as the memory element area, needs a thicker gate oxide layer to avoid For example, an electrical break down phenomenon caused by a supply voltage of 5.5 volts. Therefore, such embedded semiconductor devices require dual gate oxides, that is, gate oxides with different thicknesses. The following reference is made to Figs. 1A to 1F, which show cross-sectional views of a conventional manufacturing method for forming a double-gate oxide layer. First, please refer to FIG. 1A, and provide a Shi Xi substrate 10, which is formed with a shallow trench isolati () n (STI) composed of silicon dioxide to isolate the active area. The silicon substrate 10 has a source 1242238.

V. Description of the invention (2) or non-polarly doped region 2. Next, a first insulating layer 4 made of an oxide is formed on the Shi Xi substrate 10 in a comprehensive manner by a thermal growth method. Furthermore, please refer to Figs. 1A and 1B. The first photoresist mask 15 is formed by a photolithography method, and the active area is engraved with a wet-type wet engraving method The first insulating layer 1 4. Then, referring to FIG. 1C, a second insulating layer 16 made of a thin oxide is formed on the surface of the silicon substrate 10. Next, referring to FIG. D and FIG. E, a polysilicon layer 18 is deposited on the second insulating layer, and the position of the gate electrode 18a is defined by a second photoresist mask (not shown). And the wet etching of hydrofluoric acid is used to selectively etch the polycrystalline silicon layer 8 and the second insulating layer 6 which are not covered by the photoresist. After the money engraving is completed, the photoresist mask is removed, and subsequent lightly doped drain ion implantation and formation of composite spacers can be performed, and finally formed as in FIG. 1F ^ Structure shown. In the conventional manufacturing method, the active area is used as a landmark, and the unmasked area of the first photomask is larger than the active area, that is, it includes shallow trench spacers. Therefore, when the first insulating layer is etched, the polycrystalline silicon layer is etched with When the second insulating layer is used, the edges of the shallow trench spacers are over-etched, and the self-aligned salicide is filled into the edges due to the over-etched edges, and the self-aligned silicide in the deep is self-aligned. It is very likely to cause a leakage current. In addition, in current semiconductor device manufacturing methods, the gate oxide layer is usually less than 50 angstroms in thickness. Therefore, when the polycrystalline silicon layer and the insulating layer in the gate electrode region are removed, over-etching often occurs.

0503-7091TWF (N); TSMC2001-0991; Chiumeow.ptd

1242238 V. Description of the invention (3) Oxidation layer, which damages the manufacturing method will be more serious. On the question. DETAILED DESCRIPTION OF THE INVENTION The purpose of the present invention includes the following steps to define a first and second region adjacent to a main patterned photoresist; using the substrate; removing the sequentially forming a second upper; And defining an etched electrode structure to expose a side wall of the double-gate gate structure between the first and second double-gate regions of the substrate, the double-gate pole is smaller than the first insulated double-gate grooved spacer. The following silicon substrate will face the shortcomings of the conventional technology on the surface, so that the shortcomings will be adjusted later, so that the leakage current is what the present invention intends to solve is to provide a moving area; Layer, photoresist layer, cladding layer, photoresist layer, insulation layer, etc. The oxide layer has the base oxide layer and the edge layer of the oxide layer. Oxide layer The oxide layer provides a double base, which forms a first cover, the first region of the isolation junction, as a mask, to expose the first and first conductive layers and the manufacturing method of the bottom. Manufacturing method on the substrate. Manufacturing method Manufacturing method Manufacturing method Gate oxide manufacturing method The substrate has an isolation structure, an insulating layer on the substrate; a shape, and the isolation structure exposes the first insulating layer except the second region Part to expose a region and the isolation structure; two insulating layers on the base and the first region to form a gate, the gate structure and the first 'form a gap wall in the middle' the first The thickness of the two insulating layers is' the substrate is a silicon substrate. Middle ’the isolation structure is a shallow trench

1242238

4 Isolation structure is partial 5. Explanation of the invention (4) Silicon oxide in the manufacturing method of the above-mentioned double-gate oxide layer. The insulating layer is formed by removing a conductive layer from a conductive layer, and an oxide layer in the manufacturing method of the double-gate oxide layer described above. In addition, in the above-mentioned manufacturing method of the double-gate oxide layer, the second region of the edge layer is wet etching using hydrofluoric acid. Furthermore, in the above-mentioned method for manufacturing the double-gate oxide layer, a polycrystalline silicon layer is used. Moreover, in the above-mentioned method for manufacturing the double-gate oxide layer, the one-pole structure further includes the following steps: defining a patterned photoresist layer and a predetermined area of the armored structure; wet-etching the uncovered area with hydrofluoric acid; The above photoresist layer. In addition, in the manufacturing method of the above-mentioned double-gate oxide layer, after forming the gate electrode, the lightly dQped drain ion implantation can be performed next, and the aforementioned composite spacer (c⑽p〇) is formed. site spacer) and other steps, the composition spacer may be a combination of two or three layers of an oxide layer and a nitride layer. EXAMPLES The following 'refer to Figures 2A to 2F, which show a preferred embodiment of the present invention. This example uses the manufacturing process of a double-layered gate oxide layer as an example to illustrate the technology of the present invention. First, referring to FIG. 2A, a stone evening substrate 100 is provided, and a shallow trench spacer STI made of silicon dioxide is formed to define an active region. Of course, the local trench oxide (LOCOS) can also be used to replace the shallow trench isolation.

0503-7091BfF (N); TSMC2001-0991; Chiumeow.ptd

1242238 V. Description of the invention (5) Isolate object \ ΤΙ. Next, a first insulating layer 104 made of, for example, an oxide is formed on the silicon substrate. The first insulating layer may be formed by chemical vapor deposition (CVD) or high temperature. The thermal oxidation method is comprehensively formed, and the thickness of the first insulating layer is 30 to 100 angstroms. Then, according to FIGS. 2A ′ and 2B, a patterned photoresist layer j 〇5 ′ is formed to cover the shallow trench spacer and the first region 104b of the adjacent first insulating layer, and The second region portion 104a of the first insulating layer is exposed, and a hydrofluoric acid acid pattern is used to remove the exposed second region portion 104a of the first insulating layer. Furthermore, referring to FIG. 2C, after the photoresist layer is removed, a second insulating layer 106 made of a thinner oxide than the first insulating layer is formed on the surface of the silicon substrate, and the thickness is 10 to 30. Aye. Then, referring to FIG. 2D, a polysilicon layer 108 is deposited on the second insulating layer 106. The polycrystalline silicon layer 108 can be deposited by low pressure chemical vapor deposition (LPCVD) between 525 and 575 ° C, and its thickness preferably ranges from 100 to 500 angstroms. For NMOS devices, it is possible to add in-situ doped hydrogen (phosphine) or trisine (ar si ne) to the stone sintering gas at 108 when the polycrystalline spar layer is deposited, or doped in-situ, or, The polycrystalline stone layer is deposited first after 108, and then ion implantation is performed by filling ions or kun ions. The implantation energy range is about 25 ~ 75KeV, and the implantation concentration range is about 1E14 ~ 1E16 atoms / cm2. Next, referring to FIG. 2E, a mask with a gate pattern is formed by conventional lithography and etching to cover the predetermined gate electrode 108a position, which includes a hard mask, an anti-reflection layer at the bottom, and a photoresist layer. . Rigid screen

〇503-7091TW (N); TSMC2001-0991; Chiumeow.ptd Page 8 1242238 V. Description of invention (7) The scope shall be determined by the scope of the attached patent application.

Hi 0503-7091TWF (N); TSMC2001-0991; Chiumeow.ptd page 10

Claims (1)

I242238-Case No. 91104625 Amendment to C ~ C of the year + ·… Applicable patent range jg, also 1 · A method for manufacturing a double gate oxide layer, including the following steps: · A substrate is provided, the substrate has an isolation structure, and To define a first insulating layer actively formed on the substrate; forming a patterned photoresist layer covering the isolation structure and the first region of the first insulating layer adjacent to the isolation structure, and Exposing the second region of the first insulating layer; using the photoresist layer as a mask, removing the second region to expose the substrate within the active region of the portion; removing the photoresist layer to expose the The first region and the isolation structure; _ sequentially forming a second insulating layer and a conductive layer on the exposed substrate and the first region; and ^ defining the conductive layer and the second insulating layer to form A gate structure is on the exposed substrate. 2. The method for manufacturing a double-gate oxide layer according to item 1 of the scope of the patent application, wherein the substrate is exposed between the gate structure and the first region. 3. The method for manufacturing a double-gate oxide layer as described in item 2 of the scope of the patent application, wherein a spacer is formed on a side wall of the gate structure and on the substrate. 4. The method for manufacturing a double-gate oxide layer according to item 1 of the scope of patent application, wherein the thickness of the second insulating layer is smaller than that of the first insulating layer. 5. The manufacturing method of the dual-gate oxide layer according to item 4 of the scope of the patent application, wherein the thickness of the first insulating layer is 30 to 100 angstroms, and the thickness of the second insulating layer is 10 to 30 angstroms. 0503-7901TWF2 (2) .ptc Page 12 2005. 05. 09. 013 1242238 _Case No. 91104625_ Month and Day__ VI. Application for patent scope 6. Double gate oxidation as described in item 1 of patent scope A method for manufacturing a layer, wherein the substrate is a silicon substrate. 7. The method for manufacturing a double-gate oxide layer as described in item 1 of the patent application scope, wherein the isolation structure is a shallow trench spacer. 8. The method for manufacturing a double-gate oxide layer as described in item 1 of the patent application scope, wherein the isolation structure is a local silicon oxide. 9. The method for manufacturing a double-gate oxide layer as described in item 1 of the scope of patent application, wherein the insulating layer is an oxide layer. 10. The method for manufacturing a double-gate oxide layer as described in item 1 of the scope of the patent application, wherein removing the second region of the first insulating layer is performed using a hydrofluoric acid wet type. 11. The method for manufacturing a double-gate oxide layer according to item 1 of the scope of the patent application, wherein the conductive layer is a polycrystalline silicon layer. 1 2. The method for manufacturing a double-gate oxide layer as described in item 1 of the patent application scope, wherein forming the gate structure further comprises: forming a patterned photoresist layer covering a predetermined area of the gate structure, and using hydrofluoric acid The uncovered area is wet-etched, and the gate structure is formed by removing the photomask. 1 3. A method for manufacturing a double-gate oxide layer, including the following steps: providing a silicon substrate having an isolation structure for defining an active region; forming a first oxide layer on the substrate; Forming a patterned photoresist layer to cover the isolation structure and a first region of the first oxide layer adjacent to the isolation structure to expose the first oxygen 0503-7901TWF2 (2) .ptc Page 13 2005.05.09.014 Modification: v—? Area and the isolation structure; polycrystalline stone layer on the silicon substrate and the photoresist layer as a screen, remove the second area to expose the area within the active area of the part A silicon substrate; removing the photoresist layer, exposing the second oxide layer and the first region in order; and defining the polycrystalline second layer and the second oxygen layer to form a gate The pole structure is on a silicon substrate within the active area of the part. 14. The manufacturing method of the double-gate oxide layer covered by item 13 of the scope of the patent application, wherein the substrate is exposed between the gate structure and the second region. 15 · The method for manufacturing a double-gate oxide layer as described in item 13 of the scope of the patent application, wherein a spacer is formed on the side wall of the gate structure and on the substrate. 16 · The manufacturing method of the dual-gate oxide layer according to item 3 of the patent application scope, wherein the thickness of the second oxide layer is smaller than that of the first oxide layer. ^ 1 7 · The manufacturing method of the double-gate oxide layer as described in item 16 of the scope of patent application = method 'wherein the thickness of the first oxide layer is 30˜100 angstroms, and the thickness of the second oxide layer It is 10 to 30 angstroms. 1, 18 · The manufacturing method of the double-gate oxide layer according to item 3 of the scope of the applied patent, wherein the isolation structure is a shallow trench spacer. ^ 1 9 The method for manufacturing a double-gate oxide layer as described in item 13 of the scope of the patent application, wherein the isolation structure is a local silicon oxide. 20．The system of double gate oxide layer as described in item 13 of the scope of patent application 0503-7901TWF2 (2) .ptc Page 14 2005.05. 09.015 1242238 _Case No. 91104625_Year Month_Hi_ VI. Patent application method, in which the second region of the first oxide layer is removed using hydrogen fluoride Acid and wet money carved. 2 1. The method for manufacturing a double-gate oxide layer as described in item 13 of the scope of patent application, wherein forming the gate structure further comprises: forming a patterned photoresist layer covering a predetermined area of the gate structure, and using hydrogen fluoride The uncovered area is acid-etched, and the gate structure is formed by removing the photomask. 0503-7901TWF2 (2) .ptc Page 15 2005.05.09.016