JP2004214440A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can reduce leakage current by suppressing an ion implantation defect concentrated at the part of an active region by a heat treatment. <P>SOLUTION: A gate insulating film 3 is formed on a semiconductor substrate 1 in which a trench element isolated region 2 is formed. Thereafter, a gate electrode section 8 having a lower gate electrode 4a, an upper gate electrode 5a and an insulating film 6a on the gate is formed on the gate insulating film 3. Thereafter, with the gate electrode 8 as a mask, an n-type extension injection layer 9 and a p-type pocket injection layer 10 are formed. Thereafter, after a sidewall 12 is formed on the side face of the gate electrode 8, an n-type source/drain injection layer 13 is formed. Thereafter, after a protective insulation film 15 is formed, an impurity is activated, and an RTA treatment for releasing the stress of the insulating film embedded in the trench element isolated region 2 is performed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a trench element isolation region capable of suppressing a source-drain leakage current caused by a crystal defect.
[0002]
[Prior art]
With the miniaturization and high integration of semiconductor devices, the dimensions of element isolation regions are becoming smaller and smaller. Conventionally, the LOCOS method, which has a simple process, has been used for forming the element isolation region. However, the size reduction of the element formation region due to a bird's beak formed at the end of the LOCOS element isolation region cannot be ignored. Recently, a trench element isolation region (STI: Shallow Trench Isolation) has been used instead of the element isolation region by the LOCOS method (for example, see Patent Document 1).
[0003]
Hereinafter, a conventional method for manufacturing a semiconductor device having a trench element isolation region will be described.
[0004]
6 (a) to 6 (e) are cross-sectional views showing steps of manufacturing a conventional semiconductor device having a trench element isolation region. Here, description will be made using a method for manufacturing an n-type MIS transistor.
[0005]
First, in a step shown in FIG. 6A, a trench element isolation region 102 is formed on a main surface of a semiconductor substrate 101. In the trench element isolation region 102, after a silicon nitride film (not shown) is formed on an element formation region in the semiconductor substrate 101, the semiconductor substrate 101 is etched using the silicon nitride film as a mask to form a trench. After that, an insulating film is deposited on the entire surface of the substrate, the insulating film is selectively buried in the trench by CMP or the like, and then the silicon nitride film is removed.
[0006]
Next, in a step shown in FIG. 6B, a gate insulating film 103 made of a silicon oxide film is formed on the element formation region of the semiconductor substrate 101 by a thermal oxidation method. Thereafter, a polysilicon film 104 doped with impurities, a tungsten film 105, and a silicon nitride film 106 are sequentially deposited on the gate insulating film 103. After that, a resist film 107 having a gate electrode shape is formed on the silicon nitride film 106.
[0007]
Next, in the step shown in FIG. 6C, the silicon nitride film 106, the tungsten film 105, and the polysilicon film 104 are anisotropically etched using the resist film 107 as a mask, and the lower gate electrode 104a and the upper gate An electrode 105a and a gate electrode portion 108 including an on-gate insulating film 106a are formed.
[0008]
Thereafter, after removing the resist film 107, ion implantation of n-type impurities is performed at an implantation angle substantially perpendicular to the element formation region of the semiconductor substrate 101 and with low energy using the gate electrode portion 108 as a mask. An n-type extension injection layer 109 is formed. Thereafter, oblique ion implantation of a p-type impurity is performed at an implantation angle of 35 ° into the element formation region of the semiconductor substrate 101 using the gate electrode portion 108 as a mask, and a p-type pocket implantation layer 110 is formed below the n-type extension implantation layer 109. Form. As a result, an n-type extension injection layer 109 and a p-type pocket injection layer 110 are formed in the element formation region of the semiconductor substrate 101 with the channel region 111 located immediately below the gate electrode portion 108 interposed therebetween.
[0009]
Next, in the step shown in FIG. 6D, after a sidewall insulating film is deposited on the entire surface of the substrate, the sidewall insulating film is anisotropically etched to form a film on the side surface of the gate electrode portion 108. A sidewall 112 is formed. At this time, the gate insulating film 103 exposed on the source / drain regions is etched. Thereafter, using the gate electrode portion 108 and the side wall 112 as a mask, ion implantation of an n-type impurity is performed on the element formation region of the semiconductor substrate 101 to form an n-type source / drain implantation layer 113.
[0010]
Next, in a step shown in FIG. 6E, a heat treatment for activating impurities in the extension injection layer 109, the pocket injection layer 110, and the source / drain injection layer 113 is performed, so that an element formation region of the semiconductor substrate 101 is formed. A source / drain region 114 composed of an n-type extension diffusion layer 109a and an n-type source / drain diffusion layer 113a with a channel region 111 located immediately below the gate electrode portion 108 interposed therebetween; Are formed, respectively. Note that the heat treatment for activating the impurities in the extension injection layer 109 and the pocket injection layer 110 does not necessarily need to be performed simultaneously with the source / drain injection layer 113, and may be performed before the source / drain injection layer 113 is formed. good.
[0011]
[Patent Document 1]
JP-A-2001-160623 (pages 2-3, FIGS. 6 to 14)
[0012]
[Problems to be solved by the invention]
However, the conventional method for manufacturing a semiconductor device as described above has the following disadvantages.
[0013]
As shown in FIG. 6, after a trench isolation region 102 is formed in a semiconductor substrate 101, a thermal oxidation process for forming a gate insulating film 103 and an extension injection layer, a pocket injection layer, and a source / drain injection layer are performed. A heat treatment step for activating the impurities is performed. As a result, the edge portion of the element formation region of the semiconductor substrate near the boundary between the element formation region and the trench element isolation region of the semiconductor substrate due to the volume expansion due to thermal oxidation and the difference in the coefficient of thermal expansion between the silicon substrate and silicon oxide. Stress is concentrated on
[0014]
FIG. 7 is a cross-sectional view showing a result of a stress simulation after forming a gate insulating film. This figure shows a stress distribution after forming a gate insulating film 103 made of a silicon oxide film having a thickness of 7.5 nm at an oxidation temperature of 850 ° C., and the compressive stress of the central part P1 of the active region is 1.26E10. (Dyne / cm ² ), Whereas the compressive stress at the edge portion P2 of the active region is 2.10E10 (dyne / cm). ² ), Which indicates that the compressive stress is concentrated on the edge portion P2.
[0015]
Further, in recent years, with the miniaturization of elements, the area of the active region has been reduced. FIG. 8A is a plan view for explaining the simulated portion, and FIG. 8B is a simulation result showing a distribution of compressive stress applied from the trench element isolation region to the active region after forming the gate insulating film.
[0016]
As shown in FIG. 8A, the width of the trench isolation region (STI) is fixed at 0.22 μm, and the width X of the active region in the gate length direction is set. _L Was changed to 0.62 μm, 0.78 μm, and 1.0 μm, and a change in stress from the edge of the active region to the center of the active region immediately below the gate electrode was simulated. As shown in FIG. 8B, the width X of the active region in the gate length direction _L It can be seen that the compressive stress at the central portion of the active region located immediately below the gate electrode increases as the value decreases. From this, it is expected that the problem of the stress applied to the active region becomes more serious with further miniaturization. The width X of the active region in FIG. _L Is the mask dimension, and the position of the dotted line in the drawing is based on the side wall oxidation (about 70 nm) when forming the trench element isolation region.
[0017]
In the step shown in FIG. 6D, when the n-type source / drain implantation layers 113 are formed, high-concentration impurity ions are implanted, so that the source / drain implantation layers 113 of the semiconductor substrate 101 become amorphous. And an injection defect occurs.
[0018]
9A and 9B are diagrams for explaining the occurrence of the implantation defect in FIG. 6D, wherein FIG. 9A is a plan view and FIG. 9B is a cross-sectional view taken along a line AA in FIG. 9A. Implantation defects 115 generated by ion implantation for forming the n-type source / drain implantation layers 113 are considerably recovered by RTA (Rapid Thermal Anneal) for activating impurities in the source / drain implantation layers 113. However, at the same time as the impurity is activated during the RTA process, an implantation defect is attracted to a region having a high stress. That is, in the channel region 111 immediately below the gate electrode portion 108 which has not been made amorphous, the defects 115 are concentrated particularly in the region 116 having a high compressive stress at the edge of the active region. As a result, a crystal defect 117 that causes a leak path between the source and the drain is generated.
[0019]
The present invention has been made to solve the above-described problem, and a semiconductor capable of reducing leakage current by suppressing implantation defects generated by ion implantation from concentrating defects on a part of an active region by heat treatment. An object of the present invention is to provide a method for manufacturing a device.
[0020]
[Means for Solving the Problems]
According to a first method of manufacturing a semiconductor device of the present invention, a step (a) of forming a trench element isolation region in a semiconductor substrate, a gate insulating film and a gate are formed on the element formation region of the semiconductor substrate surrounded by the trench element isolation region. After the step (b) of forming an electrode, and after the step (b), a step (c) of ion-implanting a first impurity into an element formation region to form a source / drain implantation layer, and after the step (c) (D) forming a protective insulating film on the entire surface of the substrate, and performing a heat treatment for activating the first impurity of the source / drain injection layer while the protective insulating film is formed, And (e) forming a drain diffusion layer.
[0021]
According to this configuration, after forming the source / drain implanted layer by ion implantation, a protective insulating film is formed on the entire surface of the substrate, and the impurity in the source / drain implanted layer is activated with the protective insulating film formed. By performing the heat treatment for reducing the compression stress, the compression stress can be reduced. Therefore, it is possible to suppress the concentration of the injection defects generated at the time of forming the source / drain injection layer at the edge of the active region due to the subsequent heat treatment, thereby reducing the leak current.
[0022]
In the first method of manufacturing a semiconductor device, after the step (c) and before the step (d), a second impurity is ion-implanted into a position immediately below the source / drain implantation layer to form a high strain layer. Is formed.
[0023]
In the first method for manufacturing a semiconductor device, after the step (c) and before the step (d), a third impurity is ion-implanted into a channel region of the semiconductor substrate located below the gate electrode to form an amorphous state. Forming a porous layer.
[0024]
According to a second method of manufacturing a semiconductor device of the present invention, a step (a) of forming a trench element isolation region in a semiconductor substrate, and a step of forming a gate insulating film and a gate on the element formation region of the semiconductor substrate surrounded by the trench element isolation region A step (b) of forming an electrode, and after the step (b), a step (c) of ion-implanting a first impurity into an element formation region of the semiconductor substrate to form a source / drain implantation layer; (D) forming a high-strain layer by ion-implanting a second impurity at a position immediately below the source / drain injection layer; and (d) forming the high-strain layer after the step (d). (E) forming a source / drain diffusion layer by performing a heat treatment for activating the first impurity.
[0025]
According to this configuration, the heat treatment for activating the impurities in the source / drain injection layer is performed in a state where the high strain layer is formed below the source / drain injection layer, so that the active region edge portion and the channel region can be formed. Of the defects can be suppressed. Therefore, it is possible to suppress the concentration of the injection defects generated at the time of forming the source / drain injection layer at the edge of the active region due to the subsequent heat treatment, thereby reducing the leak current.
[0026]
According to a third method of manufacturing a semiconductor device of the present invention, there is provided a step (a) of forming a trench element isolation region in a semiconductor substrate, and forming a gate insulating film and a gate on the element formation region of the semiconductor substrate surrounded by the trench element isolation region. A step (b) of forming an electrode, and after the step (b), a step (c) of ion-implanting a first impurity into an element formation region of the semiconductor substrate to form a source / drain implantation layer; (D) forming a non-crystalline layer by ion-implanting a second impurity into a channel region of the semiconductor substrate located below the gate electrode after the step (d); and forming a source / drain injection layer after the step (d). (E) performing heat treatment for activating the first impurity to form source / drain diffusion layers.
[0027]
According to this structure, the stress remaining in the channel region can be released by the amorphous layer formed in the channel region, so that a crystal defect causing a leak path between the source and the drain is formed below the gate electrode. Concentration on the channel region can be suppressed. Therefore, it is possible to suppress the concentration of the injection defects generated at the time of forming the source / drain injection layer at the edge of the active region due to the subsequent heat treatment, thereby reducing the leak current.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0029]
(1st Embodiment)
FIGS. 1A to 1F are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention. Here, description will be made using a method for manufacturing an n-type MIS transistor.
[0030]
First, in a step shown in FIG. 1A, a trench element isolation region 2 is formed on a main surface of a semiconductor substrate 1. The trench isolation region 2 is formed by forming a silicon nitride film (not shown) on an element formation region of the semiconductor substrate 1 and then etching the semiconductor substrate 1 by about 300 nm using the silicon nitride film as a mask to form a trench. Form. Thereafter, an insulating film made of a silicon oxide film having a thickness of 700 nm is deposited on the entire surface of the substrate using a high-density plasma method, and then the insulating film is selectively embedded in the trench by CMP or the like. It is formed by removing. Before depositing the insulating film in the trench, a silicon oxide film having a thickness of about 20 nm may be formed on the exposed surface in the trench by a thermal oxidation method.
[0031]
Next, in a step shown in FIG. 1B, a gate insulating film 3 made of a silicon oxide film having a thickness of about 2.6 to 7 nm is formed on the element formation region of the semiconductor substrate 1 by a thermal oxidation method. Thereafter, on the gate insulating film 3, a polysilicon film 4 doped with impurities having a thickness of about 80 nm, a tungsten film 5 having a thickness of about 60 nm, and a silicon nitride film 6 having a thickness of about 140 nm are sequentially deposited. After that, a resist film 7 having a gate electrode shape is formed on the silicon nitride film 6.
[0032]
Next, in the step shown in FIG. 1C, the silicon nitride film 6, the tungsten film 5, and the polysilicon film 4 are anisotropically etched using the resist film 7 as a mask, and the lower gate electrode 4a, the upper gate An electrode 5a and a gate electrode portion 8 composed of an on-gate insulating film 6a are formed.
[0033]
Thereafter, after removing the resist film 7, arsenic, which is an n-type impurity, is implanted into the element formation region of the semiconductor substrate 1 with an implantation angle of 0 °, an implantation energy of 5 keV, and a dose of 5 × using the gate electrode portion 8 as a mask. 10 ¹⁴ / Cm ² Is performed under the conditions described above to form an n-type extension implantation layer 9. Thereafter, using the gate electrode portion 8 as a mask, boron as a p-type impurity is implanted into the element formation region of the semiconductor substrate 1 at an implantation angle of 35 °, an implantation energy of 15 keV, and a dose of 6 × 10 5. ¹² / Cm ² 4 times oblique ion implantation is performed under the conditions described above to form a p-type pocket implantation layer 10 under the n-type extension implantation layer 9. As a result, an n-type extension injection layer 9 and a p-type pocket injection layer 10 are formed in the element formation region of the semiconductor substrate 1 with the channel region 11 located immediately below the gate electrode portion 8 interposed therebetween. In addition, it is preferable to use a range of 15 to 60 ° as an implantation angle of oblique ion implantation for forming the pocket implantation layer.
[0034]
Next, in a step shown in FIG. 1D, a sidewall insulating film made of a silicon nitride film having a thickness of about 80 nm is deposited on the entire surface of the substrate, and then the sidewall insulating film is anisotropically etched. Thereby, the sidewall 12 is formed on the side surface of the gate electrode portion 8. At this time, the gate insulating film 3 exposed on the source / drain regions is subsequently etched. In the step shown in FIG. 1C, the exposed gate insulating film 3 may be etched after forming the gate electrode portion 8 in the step shown in FIG. Thereafter, arsenic, which is an n-type impurity, is implanted into the element formation region of the semiconductor substrate 1 at an implantation angle of 7 ° and a dose of 4 × 10 6 using the gate electrode portion 8 and the sidewall 12 as a mask. ^Fifteen / Cm ² Is performed under the conditions described above to form an n-type source / drain implantation layer 13.
[0035]
Next, in a step shown in FIG. 1E, a 50 nm-thickness is formed on the entire surface of the substrate by the CVD method so as to cover the trench element isolation region 2, the gate electrode portion 8, and the sidewall 12. A protective insulating film 15 made of a silicon oxide film (NSG film) containing no impurities is formed. After that, the impurities in the extension injection layer 9, the pocket injection layer 10, and the source / drain injection layer 13 are activated, and the temperature is sufficient to release the stress of the insulating film embedded in the trench isolation region 2. RTA processing (short annealing) is performed at 1000 ° C. to 1050 ° C. As a result, in the element formation region of the semiconductor substrate 1, the source / drain region including the n-type extension diffusion layer 9a and the n-type source / drain diffusion layer 13a is sandwiched by the channel region 11 located immediately below the gate electrode portion 8. 14 and a p-type pocket diffusion layer 10a located below the n-type extension diffusion layer 9a, respectively. The heat treatment for activating the impurities in the extension injection layer 9 and the pocket injection layer 10 does not necessarily need to be performed simultaneously with the source / drain injection layer 13, and may be performed before the source / drain injection layer 13 is formed. good. In the present embodiment, the NSG film is used as the protective insulating film 15, but a silicon nitride film may be used.
[0036]
Next, in the step shown in FIG. 1F, after an interlayer insulating film 16 is formed on the protective insulating film 15, a contact reaching the n-type source / drain diffusion layer 13a is formed on the interlayer insulating film 16 and the protective insulating film 15. A hole is formed, and a metal film such as tungsten is buried to form a metal plug 17. In the present embodiment, the interlayer insulating film 16 is formed with the protective insulating film 15 remaining. However, the interlayer insulating film may be formed after the protective insulating film 15 is selectively removed.
[0037]
2A and 2B are cross-sectional views showing the results of stress simulation after RTA processing for activating impurities in the source / drain injection layers. FIG. 2A shows a stress distribution when a protective insulating film is formed and RTA processing is performed. (B) shows a stress distribution when RTA processing is performed without forming a protective insulating film as in the related art.
[0038]
As shown in FIG. 2B, when RTA processing is performed without forming a protective insulating film as in the related art, the compressive stress at the central portion P1b of the active region is 4.51E9 (dyne / cm). ² ), The compressive stress of the active region edge portion P2b is 1.0E10 (dyne / cm ² ), Which indicates that the compressive stress is concentrated on the edge portion P2b.
[0039]
On the other hand, as shown in FIG. 2A, when a protective insulating film is formed and RTA processing is performed as in the present embodiment, both the active region central portion P1a and the active region edge portion P2a have a compressive stress. Is 4.96E9 (dyne / cm ² It can be seen that the concentration of the compressive stress on the edge of the active region is reduced by performing the high-temperature heat treatment with the substrate covered with the protective insulating film.
[0040]
FIG. 3 is a diagram showing the dependency of the thickness of the protective insulating film on the compressive stress at the edge of the active region. FIG. 3 shows the results of a simulation of the compressive stress when an NSG film is formed as a protective insulating film. As can be seen from FIG. 3, when the thickness of the NSG film is about 50 nm to 300 nm, the compressive stress can be reduced, and the thickness can be reduced most when the thickness is about 100 nm.
[0041]
According to the present embodiment, after the source / drain implantation layer 13 is formed by ion implantation, the protection insulating film 15 is formed on the entire surface of the substrate, and the source / drain implantation layer 13 is formed with the protection insulation film 15 formed. By performing the heat treatment for activating the impurities, the compression stress can be reduced. Therefore, it is possible to suppress the concentration of the injection defects generated at the time of forming the source / drain injection layer 13 at the edge portion of the active region due to the subsequent heat treatment, thereby reducing the leak current.
[0042]
(Second embodiment)
FIGS. 4A to 4C are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention. Here, description will be made using a method for manufacturing an n-type MIS transistor.
[0043]
First, in the step shown in FIG. 4A, the trench element isolation region 2 and the gate are formed on the main surface of the semiconductor substrate 1 by the same steps as those shown in FIGS. 1A to 1D in the first embodiment. An insulating film 3, a gate electrode portion 8, a sidewall 12, an n-type extension injection layer 9, a p-type pocket injection layer 10, and an n-type source / drain injection layer 13 are formed.
[0044]
Next, in the step shown in FIG. 4B, similarly to the implantation of the n-type source / drain implantation layer 13, the gate electrode portion 8 and the side wall 12 are used as masks and the element formation region of the semiconductor substrate 1 is formed. Silicon (Si) as an inert impurity, an implantation angle of 0 °, an implantation energy of 50 to 60 keV, and a dose of 1 × 10 ^Fifteen / Cm ² The ion implantation is performed under the conditions described above to form the high strain layer 18 just under the source / drain implantation layer 13 and at a remote position.
[0045]
Next, in the step shown in FIG. 4C, RTA is performed at about 1000 ° C. to 1050 ° C., which is a temperature sufficient to activate the impurities in the extension injection layer 9, the pocket injection layer 10, and the source / drain injection layer 13. Processing (short annealing) is performed. At this time, similarly to the first embodiment, the RTA process may be performed after forming the protective insulating film. As a result, in the element formation region of the semiconductor substrate 1, the source / drain region including the n-type extension diffusion layer 9a and the n-type source / drain diffusion layer 13a is sandwiched by the channel region 11 located immediately below the gate electrode portion 8. 14 and a p-type pocket diffusion layer 10a located below the n-type extension diffusion layer 9a, respectively. Further, the implantation defect generated during the formation of the source / drain injection layer 13 is transferred to the high strain layer 18 due to the gettering action of the high strain layer 18 during the RTA process.
[0046]
Then, after forming an interlayer insulating film on the substrate, a contact hole reaching the n-type source / drain diffusion layer 13a is provided in the interlayer insulating film, and a metal plug is formed by embedding the metal film.
[0047]
In this embodiment, Si is used as an ion species for forming the high-strain layer 18. However, Ge, which is an element similar to Si, may be used. Each of these elements has an impurity concentration of 6 × 10 ¹⁸ ~ 1 × 10 ²¹ / Cm ³ A high-strain layer can be formed with the degree.
[0048]
According to the present embodiment, the heat treatment for activating the impurities in the source / drain injection layer 13 is performed in a state where the high strain layer 18 is formed below the source / drain injection layer 13 so that the active region edge portion Further, the transfer of defects to the channel region can be suppressed. Therefore, it is possible to suppress the concentration of the injection defects generated at the time of forming the source / drain injection layer 13 at the edge portion of the active region due to the subsequent heat treatment, thereby reducing the leak current.
[0049]
(Third embodiment)
FIGS. 5A to 5C are cross-sectional views illustrating the steps of manufacturing a semiconductor device according to the third embodiment of the present invention. Here, description will be made using a method for manufacturing an n-type MIS transistor.
[0050]
First, in the step shown in FIG. 5A, the trench element isolation region 2 and the gate are formed on the main surface of the semiconductor substrate 1 by the same steps as those shown in FIGS. 1A to 1D in the first embodiment. An insulating film 3, a gate electrode portion 8, a sidewall 12, an n-type extension injection layer 9, a p-type pocket injection layer 10, and an n-type source / drain injection layer 13 are formed.
[0051]
Next, in the step shown in FIG. 5B, similarly to the implantation of the n-type source / drain implantation layer 13, the gate electrode portion 8 and the side wall 12 are used as masks and the Silicon (Si) as an inert impurity, an implantation angle of 60 °, an implantation energy of 110 keV or more, and a dose of 1 × 10 ^Fifteen / Cm ² The oblique ion implantation is performed four times under the conditions described above to form an amorphous layer 19 in the channel region 11 located directly below the gate electrode portion 8 and inside the n-type extension diffusion layer 9.
[0052]
Next, in the step shown in FIG. 5C, RTA is performed at about 1000 ° C. to 1050 ° C., which is a temperature sufficient to activate the impurities in the extension injection layer 9, the pocket injection layer 10, and the source / drain injection layer 13. Processing (short annealing) is performed. At this time, similarly to the first embodiment, the RTA process may be performed after forming the protective insulating film. As a result, in the element formation region of the semiconductor substrate 1, the source / drain region including the n-type extension diffusion layer 9a and the n-type source / drain diffusion layer 13a is sandwiched by the channel region 11 located immediately below the gate electrode portion 8. 14 and a p-type pocket diffusion layer 10a located below the n-type extension diffusion layer 9a, respectively. At this time, the stress remaining in the channel region 11 is released by the amorphous layer 19 formed in the channel region 11, so that when the amorphous layer 19 is recrystallized during the RTA process, In addition, it is possible to suppress the concentration of crystal defects causing a leak path between the source and the drain in the channel region below the gate electrode.
[0053]
Then, after forming an interlayer insulating film on the substrate, a contact hole reaching the n-type source / drain diffusion layer 13a is provided in the interlayer insulating film, and a metal plug is formed by embedding the metal film.
[0054]
According to the present embodiment, since the stress remaining in the channel region 11 can be released by the amorphous layer 19 formed in the channel region 11, a region having a high stress is reduced. Thus, the number of implantation defects attracted to the region with high stress can be suppressed, so that it is possible to suppress concentration of crystal defects that cause a leak path between the source and the drain in the channel region below the gate electrode. it can. Therefore, it is possible to suppress the concentration of the injection defects generated at the time of forming the source / drain injection layer 13 at the edge portion of the active region due to the subsequent heat treatment, thereby reducing the leak current.
[0055]
【The invention's effect】
According to the method of manufacturing a semiconductor device of the present invention, implantation defects caused by ion implantation can be suppressed from being concentrated on the channel region below the gate electrode by heat treatment, so that high performance with reduced leakage current can be achieved. A semiconductor device can be formed.
[Brief description of the drawings]
FIGS. 1A to 1F are cross-sectional views illustrating manufacturing steps of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a result of a stress simulation after an RTA process for activating impurities in a source / drain injection layer;
(A) is a stress distribution diagram when a protective insulating film is formed and RTA processing is performed.
(B) is a stress distribution diagram when RTA processing is performed without forming a protective insulating film as in the related art.
FIG. 3 is a diagram showing the dependency of the thickness of a protective insulating film on the compressive stress at the edge of an active region.
FIGS. 4A to 4C are cross-sectional views illustrating manufacturing steps of a semiconductor device according to a second embodiment of the present invention.
FIGS. 5A to 5C are cross-sectional views illustrating manufacturing steps of a semiconductor device according to a third embodiment of the present invention.
6 (a) to 6 (e) are cross-sectional views showing steps of manufacturing a conventional semiconductor device.
FIG. 7 is a cross-sectional view showing a result of stress simulation after forming a gate insulating film.
FIG. 8A is a plan view for explaining a simulated portion;
(B) is a diagram showing a simulation result showing a distribution of compressive stress applied from the trench element isolation region to the active region after the gate insulating film is formed.
FIG. 9 is a schematic diagram for explaining the occurrence of an injection defect in FIG.
[Explanation of symbols]
1 semiconductor substrate
2 Trench element isolation region
3 Gate insulating film
4 Polysilicon film
4a Lower gate electrode
5 Tungsten film
5a Upper gate electrode
6 Silicon nitride film
6a Insulating film on gate
7 Resist film
8 Gate electrode section
9 n-type extension injection layer
9a n-type extension diffusion layer
10 p-type pocket injection layer
10a P-type pocket diffusion layer
11 Channel area
12 Side wall
13 n-type source / drain injection layer
13a n-type source / drain diffusion layer
14 Source / drain region
15 Protective insulating film
16 Interlayer insulation film
17 Metal plug
18 High strain layer
19 Amorphous layer

Claims (5)

(A) forming a trench isolation region in a semiconductor substrate, and (b) forming a gate insulating film and a gate electrode on an element formation region of the semiconductor substrate surrounded by the trench isolation region;
(C) forming a source / drain implantation layer by ion-implanting a first impurity into the element formation region after the step (b);
A step (d) of forming a protective insulating film on the entire surface of the substrate after the step (c);
Performing a heat treatment for activating the first impurity of the source / drain injection layer in a state where the protective insulating film is formed, thereby forming a source / drain diffusion layer. A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 1,
After the step (c) and before the step (d), a step of ion-implanting a second impurity directly below the source / drain implantation layer to form a high strain layer is provided. A method for manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 1,
Forming a non-crystalline layer by ion-implanting a third impurity into a channel region of the semiconductor substrate located below the gate electrode after the step (c) and before the step (d); A method for manufacturing a semiconductor device, comprising: (A) forming a trench isolation region in a semiconductor substrate, and (b) forming a gate insulating film and a gate electrode on an element formation region of the semiconductor substrate surrounded by the trench isolation region;
(C) forming a source / drain implantation layer by ion-implanting a first impurity into the element formation region of the semiconductor substrate after the step (b);
After the step (c), a step (d) of ion-implanting a second impurity at a position immediately below the source / drain implantation layer to form a high strain layer;
A step (e) of forming a source / drain diffusion layer by performing a heat treatment for activating the first impurity of the source / drain injection layer after the step (d). A method for manufacturing a semiconductor device. Forming a trench element isolation region in a semiconductor substrate (a);
(B) forming a gate insulating film and a gate electrode on an element formation region of the semiconductor substrate surrounded by the trench element isolation region;
(C) forming a source / drain implantation layer by ion-implanting a first impurity into the element formation region of the semiconductor substrate after the step (b);
A step (d) of ion-implanting a second impurity into a channel region of the semiconductor substrate located below the gate electrode after the step (c) to form an amorphous layer;
A step (e) of forming a source / drain diffusion layer by performing a heat treatment for activating the first impurity of the source / drain injection layer after the step (d). A method for manufacturing a semiconductor device.

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