TW415021B - Method to produce integrated MOS-circuits - Google Patents

Method to produce integrated MOS-circuits Download PDF

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Publication number
TW415021B
TW415021B TW87112535A TW87112535A TW415021B TW 415021 B TW415021 B TW 415021B TW 87112535 A TW87112535 A TW 87112535A TW 87112535 A TW87112535 A TW 87112535A TW 415021 B TW415021 B TW 415021B
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TW
Taiwan
Prior art keywords
polycrystalline silicon
gate
layer
pbl
deposited
Prior art date
Application number
TW87112535A
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Chinese (zh)
Inventor
Dietrich Widmann
Martin Kerber
Original Assignee
Siemens Ag
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Publication of TW415021B publication Critical patent/TW415021B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Non-Volatile Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

In a method to produce MOS-circuits, a process-simplification of a PBL (polysilicon-Buffered -Locos)-Process is attained, in which a Padoxide (3) deposited in PBL-Process is used as Gate-oxide, in addition, said polysilicon-layer (4) deposited in PBL-Process is used as a part of Gare-polysilicon.

Description

4i5〇2x A7 B7 ^:"ίΓ屮决稃"而「.:: 五、發明説明 ( Γ ) 1 1 本 發 明 傜 關 於 積體M0 s電路之製造方法, 其中 使 用一種 i I F Η L程序。 1 1 在 製 造 積 體 M0 S電路(特別 是 C 0 M S電路 )時 > 種 大規模 請 1 先 ί 使 用 之 技 術 日 疋 L 0 C 0 S ( L 〇 cal 0 X i d a t i ο η of Sili C 0 η )技術 閱 ή 〇 m 由 此 種 矽 之 局部性 氧化 方 式,則能 以自動調整之較 背 而 1 I 之 1 高 之 場 摻 雜 作 用 來産生 較厚 之 場氧化區 ,在積體μ 0S電路 注 意 1 事 1 中 主 動 區 曰 疋 以 場 氧化昆 來作 為 邊界的。 在場氧化物和主 項 再 1 動 區 之 間 以 L0 C0 S技術所産生之過渡區具有 一種 步 階(s t e ρ ) 填 % 本 5 此 種 步 階 由 於 其典型 之外 型 亦稱為鳥 嘴。 為了縮短此 頁 1 I 種 佔 用 珍 貴 之 主 動面之 鳥嘵 t 則缓衝之 10C 0S技 術 須引用 1 1 於 多 晶 矽 中 這 在以下 稱為 Ρ B L ( Ρ ο 1 y s i 1 i C ο π - B uffered' 1 i L0 C 0 S ) 程 序 〇 1 訂 在 Ρ B L程序中, 須在基體上沈積一種由襯 墊氧 化 物(其 1 由 熱 氧 化 物 所 構 成),多晶矽以及氮化物所 構成 之 層序列 ! i 〇 在 此 種 對 PB L程序而言典型上是三層之此 種層 序 列上沈 [ I 積 一 種 光 阻 遮 罩 以便界 定一 主動區。 在不被光阻遮罩 1 1 所 覆 芸 -ΓΓΠ- 之 主 動 區 外部對 氮化 物 (典型上是使 用氮 化 矽(S i N 4 )) 進 行 非 等 向 性 之 蝕刻。 然後 在 以遮罩標 不之主動區外部 1 I 進 行 LOCO S氣化作用以便産生場氧化物。 然 後在 主 動區中 1 1 去 除 氣 化 層 〇 隨 後去除 多晶 矽 層和襯墊 氣化物, 它們在 i ! Ρ Θ L程序時被沈積而作為輔肋層。在去除襯 墊氣 化 物時場 I 1 氧 化 物 亦 薄 。然後 進行 — 種熱氧化 作用以便使氮化 f 1 物 形 式 之 層 (k 0 0 i -層)發生氧化作用。在去 除上 述 之氧化 1 I 層 時 1 場 氯 化 物 會再變 薄。 1 1 - 3 1 1 1 i 本紙張尺度沩州中网内家標锌(rNS ) Λ4現梠(公f ) 415021 A7 整 其,吏而 進 植.胄後之定刻考 種 1 省生 有 Η 是場影閛之 之0之11界蝕被^t 一^ I®可産 別Ϊ平的所使程 硼th驟矽便之不 ^ 特::幾厚力會製 。U 步晶以忡處 s g 使· I 樣之 是3ΐί之到應這種 〇 極 。輔 由 物作各多罩向此 Μ 1 :卩Ϊ 這物 用 圓受械 ,此 化便逑行遮等在 體卩。成 '化 作ΊΟ晶未機糙用 氣以上進S非用.積Η的逹UM物氣 化|1橱然及粗使 式行在及光揷作 造^能式^ ^化極 氧 W 整仍以漸可 射進。以個 1Λ製«4可方;^ b氧閘 極U在面㈡逐是 散來除用一行棺 以 g 是述 ΐίΐ極, 閘? 可表 Μ 商的 種物去作 S 淮iSl 法ΐί序 Tuwsl 除 行“物表fll I 化再化沈砂的 方 程以 t 作去 進 Ϊ 化美 W 使有 長氣須氣上晶要 種1之是 t 罾用之 前CO氣完會別 生式樣和層多需 一ΙΠ易的M1 接物 之 Ξ 極種 f 稈特 且 氣造 作 式射同化矽對是 供,,簡目丨 盲化 β用在閘此,{過ο 方散物淨晶 Η 能 提 — 別述 Ξ ,1,可氧驟作是則 ,U 化化 熱種化之多構可 是 L 特上層埶步化用,行 1 氣惡 ) 加此氣物在結中 的PB種,斤1化襯之氣作用進^_多質 > 以由式化 6 矽程 目種一明ΦΡ氣:關場化作上gr許品 ( 常菇射氣雜晶過 之一中發 墊驟相在氣化而 Η ,之 明 通是散楝椟多榫 明用法本— 襯步它 '場氧表ί 外物 J 程 説 後用揷閛和-此 發使方據 之下其比。極之屑此化 1 B 程 明 然作此行樁楝在 C 本須種依 PU 精以及因的閛美化。氣 發 人 c 進沈閘 蓆 中此 在PR沈略以 利行完氣饗極 \ 五 (#先閱讀背面之注意事項再填寫本頁) 本紙張尺度速用中國國家樣準(CNS > Α4規格(2Ι〇Χ297公釐) 415021 A7 B7 五、發明説明(今 質 品 種 1 用 0 使成 可製 是先 於早 Ίο S 物特 化中 氣序 極程 閘種 為此 作在 物其 化 , 氧物 熱化 種氧 一 之 第高 矽Γ ΐ Β 00 Ρ 多, 在-多 r 之 種極 積:Μ —3 i ^ 使作 以中 ’ 序 #^程 此部Lfe 積 沈 所 中 序 的 f 有 是 以 部 全 之 層 矽 極 晶 Μ 閘 可 > 之 作 小乂在吣 至重晶 @ 之 t 多 層出 用 一作 Λ 中 達 序 序 程 程Lf nD 使 ρ 可準 式標 方在 種它 此其 以於 為由 因是 是其 這 , , 化 的簡 利之 有泛 別廣 特別 是恃 ----->—?二 I 種 序過 程積 之沈 明再 發之 本後 在稍 合及 整以 全除 完去 可之 矽矽 晶晶 多多 之份 積部 沈一 而少 用至 層此 肋因 輔 , 為中 它以ί箱 其Η可 之-3Ρ亦 中 法 > 序 方 此 3 程 d 本Lf·因 在PB。 。種層 略此矽 省於晶 可矽多 都晶一 程多另 中 式 彩 上 層 矽 晶 多 之 積 另 該 由 積 -Μ整 極la在 SS⑶而 成員層 形,矽 了 晶 層 為 f 多 在结 0 它 矽其 晶積 多沈 - 地 極易 閛簡 之別 面特 表驟 式步 面述 平下 有以 具能 種上 一 面 生表 産式 上面 圓平 晶種 値此 構準 標 在 它 其 中 其 成 逹 來 序 程 之 有 0^- 發 本 由 0 可 這 此 在 合 整 可 層 矽 晶 多 及 層 化 氧 之 層 助 甫 作 用 中 序 程 底 較 一 它 此 其 在。在 ,面 〇 層表的 底之利 之坦有 坦平是 平成中 能形序 可便程 盡以HS 種層CO 一 矽於 成晶法 達多方 可一之 此另明 因積發 且沈本 中可用 程上使 過 層 (对先閲讀背面之注意事項再填寫本頁) 裝4i5〇2x A7 B7 ^: " ίΓ 屮 定 稃 " and ". :: V. Description of the Invention (Γ) 1 1 The present invention relates to a method for manufacturing an integrated M0 s circuit, in which an i IF Η L program is used 1 1 When manufacturing the integrated M0 S circuit (especially C 0 MS circuit) > kind of large-scale please 1 first ί technology used L0 C 0 S (L 〇cal 0 X idati ο η of Sili C 0 η) Technical reading price 〇m This kind of local oxidation of silicon can automatically adjust the field doping effect of 1 I to 1 to produce a thicker field oxidation region. 0S circuit Note 1 The active area in Event 1 is defined by the field oxide Kun. The transition area generated by the L0 C0 S technology between the field oxide and the main active area has a step (ste ρ ) Fill in% 5 This step is also called a bird's beak because of its typical appearance. In order to shorten this page 1 I kind of bird occupying a precious active face t The buffered 10C 0S technology must be referenced 1 1 in polycrystalline silicon. This is referred to as P BL (ρ ο 1 ysi 1 i C ο π-B uffered '1 i L0 C 0 S). In the procedure, a layer sequence consisting of a pad oxide (which is composed of a thermal oxide), polycrystalline silicon, and a nitride must be deposited on the substrate! I 〇 This is typically three for the PB L procedure. The layer sequence of this layer sinks [I product a photoresist mask to define an active area. Outside the active area of the -ΓΓΠ- which is not covered by the photoresist mask 1 1 nitride (typically using nitrogen Silicon nitride (S i N 4)) is anisotropically etched. Then, LOCO S gasification is performed on the outside of the active area marked with a mask to generate field oxides. Then the gasification layer is removed in the active area 1 1. The polycrystalline silicon layer and the pad gasification are subsequently removed. They are deposited during the i! P Θ L procedure as auxiliary ribs. The field I 1 oxide is also thin when the pad gas is removed. Then-a kind of thermal oxidation is performed in order to oxidize the layer (k 0 0 i -layer) of the nitrided f 1 form. When the oxide 1 I layer is removed, the chloride in one field will become thinner. 1 1-3 1 1 1 i This paper is a standard of zinc in the home network of Yinzhou (rNS). Λ4 is now (public f) 415021 A7. It is a field shadow of 0 to 11 of the eclipse ^ t a ^ I® can produce all kinds of flat boron and thorium silicon. ^ Special :: a few thick forces will make. The U step crystal uses s g so that I like 3 · 到 the answer to this 〇 pole. Auxiliary objects make various masks towards this Μ 1: 卩 Ϊ This object is treated with a circle, and this transformation will be covered in the body. The formation of Ί Ί crystals is not mechanically rough, and the gas is used to enter the non-use. The accumulated UM material is gasified | To gradually shoot into. Take a 1Λ system «4 may square; ^ b oxygen gate electrode U is scattered in the face to divide by a row of coffins, where g is the gate, gate? The seed material can be expressed as S, Huai iSl method, the sequence Tuwsl is deleted, the material table fll I, and the sedimentation equation is taken as t, and the beauty is w. It is t. Before the use of CO gas, it is necessary to create a new model and layer of M1, which is easy to use. The extremely special type of f is special and gas-made. Assimilation of silicon is provided.此 此, {过 ο Fang Sanwu Jingjing can mention — do n’t mention Ξ, 1, the oxygen can be used as a rule, the polymorphism of U chemical heat seeding can be used in the upper layer of liming, line 1. ) Add the PB species of this gas in the knot, and use the gas of the lining to enter the ^ _ multi-quality > To formulate the 6 Si Cheng Cheng species to illuminate the ΦP gas: turn the field into gr Xupin (often In one of the mushroom shot gas hybrid crystals, the phase of the hair cushion is evaporating, and the Mingtong is a loose and multi-joint method. It is a stepping stone to its' field oxygen table. -This issue leads the party to follow its ratio. The pole's crumbs are transformed into this one. B Cheng Chengran made this trip, and the beautification in C was based on the PU essence and the beautification of the cause. Qi was sent to the sink gate by PR. Shen slightly Eliminated \ Five (#Please read the precautions on the back before filling this page) This paper standard uses the Chinese national standard (CNS > Α4 size (2Ι〇 × 297 mm) 415021 A7 B7 V. Description of the invention (for this quality variety 1 use 0 It can be made before the early Ίο S specialization of gas-sequence polar range gates for this purpose, the material of which is the highest temperature of the oxygen heat species of oxygen Γ ΐ Β 00 ρ more, in-more r This kind of polar product: Μ — 3 i ^ Make it in order. The sequence of the order in this part of the Lfe accumulation is to use a full layer of silicon pole crystal M gate. ≫ The multi-layered production of t to the crystalline @@ is used as a sequence of Λ to achieve the sequence of Lf nD, so that ρ can be quasi-formal, so the reason is because of this. In particular, 恃 ----- >-? The sequence of the two I sequence processes, Shen Ming's reissues, and then a little more and more parts of the silicon silicon crystals can be closed and re-divided. It is rarely used until the ribs are supplemented, and it is used in 3 boxes and it can also be used in Chinese law > Preface and the 3 procedures d this Lf · In the PB .. The seed layer is omitted. The silicon is saved in the crystal. The silicon is more than one pass. In addition, the product of the upper layer of the Chinese crystal is more. The product of the M-pole is la and the member is layered. The silicon layer is f is more at the junction 0, it ’s silicon and its crystal deposit is more sinking. The ground is very easy to simplify. The special step is described in the following steps. There is a round seed crystal on the top. Marked in it is the sequence of the formation of 0 ^-hair from 0, but this is more in the integration of layered silicon crystals and layered oxygen layer help role is more important than other. Now, the bottom layer of the surface and the bottom layer of the surface is flat and can be used in the Heisei medium order. It can be done with the HS seed layer CO-silicon in the crystallization method. This can be explained by the accumulation and the available process. Top layer (read the precautions on the back before filling this page)

rIT _屮吹桄卑局Θ-Τ: Γ- /π 在PE pu C0E 種 E 此在 用是 使別 可待 亦 , 中極 用閘 € Βν. πνη 同浮 不為 之作 佳砂 在物物 種化化 此氧氧 用或或 使物層 須化化 中氣氣 況之的 情化化 種氮氛 此己已 在之之 。 層 層 此化化 極 晶1氮ΐ Η乡1¾¾ S i 之Hi作ιΐ— 積吣是ffiif 申 種¾¾ 〜 ® $ 比乍 一 r— LI /Λ— 所 最 中單中。是 體層層 序憶序化化 LfBHLfmm 本紙乐尺度ίΐ'州屮ΚΚΐ:彳ί;彳(ΓΝί; ) Λ4规格(2IOxW/公f ) 415021 at B7 好浐部t"打^r/Jh二消於At竹.7i卬$ 五、發明説明 ( 4· ) ! 1 1 和 控 制 鬧 掙 之 間 的 隔 離 層 〇 在應 用 本 發 明 之方法 時, 在 1 I 去 除 氣 化 物 之 過 程 中 記 憶 體 早胞 之 區 域 是 由漆遮 罩所 覆 1 I 器 r> 這 揉 所 商 生 之 四 周 7Ό 隔離 之 多 晶 矽 (其在Ρ BL程 序 請 先 1 1 中 已 沈 積 完 成 )除了其在L 0 C os方 法 中 之 功 能之外 同時 亦 閱 讀 I 背 可 用 作 浮 動 閘 極 〇 面 之 ! 圖式 i 本 發 明 以 下 將 依 據 顯 示 在 中 之 較 佳 宵施例 作進 t 事 1 步 描 〇 項 再 1 填 圖 式 簡 DO 里 説 明 如 下 ; 寫 本 裝 第 1 至 第 5 圖 木 發 明 之 M0 s電晶體及其環境在本方法較 頁 ·-_^ 1 1 早 之 各 階 段 中 之 俯 視 _ 和 各 種不 同 之 m 切 面圖。 1 | 第 1 圖 主 動 區 之 俯 視 圖 0 1 1 第 1 圖 沿 箸 第 1 圖 中 之 A- A '之 切 而 圖 〇 1 訂 第 3 圖 在 10 C0 S氣化過程之後沿著第] 圔中B-B ^線之切 1 1 面 圖 0 1 1 第 4 圖 在 氮 化 物 去 除 之 後 第1 圖 中 沿 B - Β '線之 切面 圖。 1 1 第 5 圖 在 Si 0 2 回蝕刻之後第1 圖中沿B -Β 1線之切面圖。 1 1 第 fi 至 第 9 圖 本 發 明 之 Μ 0 S電晶體及其環境在閛極- 多 晶 之 結 構 化 之 後 的 俯 視 圖 及各 m 不 同 之 橫切面 圖。 1 1 第 C 圖 動 區 之 俯 視 圖 0 1 I 第 7 圖 沿 箸 第 (! 圖 中 之 Β- ίί |之 切 而 圖 〇 1 I 第 R 圖 沿 箸 第 r> 圖 中 之 C - C,之 切 而 圖 〇 1 | 第 9 _ 沿 第 Γι 圖 中 之 A - A ’之 切 而 圖 〇 ί 1 第 1 圖 中 所 示 的 曰 在 1,0 C 0 S氣化作用之後主動區I之俯 1 1 ‘視 阚 〇 第 2 圖 所 示 的 是 沿 Μ 第1 圃 之 A - Λ ' 線經由 主動 區1 1 I -G 1 1 1 本紙張尺度速用中S國家標準(CNS ) Λ4規格(21〇Χ297公釐) 415021 A7 B7 五、發明説明(r ) 訂 (邻先閱讀背而之注意事項再填{本頁) 之橫切面圖。在此一横切面圖中基體2位於最下方,其 是由單晶矽所構成。在基體2上沈積P B L程序所用之典型 的三層序列,其是由襯墊氧化物3 ,多晶矽4和m化物 所構成。然後在主動區1中沈積一個光咀遮罩,其可作 為主動區1之遮罩。在光阻遮罩外部(即,在主動區1之 外部)進行一種非等向性之氮化物蝕刻過程,其中可去除 氮化層,使其下方之多晶矽層4裸露出來。然後去除光 阻遮罩且進行L 0 C Q S氣化作用以便産生場氧化物(S i 0 2 ) 。此種方法所形成之狀態及已變厚之場氣化區5 (其是由 氧化之多晶矽層4所産生)和主動區1中仍保留之氮化物 6各顯在第3圖中。第3圔是第1圖中沿B-B1線之切面 圖〇在L 0 C 0 S氣化過程時在氮化層之上側産生一種氧化之 氮化物,其須以等向性方式而被蝕刻。於是在隨後完全 去除氪化物時場氧化區5會變薄。此種方法所形成之狀 據顯不在第4圖中。 然後對場氧化物5 (其由Si02構成)進行進一步之回姓 刻,往下直至主動區1中之多晶矽4為止。此時之狀態 顯示在第5圖中。 本方法之其它流程將依據第6至第9圖來描述。第6 圖所示的是以本發明之方法所製成之M Q S電晶體及其環境 在進一 ·步之流程中主動區1之俯視圖。 首先沈積另一多晶矽層7且進行η + -摻雜。第9圖顯 示此種多晶矽層7 ,其中第9圖顯示第6圖中沿A - A '線 之横切面。此種多晶砂層7具有平坦之表面,可能時在 -7 - 本紙川屮ΚΙϋ標肀(('NS ) Λ4現格(2丨0>;2刀公漦) 415021 A7 B7 衫"部屮-ΐκ^^-^πίτ.消外合竹d印^τ 五、發明説明( b ) 1 1 其 上 可 産 生 特 別 有 利 之 其 它 結 構 〇 此 種 结 構 由於P B L程序 1 期 間 所 沈 積 之 多 晶 砂 層 4 包 含 在 閘 極 - 多 晶 矽中而成為 ! | 可 能 〇 :然 後 沈 積 另 __- 光 阻 遮 罩 8 以 便 界 定 閘 極-多晶碑 r—>. I 請 1 結 構 , 其 在 第 G 圖 中 是 以 虛 線 表 示 0 妖 i \ ν'» 後 對 多晶矽進行 先 閱 1 I 讀 非 等 向 性 之 蝕 刻 其 中 由 % 多 晶 層 7 所 構成之多晶 背 \ 而 i 矽 以 及 由 最 先 沈 積 之 多 m ΒΕΙ 矽 層 4 所 構 成 之 多 晶矽只要它 之 注 1 1 們 不 被 光 阻 遮 罩 8 所 覆 蓋 都 須 去 除 〇 第 8 圖 中所顯示的 意 事 1 項 | 是 沿 第 6 圖 C - C ' 線 之 橫 切 面 圖 〇 由 第 8 圖 中 很明顯的是 再 填 光 阻 遮 罩 8 外 部 之 多 晶 矽 已 去 除 t 因 此 該 處只在主動 本 裝 頁 1 區 1 之 外 部 殘 留 較 厚 之 場 氧 化 區 (S i0 2 )以及在主動區1 1 内 部 殘 留 原 來 已 沈 積 之 襯 墊 氧 化 物 3 (其同樣是由Si02所 1 I 構 成 )。 第7 圖所示的是第6 圖中沿著Β -B |線之切面圖, 1 I 其 中 閘 極 - 多 晶 矽 结 構 待 別 明 顯 〇 在 基 體 2 上在主動區 I 訂 1 中 通 常 有 一 襯 墊 氧 化 物 (其由s iO 2 構 成 )且其上在此 1 其 間 由 光 阻 遮 罩 8 所 覆 盡 之 區 域 中 會 産 生 一 種多晶矽結 1 I 構 7 其 下 方 之 三 分 之 一 是 由 取 初在PBL程序範圍中所沈積 1 I 之 多 晶 矽 4 所 構 成 且 其 上 方 之 二 分 之 二 曰 疋 由 g —多晶砂 1 1 層 7 稻 後 所 沈 積 之 多 晶 矽 所 構 成 〇 广W - t 參 考 符 號 説 明 1 1 . -* • 主 動 區 1 2 . 基 體 1 1 3 . 襯 墊 氧 化 物 1 I 4 . 多 晶 砂 1 1 5 . * * 場 氣 化 區 i I 6 . 氮 化 物 1 1 Ί · 另 一 多 晶 矽 層 1 1 8 . 光 阻 遮 罩 ! -8 - 1 1 本紙张尺度適屮家標肀(('NS ) /以说格(公始)rIT _Blowing the inferior game Θ-Τ: Γ- / π in PE pu C0E species E This is used to make it impossible to wait, the middle pole is used as a gate € Βν. πνη is not a good species in the sand The chemical atmosphere used to change the oxygen and oxygen or the physical condition of the gas layer must be in it. Layer by layer This transformation of the polar crystal 1 nitrogen ΐ Η 乡 1¾¾ S i's Hi-work ΐ — the product is the ffiif application ¾¾ ~ ® $ Bizha r — LI / Λ — most orders. It is a layer sequence remembrance LfBHLfmm paper scale ΐ 尺度 '州 屮 ΚΚΐ: 彳 ί; 彳 (ΓΝί;) Λ4 size (2IOxW / male f) 415021 at B7 Haobu Department t " hit ^ r / Jh two elimination in At bamboo.7i 卬 $ V. Description of the invention (4 ·)! 1 The isolation layer between 1 1 and controlling the trouble. When applying the method of the present invention, the area of the early cells in the memory during the process of 1 I removing gaseous substances. It is covered by a lacquer mask. This device is surrounded by a 7Ό perimeter. It is an isolated polycrystalline silicon (which has been deposited in the P BL procedure before 1 1) except for its function in the L 0 Co os method. I also read that the I-back can be used as the floating gate 0 side! Schema i The present invention will be based on the preferred embodiment shown in the following t things 1 step description 0 items and 1 fill in the schematic DO The description is as follows; M0 s transistor of the invention of the first to fifth drawings And context of the present method is more pages · _ ^ 11 in the early stages of each of a plan view of _ and m different cut plane in various FIG. 1 | Fig. 1 Top view of active area 0 1 1 Fig. 1 cuts along AA 'in Fig. 1 and Fig. 0 draws Fig. 3 along 10 C0 S after gasification process. Section 1 of the BB ^ line 1 0 0 1 1 Figure 4 is a section along the line B-Β 'in Figure 1 after nitride removal. 1 1 Figure 5 A cross-sectional view taken along line B-B 1 in Figure 1 after Si 0 2 etch back. 1 1 Fig. Fi to Fig. 9 The top view of the MOS transistor and its environment of the present invention after the structure of the pole-polycrystal and the cross-sections of each m are different. 1 1 The top view of the moving area of the C diagram 0 1 I The 7th diagram is cut along the (-) in the B! (Figure 1) The C-C in the R > Cut diagram 〇1 | Section 9 _ cut along A-A 'in the Γι diagram and 〇ί 1 The first diagram shown in Figure 1 shows the active area I after the 1,0 C 0 S gasification 1 1 '视 阚 〇 The second figure shows the A- Λ' line through the 1st field through the active area 1 1 I -G 1 1 1 The national standard (CNS) Λ4 specification of this paper standard 21〇 × 297mm) 415021 A7 B7 V. Description of the invention (r) Order (read the notes on the back first and then fill in the {page) cross-sectional view. In this cross-sectional view, the substrate 2 is at the bottom, It is composed of single crystal silicon. A typical three-layer sequence used in the PBL process is deposited on substrate 2. It is composed of pad oxide 3, polycrystalline silicon 4 and mide. Then a light is deposited in active area 1. Mouth mask, which can be used as a mask for active area 1. Outside the photoresist mask (ie , Outside the active area 1), a non-isotropic nitride etching process is performed, in which the nitride layer can be removed to expose the polycrystalline silicon layer 4 underneath. Then the photoresist mask is removed and L 0 CQS gasification is performed. It acts to generate field oxide (S i 0 2). The state formed by this method and the thickened field gasification region 5 (which is generated by the oxidized polycrystalline silicon layer 4) and the active region 1 remain Nitride 6 is shown in Figure 3. Figure 3 is a cross-sectional view taken along line B-B1 in Figure 1. During the L 0 C 0 S gasification process, an oxidized nitride is generated on the upper side of the nitride layer. , Which must be etched in an isotropic manner. The field oxide region 5 will then become thinner when the halide is subsequently completely removed. The state formed by this method is apparently not shown in Figure 4. Then the field oxide 5 ( It is composed of Si02) for further engraving of the last name, down to the polycrystalline silicon 4 in the active area 1. The state at this time is shown in Fig. 5. The other processes of this method will be described according to Figs. 6 to 9 Figure 6 shows the MQS transistor made by the method of the present invention and its environment. Top view of active area 1 in a one-step process. First, another polycrystalline silicon layer 7 is deposited and η + -doped. Figure 9 shows such a polycrystalline silicon layer 7, of which Figure 9 shows A-A along Figure 6 'Cross-section of the line. This polycrystalline sand layer 7 has a flat surface, possibly at -7-Honkikawa 屮 ΚΙϋ 标 肀 ((' NS) Λ4 grid (2 丨 0 >; 2 knives) 4 415021 A7 B7 shirt " Ministry 屮 -ΐκ ^^-^ πίτ. Elimination of foreign matter d India ^ τ V. Description of the invention (b) 1 1 Other structures that can be particularly advantageous can be created on this structure. The deposited polycrystalline sand layer 4 is contained in the gate-polycrystalline silicon and becomes! | Possible 〇: Then deposit another __- photoresist mask 8 to define the gate-polycrystalline monument r— >. I Please 1 structure, which In Figure G, it is indicated by a dashed line. 0 i i \ ν '», then read the polycrystalline silicon first. I read anisotropic etching. The polycrystalline back consisting of% polycrystalline layer 7 \ The i-silicon and the polycrystalline silicon composed of the first deposited m ΒΕΙ silicon layer 4 must be removed as long as its note 1 1 is not covered by the photoresist mask 8. The meaning shown in Figure 8 is 1 It is a cross-sectional view taken along the line C-C 'in FIG. 6. It is obvious from FIG. 8 that the photoresist mask 8 is filled again. The polysilicon on the outside has been removed, so it is only in the active page 1 area 1 A thicker field oxide region (S i0 2) remains outside and a pad oxide 3 (which is also composed of Si02 1 I) that has been deposited remains in the active region 1 1. Figure 7 shows a cross-section view along the line B -B | in Figure 6, 1 I of which the gate-polycrystalline silicon structure is not obvious. On the substrate 2 there is usually a pad oxidation in the active region I. 1 A polycrystalline silicon junction will be produced in the area covered by the photoresist mask 8 during this 1 s iO 2, and the first third of it will be formed in the PBL. In the program range, 1 I of polycrystalline silicon 4 is deposited and two-half of it is composed of g—polycrystalline sand 1 1 layer 7 polycrystalline silicon deposited after rice. Wide W-t reference symbol description 1 1 -* • Active region 1 2. Base 1 1 3. Pad oxide 1 I 4. Polycrystalline sand 1 1 5. * * Field gasification region i I 6. Nitride 1 1 1 · Another polycrystalline silicon layer 1 1 8. Photoresist mask! -8- 1 1 The size of this paper is suitable for domestic use (('NS) / Yi Sao Ge (Gong Shi))

Claims (1)

六、申請專利範圍 (87年11月修正) -焴脅-ίί?Γν!^_-,:. ’本案修正後是否變更原實rt':·.:Μ濟部中央標率局Λ工消费合作社印装 1. 一種積體MOS電輅之製造方法,其傜使用一種PBL (plysilicon-Buffered-LOCOS)程序,其待歡為:使用 一種在PBL程序中所沈積之襯墊氧化物作為閘榷氧化物。 2. 如申請專利範圍第1項之方法,其中首先産生閘極氣 化物,然後産生場氣化物。 3. 如申請專利範圍第1或第2項之方法,其中使用此製 程之第一種熱氣化物作為閘極氣化物。 4. 如申請專利範圍第1項之方法,其中使用一種在PBL程 序中所沈積之多晶矽層的至少一部份以作為閘極-多 晶矽。 5. 如申謓專利範圍第1,2或4項之方法,其中為了在PBL 程序中所沈積之多晶矽層上形成閛搔-多晶矽,則須 沈積另一多晶砂層。 6. 如申請專利範圍第5項之方法,其中所産生之該另一 多晶砂層之厚度大約是PBL程序中所沈積之多晶砂層厚 度之二倍。 7. 如申請專利範圍第5項之方法,其中藉由該另一多晶 矽層而在整個晶圓上産生一種具有平坦表面之閘極-多晶矽。 8. 如申諳專利範圍第6項之方法,其中藉由該另一多晶 矽層而在整個晶圓上産生一種具有平坦表面之閘極-多晶矽。 9. 如申請專利範圍第1項之方法,其中此方法是用在 CMOS裂程中。 -9- n^i ^^^1 nn n^i 1 - -I I- f n ^^^1 ip^i VOJ (請先閲讀背面之注意事項再填寫本頁) 本紙張/^度逍用中國國家揉準(〇奶)八4«^格(210父297公釐)Scope of Patent Application (Amended in November 1987)-焴 --ίί? Γν! ^ _-,:. 'Will the original rt be changed after the amendment of this case?' Cooperative printing 1. A method for manufacturing integrated MOS batteries, which uses a PBL (plysilicon-Buffered-LOCOS) program, which is to use a pad oxide deposited in the PBL program as a gate Oxide. 2. The method according to item 1 of the scope of patent application, wherein the gate gas is generated first, and then the field gas is generated. 3. If the method of claim 1 or 2 is applied for, the first hot gaseous substance of this process is used as the gate gaseous substance. 4. The method according to item 1 of the patent application scope, wherein at least a part of the polycrystalline silicon layer deposited in the PBL process is used as the gate-polycrystalline silicon. 5. If the method of claim 1, 2, or 4 is applied, in order to form ytterbium-polycrystalline silicon on the polycrystalline silicon layer deposited in the PBL procedure, another polycrystalline sand layer must be deposited. 6. As in the method of claim 5, the thickness of the other polycrystalline sand layer is about twice the thickness of the polycrystalline sand layer deposited in the PBL procedure. 7. The method as claimed in claim 5 wherein a gate-polycrystalline silicon having a flat surface is produced on the entire wafer by the another polycrystalline silicon layer. 8. The method as claimed in claim 6 of the patent, wherein a gate-polycrystalline silicon having a flat surface is produced on the entire wafer by the another polycrystalline silicon layer. 9. The method of claim 1 in the scope of patent application, wherein this method is used in the CMOS crack process. -9- n ^ i ^^^ 1 nn n ^ i 1--I I- fn ^^^ 1 ip ^ i VOJ (Please read the notes on the back before filling out this page) This paper / ^ 度 闲 用 中国National Kneading Standard (〇 奶) 8 4 ^^ (210 father 297 mm) 六、申請專利範圍 (87年11月修正) -焴脅-ίί?Γν!^_-,:. ’本案修正後是否變更原實rt':·.:Μ濟部中央標率局Λ工消费合作社印装 1. 一種積體MOS電輅之製造方法,其傜使用一種PBL (plysilicon-Buffered-LOCOS)程序,其待歡為:使用 一種在PBL程序中所沈積之襯墊氧化物作為閘榷氧化物。 2. 如申請專利範圍第1項之方法,其中首先産生閘極氣 化物,然後産生場氣化物。 3. 如申請專利範圍第1或第2項之方法,其中使用此製 程之第一種熱氣化物作為閘極氣化物。 4. 如申請專利範圍第1項之方法,其中使用一種在PBL程 序中所沈積之多晶矽層的至少一部份以作為閘極-多 晶矽。 5. 如申謓專利範圍第1,2或4項之方法,其中為了在PBL 程序中所沈積之多晶矽層上形成閛搔-多晶矽,則須 沈積另一多晶砂層。 6. 如申請專利範圍第5項之方法,其中所産生之該另一 多晶砂層之厚度大約是PBL程序中所沈積之多晶砂層厚 度之二倍。 7. 如申請專利範圍第5項之方法,其中藉由該另一多晶 矽層而在整個晶圓上産生一種具有平坦表面之閘極-多晶矽。 8. 如申諳專利範圍第6項之方法,其中藉由該另一多晶 矽層而在整個晶圓上産生一種具有平坦表面之閘極-多晶矽。 9. 如申請專利範圍第1項之方法,其中此方法是用在 CMOS裂程中。 -9- n^i ^^^1 nn n^i 1 - -I I- f n ^^^1 ip^i VOJ (請先閲讀背面之注意事項再填寫本頁) 本紙張/^度逍用中國國家揉準(〇奶)八4«^格(210父297公釐) 415021 A8 B8 C8 D8 申請專利範圍 浮 項Μ法 用 第Ifl之 是 或 項 層 1A ir ro 砂 β βf帛f 圍 圍 ®^ ΛΠ t - 4ΡΓ 之 利 —利V “¥ ssffits 丨所丨 申 Ϊ 申 中 如冑如 序 . 在 中 B 其 P ,β在 極 方ΑΡ其 勒 之 程 所 中 序 程 極 閘 動 浮 作 用 是 層 矽 晶 多 之 積 沈 使 中 序 程 L B P 在 中 其 法 方 之 項 ο ,1 第 圍 範 利 專 請 申 如 層 化 氮 為 作 靥 化 氮 - 物 化 氧 或 物 化 氧 之 化 氮 已 用 化 氮 作 用 該 用 使 中 其 法 方 之 項 ο 第 圍 範 Λ? 利 專 請 申 如 極 浮 為 作 層 化 氪 - 物 化。 氣層 或離 層隔 化的 氣間 之之 化極 氮閘 已制 之控 層和 專 諳 申 如 化 氮 作 用 該 用 使 中 其 法 方 之 項 2 1 第 圍 範 極 閱 動 浮 為 作 層 化 氮- 物 化 C 氣層 或離 層隔 化的 氣間 之之 化極 氮閘 已制 之控 層和 (請先閱讀背面之注^'項再填寫本頁) 訂 經濟部中失揉率局員工消费合作社印氧 本紙浪尺度適用中國國家揉率(CNS > A4規格(210X297公釐)Scope of Patent Application (Amended in November 1987)-焴 --ίί? Γν! ^ _-,:. 'Will the original rt be changed after the amendment of this case?' Cooperative printing 1. A method for manufacturing integrated MOS batteries, which uses a PBL (plysilicon-Buffered-LOCOS) program, which is to use a pad oxide deposited in the PBL program as a gate Oxide. 2. The method according to item 1 of the scope of patent application, wherein the gate gas is generated first, and then the field gas is generated. 3. If the method of claim 1 or 2 is applied for, the first hot gaseous substance of this process is used as the gate gaseous substance. 4. The method according to item 1 of the patent application scope, wherein at least a part of the polycrystalline silicon layer deposited in the PBL process is used as the gate-polycrystalline silicon. 5. If the method of claim 1, 2, or 4 is applied, in order to form ytterbium-polycrystalline silicon on the polycrystalline silicon layer deposited in the PBL procedure, another polycrystalline sand layer must be deposited. 6. As in the method of claim 5, the thickness of the other polycrystalline sand layer is about twice the thickness of the polycrystalline sand layer deposited in the PBL procedure. 7. The method as claimed in claim 5 wherein a gate-polycrystalline silicon having a flat surface is produced on the entire wafer by the another polycrystalline silicon layer. 8. The method as claimed in claim 6 of the patent, wherein a gate-polycrystalline silicon having a flat surface is produced on the entire wafer by the another polycrystalline silicon layer. 9. The method of claim 1 in the scope of patent application, wherein this method is used in the CMOS crack process. -9- n ^ i ^^^ 1 nn n ^ i 1--I I- fn ^^^ 1 ip ^ i VOJ (Please read the notes on the back before filling out this page) This paper / ^ 度 闲 用 中国National standard (0 milk) 8 4 «^ (210 father 297 mm) 415021 A8 B8 C8 D8 Patent application scope Floating item M method Ifl of the item or item layer 1A ir ro sand β βf 帛 f encirclement ® ^ ΛΠ t-4ΡΓ-Profit V "¥ ssffits 丨 所 丨 Shenzhong Rugao is in sequence. In the middle of B, P, β in the polar AP, the sequence of the pole gate dynamic floating action is The accumulation of multiple layers of silicon crystals makes the middle-order sequence LBP in its method ο, 1. Fan Li specifically requested that the layered nitrogen be used as tritiated nitrogen-physical oxygen or physical nitrogen has been used. the nitrogen of the item so that the first side ο its normal range Λ surrounded by special interest for the requested application, such as a floating electrode layer of krypton -? materialization of delamination or gas layer between the gas barrier of the gate is made extremely nitrogen The control layer and the special application of nitrogen should be used in their legal methods 2 1 Floating for stratified nitrogen-physicochemical C gas layer or separated layer of gas between the electrode and nitrogen gate. The control layer has been prepared and (please read the note ^ 'on the back before filling this page) Order in the Ministry of Economic Affairs Lost and rubbed rate Bureau Consumer Consumption Co., Ltd. Printed oxygen paper scale is applicable to China's national rubbed rate (CNS > A4 specification (210X297 mm)
TW87112535A 1997-08-01 1998-07-30 Method to produce integrated MOS-circuits TW415021B (en)

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DE4214993A1 (en) * 1991-05-07 1992-11-12 Micron Technology Inc Semiconductor disc prepn. - by forming layer of polycrystalline silicon on substrate, forming dielectric by oxidn. of substrate, and then doping
US5358892A (en) * 1993-02-11 1994-10-25 Micron Semiconductor, Inc. Etch stop useful in avoiding substrate pitting with poly buffered locos
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate
DE4336869C2 (en) * 1993-10-28 2003-05-28 Gold Star Electronics Method of manufacturing a MOS transistor
US5393694A (en) * 1994-06-15 1995-02-28 Micron Semiconductor, Inc. Advanced process for recessed poly buffered locos
US5652177A (en) * 1996-08-22 1997-07-29 Chartered Semiconductor Manufacturing Pte Ltd Method for fabricating a planar field oxide region

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