3325twf.doc/005 A7 ____ _B7___ 五、發明説明（I ) 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種積體電路元件間的元件隔離結構的製造方 法。 元件隔離區係用以防止載子(carrier)通過基底而在相鄰 支援件間移動，傳統上，元件隔離區形成於稠密的半導體 電路中相鄰的場效電晶體間，藉以減少由場效電晶體(field effect transistor，FET)產生的電荷洩露（charge leakage)，此 種稠密的半導體電路，例如是動態隨機存取記憶體 (DRAM)。元件隔離區時常以厚場氧化矽層的形式延伸而 在半導體基底表面下形成，其中最傳統普遍的技術爲矽局 部氧化技術(LOCOS)。LOCOS技術之日趨成熟，因此可藉 此技術以較低的成本獲得可靠度高且有效的元件隔離結 構，然而，LOCOS仍具有多項缺點，包括已知應力產生 之相關問題與LOCOS場隔離結構周圍鳥嘴區(bird’s beak) 的形成等。 經"部中Λ釘羋工消外合作妇印絮 {讀先Μ讀背面之注^項再填寫本頁) 在尺寸日益縮小的積體電路中，主動區(active area)與 主動區的間隔越來越小，使得LOCOS在小間隔區所形成 的場區氧化物（field oxide)會較大間隔區的場區氧化物爲 薄，因而無法有效的隔離元件。此外，LOCOS的另一缺 點在於，閘極氧化矽層變薄，因爲主動區的輪廓曲折，在 主動區轉角(edge)的地方，因爲氧化矽層材質與主動區材 質並不相同，會有應力（stress)產生，使其閘極氧化矽層會 較其他區域的閘極氧化矽層爲薄，因而造成漏電。 淺溝渠隔離（shallow trench isolation, STI)亦是一種普 3 本紙張尺度適用中國ϋί票準（CNS ) A4規格（210X297公f " ~3325twf.doc / 005 A7 ____ _B7___ 5. Description of the Invention (I) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a device isolation structure between integrated circuit components. The element isolation region is used to prevent carriers from moving between adjacent supports through the substrate. Traditionally, the element isolation region is formed between adjacent field effect transistors in a dense semiconductor circuit, thereby reducing field effect. Charge leakage generated by a field effect transistor (FET). Such a dense semiconductor circuit is, for example, a dynamic random access memory (DRAM). The device isolation area is often formed as a thick-field silicon oxide layer and is formed under the surface of the semiconductor substrate. The most traditional and common technology is the silicon local oxidation technology (LOCOS). As LOCOS technology matures, it can be used to obtain a highly reliable and effective component isolation structure at a lower cost. However, LOCOS still has a number of disadvantages, including problems related to known stress generation and birds surrounding the LOCOS field isolation structure. Formation of the beak area (bird's beak), etc. According to the Ministry of Internal Affairs and Foreign Trade Cooperative Women ’s Print (Read the first M and read the note on the back, and then fill out this page) In the increasingly compact integrated circuit, the active area and the active area The spacing is getting smaller and smaller, so that the field oxide formed by LOCOS in the small spacing area will be thinner than the field oxide in the larger spacing area, so it cannot effectively isolate the device. In addition, another disadvantage of LOCOS is that the gate silicon oxide layer is thinner because the contour of the active area is tortuous. At the edge of the active area, the material of the silicon oxide layer is not the same as that of the active area and there will be stress. (Stress) is generated, so that the gate silicon oxide layer is thinner than the gate silicon oxide layer in other regions, thereby causing leakage. Shallow trench isolation (STI) is also a standard. This paper size is applicable to China Standards (CNS) A4 (210X297 male f " ~
Mis•部中央ii.-^-^M T;消贽合竹相印¾ 3325twf.doc/005 A7 B7 五、發明説明（> ) 遍的元件隔離方法，一般使用氮化矽作爲一罩幕，以非等 向性蝕刻法（anisotropic)在半導體基底上定義一近垂直的 溝渠。之後再將溝渠塡滿氧化物層，而提供一元件隔離結 構，且此結構具有一與原基底表面同高之上表面。接著， 元件形成於P型之矽基底上，並在STI結構周圍形成FET 元件，其中包括基底通道區周圍之N型源/汲極區 (source/drain)，以及閘極氧化物層與通道區分離之多晶矽 閘極。STI結構的厚度可提供有效的隔離效果，且可應用 在較小的元件上，此即STI結構不同於LOCOS隔離區之 處。 第1A圖至第1D圖繪示係爲習知的一種淺溝渠隔離製 造方法之流程圖。請參照第1A圖，在矽基底10上先形成 一襯墊氧化矽層ll(pad oxide)，再以化學氣相沈積法形成 一氮化矽層12,而氮化矽層12係作爲化學機械硏磨法之 蝕刻終點。接著，藉著塗佈而形成一定義溝渠的光阻層14， 再進行曝光、顯影與選擇性的蝕刻光阻層14，並接續向下 鈾刻，去除部分的氮化矽層12、氧化矽層11與基底1〇， 以在基底內形成溝渠16。 接著，請參照第1B圖，於移除光阻層14後，先成長 一層薄的熱氧化砂層18(thermal oxide layer)，形成方式比 如在溫度約爲900~1100°C下進行，厚度約爲300〜500A。 之後，形成一氧化矽層20於熱氧化矽層18上，形成方式 比如利用常壓化學氣相沈積法（APCVD)，以矽酸四乙酯 (tetra-ethyl-ortho-silicate，TE0S)爲反應氣體源，使用常壓 4 本紙張尺度適州中國國家標率（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)Mis • Ministry Central ii .- ^-^ MT; Elimination of Combined Bamboo Phase Printing ¾ 3325twf.doc / 005 A7 B7 V. Invention Description (>) element isolation method, usually using silicon nitride as a curtain, Anisotropic etching is used to define a nearly vertical trench on a semiconductor substrate. The trench is then filled with an oxide layer to provide an element isolation structure, and the structure has an upper surface that is the same height as the original substrate surface. Next, the element is formed on a P-type silicon substrate, and a FET element is formed around the STI structure, which includes an N-type source / drain region around the substrate channel region, and a gate oxide layer and a channel region. Separated polysilicon gate. The thickness of the STI structure provides effective isolation and can be applied to smaller components. This is where the STI structure differs from the LOCOS isolation area. Figures 1A to 1D show a flowchart of a conventional method for manufacturing a shallow trench isolation system. Referring to FIG. 1A, a pad oxide layer 11 (pad oxide) is formed on the silicon substrate 10, and then a silicon nitride layer 12 is formed by a chemical vapor deposition method, and the silicon nitride layer 12 is used as a chemical mechanism. End of etching by honing. Then, a photoresist layer 14 defining a trench is formed by coating, and then the photoresist layer 14 is exposed, developed, and selectively etched, and then etched downward to remove a portion of the silicon nitride layer 12 and silicon oxide. The layer 11 and the substrate 10 form a trench 16 in the substrate. Next, referring to FIG. 1B, after removing the photoresist layer 14, a thin thermal oxide layer 18 is first grown. The formation method is, for example, performed at a temperature of about 900 to 1100 ° C, and the thickness is about 300 ~ 500A. Thereafter, a silicon oxide layer 20 is formed on the thermal silicon oxide layer 18, and the formation method is, for example, using atmospheric pressure chemical vapor deposition (APCVD) method, using tetra-ethyl-ortho-silicate (TEOS) as a reaction Gas source, using atmospheric pressure 4 paper sizes China State Standards (CNS) A4 size (210X297 mm) (Please read the precautions on the back before filling this page)
.IT 3325twf.doc/005 A7 B7 經济部中夾《苹豹只工消费合作相印y- 五、發明説明（今） 化學氣相沈積法沈積，使氧化物充滿溝渠。因TEOS氧化 矽層需經密實化（densification)步驟，在溫度約爲900°C 〜1100°C，時間約爲10-30分鐘。在密實化步驟之後，再以 化學機械硏磨法（chemical mechanical polishing, CMP)磨平 氮化矽層12上的TEOS氧化矽層20，而以氮化矽層12作 爲硏磨終點，在溝渠1S中形成氧化物插塞20,，如第1C 圖所示。 之後，請參照第1D圖，在形成STI結構的氧化物插 塞2〇’，並去除氮化矽層12與襯墊氧化矽層11後，以乾 式氧化(dry oxidation)的方式在基底10表面的主動區上形 成一閘極氧化矽層22。接著，以化學氣相沈積法沈積一多 晶砍層，而多晶砂層以離子植入法（ion implantation)植入 摻質再進行回火（anneaUiig)，亦可在多晶矽沈積時直接摻 入所需要的雜質，續再以微影蝕刻製程以形成元件的閘極 24 ° 習知以化學機械硏磨法去除塡充在溝渠之外的氧化矽 層’化學機械硏磨法所需成本較高，一次只可進行一片晶 圓的硏磨步驟，不利於提高製程的產能。 另外，請參照第2A圖與第2B圖，習知在美國專利案 號5,436，190中，揭露出另一種淺溝渠隔離的結構。 首先，請參照第2A圖，提供已形成有P井2〇2的P· 型半導體基底200，其中P井202中有一溝渠。先行在溝 渠之側壁形成氧化矽的間隙壁2〇4,之後再將多晶矽2〇6 塡充在溝渠中。塡充步驟包括先以化學氣相沈積法’形成 5 本紙張尺度適用中囤國家榇率（CNS ) Μ规格（21〇><297公釐） (請先閲讀背面之注f項再填寫本頁) 袭i 3325twf·doc/005 A7 五'發明説明（Y) 一層多晶矽層覆蓋在整個表面上，接著利用活性離子蝕刻 法去除溝渠之外的多晶矽層’僅留下塡充在溝渠中的多晶 矽 206。， 之後，請參照第2B圖，在基底的主動區上形成〜層 閘極氧化矽層’同時在溝渠中多晶矽206的表面上， 亦會形成一層氧化砍層21〇。 上述方法以活性離子餓刻去除多晶砂，並無法控制@ 刻後表面的平坦度，另外在溝渠上的氧化矽層210與閘極 氧化矽層208同時形成，但以目前積體電路而言，閘即氧 化矽層爲2〇〜100A，此時在溝渠上的氧化矽層大約只有 50〜200A，其隔離效果有限。 另外，在高寬比大的溝渠中，要利用多晶矽將溝渠$ 全塡滿而無空隙產生，以一般的化學氣相沈積法進行，其 效果令人質疑。 ' 有鑑於此，本發明的主要目的就是在提供一種淺溝渠 隔離的製造方法，以選擇性的化學氣相沈積法在溝渠中形 成多晶矽，且不需要利用到化學機械硏磨的方法，即可得 到平坦的淺溝渠隔離結構。 根據本發明的上述及其他目的，提出一種淺溝渠隔離 的製造方法。首先，在半導體基底上依序形成第一氧化砂 層、第一氮化矽層、第二氧化矽層；再進行微影步驟，以 光阻在第二氧化矽層上定義出主動元件區域，並以非等向 性触刻法去除未被光阻定義之第二氧化矽層、第一氮化矽 層' 第一氧化矽層及半導體基底，以在半導體基底上形成 6 本紙张纽^丨,^^^774^^—2^1-- (諳先閲讀背面之注意事項再4寫本頁}.IT 3325twf.doc / 005 A7 B7 The Ministry of Economic Affairs included the "Pingbao Leopard Consumption Cooperative Imprint y- 5. Description of the invention (now) chemical vapor deposition method, so that oxides fill the trench. Since the TEOS oxide silicon layer needs to undergo a densification step, the temperature is about 900 ° C ~ 1100 ° C, and the time is about 10-30 minutes. After the densification step, the TEOS silicon oxide layer 20 on the silicon nitride layer 12 is polished by chemical mechanical polishing (CMP), and the silicon nitride layer 12 is used as the honing end point in the trench 1S. The oxide plug 20 is formed in FIG. 1C as shown in FIG. 1C. After that, referring to FIG. 1D, after forming the oxide plug 20 ′ of the STI structure, and removing the silicon nitride layer 12 and the pad silicon oxide layer 11, the surface of the substrate 10 is dry-oxidized. A gate silicon oxide layer 22 is formed on the active region. Next, a polycrystalline cutting layer is deposited by chemical vapor deposition, and the polycrystalline sand layer is implanted with dopants by ion implantation and then tempered (anneaUiig). It can also be directly incorporated into the polycrystalline silicon during deposition. The required impurities are continued by the lithographic etching process to form the gate of the component 24 °. The chemical mechanical honing method is used to remove the silicon oxide layer filled outside the trench. The chemical mechanical honing method requires higher costs. Honing can only be performed on one wafer at a time, which is not conducive to increasing the throughput of the process. In addition, please refer to FIG. 2A and FIG. 2B. It is known in U.S. Patent No. 5,436,190 that another shallow trench isolation structure is disclosed. First, referring to FIG. 2A, a P · type semiconductor substrate 200 having a P well 202 formed therein is provided, wherein a trench is formed in the P well 202. First, a silicon oxide spacer 205 is formed on the side wall of the trench, and then polycrystalline silicon 206 is filled in the trench. The filling step includes first forming 5 paper sizes using the chemical vapor deposition method in the applicable national standard (CNS) M specification (21〇 > < 297mm) (please read the note f on the back before filling This page) i 3325twf · doc / 005 A7 Five 'invention description (Y) A polycrystalline silicon layer covers the entire surface, and then the polycrystalline silicon layer outside the trench is removed by the active ion etching method', leaving only the radon filled in the trench. Polycrystalline silicon 206. After that, please refer to FIG. 2B, a layer of gate silicon oxide layer is formed on the active area of the substrate. At the same time, an oxide chopper layer 21 will also be formed on the surface of the polycrystalline silicon 206 in the trench. The above method removes polycrystalline sand with active ion engraving, and cannot control the flatness of the surface after the engraving. In addition, a silicon oxide layer 210 and a gate silicon oxide layer 208 on the trench are formed at the same time, but in terms of the current integrated circuit, The gate or silicon oxide layer is 20 ~ 100A. At this time, the silicon oxide layer on the trench is only about 50 ~ 200A, and its isolation effect is limited. In addition, in trenches with a high aspect ratio, polysilicon is used to fill the trenches completely without voids, and the general chemical vapor deposition method is used, and its effect is questionable. '' In view of this, the main purpose of the present invention is to provide a manufacturing method for shallow trench isolation, which uses a selective chemical vapor deposition method to form polycrystalline silicon in the trench, and does not require the use of a chemical mechanical honing method. A flat shallow trench isolation structure is obtained. According to the above and other objects of the present invention, a manufacturing method for shallow trench isolation is proposed. First, a first sand oxide layer, a first silicon nitride layer, and a second silicon oxide layer are sequentially formed on a semiconductor substrate. Then, a photolithography step is performed to define an active device region on the second silicon oxide layer with a photoresist, and The second silicon oxide layer, the first silicon nitride layer, the first silicon oxide layer, and the semiconductor substrate, which are not defined by photoresist, are removed by an anisotropic etching method to form 6 pieces of paper on the semiconductor substrate ^ 丨, ^^^ 774 ^^-2 ^ 1-- (谙 Read the notes on the back first and then write this page)
經"部中决《準而只工消fr合作私印繁 3325twf.doc/005 A7 B7 ________ 五、發明説明（Γ ) 溝渠。利用離子植入的方式，在溝渠下方的半導體基底中 形成通道阻絕(channel stop)。之後，全面覆蓋上一層第二 氮化矽層，並回蝕刻以在溝渠的側壁形成間隙壁。接著’ 選擇性的沈積多晶矽在暴露出來的半導體基底上。進行濕 式氧化反應（wet oxidation)，使塡充在溝渠的多晶矽上方 反應，形成氧化物。利用活性離子蝕刻進行非等向性的蝕 刻，去除第二氧化矽層、第一氮化矽層、第一氧化矽層、 部分的氧化物與部分的間隙壁，僅留下塡充在溝渠中的多 晶矽以及包覆多晶矽的氧化物，至此即得到一淺溝渠隔離 結構。 在上述的製造方法中，主要是在溝渠的側壁形成氮化 矽間隙壁，以遮蔽助溝渠的側壁，僅暴露出溝渠底部的矽 基底。接著便可利用選擇性化學氣相沈積法，只在溝渠中 暴露的矽基底上沈積多晶矽。然後再進行氧化，使多晶矽 上方形成氧化物，以塡滿溝渠。最後再利用蝕刻即可形成 隔離效果佳且平坦的淺溝渠隔離結構，而不須使用費時且 成本高的化學機械硏磨方法。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1A圖至第1D圖繪示係爲習知的一種淺溝渠隔離製 造方法之流程圖； 第2A圖與第2B圖繪示爲習知的另一種淺溝渠隔離結 7 本紙張尺度適用t國國家榇準（CNS ) Μ規格（210x297^5") ---γ----------.1T------^:· (請先閱讀背面之注意事項再填寫本頁) 3325twf.doc/005 A7 B7 五、發明説明（心） 構之剖面簡示圖；以及 第3A圖至第3F圖繪示依照本發明一較佳實施例的淺 溝渠隔離製造方法之流程圖。 圖示標記說明： 10,200,300 基底 ,11,18,20,210,302,306 氧化矽層 12,304 氮化矽層 14 光阻層 16,308 溝渠 20’氧化物插塞 22,208 閘極氧化矽層 24 閘極 202 P 井 204,310 _ 隙壁 312 多晶矽 314 氧化物 實施例 首先，請參照第3A圖，提供一半導體基底300，其材 質比如爲矽基底，依序在基底300上形成第一氧化矽層 302、第一氮化矽層304、以及第二氧化矽層306。其中， 第一氧化矽層302係用以作爲襯墊氧化矽層，其厚度約爲 200A ;第一氮化矽層304之厚度約爲2000A ;而第二氧化 矽層306厚度約爲200〜500A。 接著，請參照第3B圖，進行微影蝕刻步驟，以光阻 8 (請先閱讀背面之注意事項再填寫本頁)According to the Ministry of Justice's decision, "Quality and only work consumer fr cooperation private printing 3325twf.doc / 005 A7 B7 ________ V. Description of invention (Γ) ditch. Using ion implantation, a channel stop is formed in the semiconductor substrate below the trench. After that, a second silicon nitride layer is completely covered and etched back to form a gap wall on the sidewall of the trench. Next, the polycrystalline silicon is selectively deposited on the exposed semiconductor substrate. Wet oxidation is performed to cause the hafnium charge to react over the polycrystalline silicon in the trench to form an oxide. Anisotropic etching is performed by using active ion etching to remove the second silicon oxide layer, the first silicon nitride layer, the first silicon oxide layer, part of the oxide and part of the gap, leaving only the radon filled in the trench. The polycrystalline silicon and the oxide covering the polycrystalline silicon thus obtained a shallow trench isolation structure. In the above manufacturing method, a silicon nitride spacer is mainly formed on the sidewall of the trench to shield the sidewall of the trench, and only the silicon substrate at the bottom of the trench is exposed. Selective chemical vapor deposition can then be used to deposit polycrystalline silicon only on the silicon substrate exposed in the trench. Oxidation is then performed to form an oxide over the polycrystalline silicon to fill the trench. Finally, etching can be used to form a shallow trench isolation structure with good isolation and flatness, without using a time-consuming and costly chemical mechanical honing method. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1A to FIG. Figure 1D is a flow chart of a conventional shallow trench isolation manufacturing method; Figures 2A and 2B show another conventional shallow trench isolation junction. 7 This paper is applicable to national standards (CNS) ) Μ specifications (210x297 ^ 5 ") --- γ ----------. 1T ------ ^: (Please read the precautions on the back before filling this page) 3325twf.doc / 005 A7 B7 V. A schematic cross-sectional view of the invention description (heart) structure; and FIGS. 3A to 3F show a flowchart of a method for manufacturing a shallow trench isolation according to a preferred embodiment of the present invention. Description of icons: 10,200,300 substrate, 11,18,20,210,302,306 silicon oxide layer 12,304 silicon nitride layer 14 photoresist layer 16,308 trench 20 'oxide plug 22,208 gate silicon oxide layer 24 gate 202 P well 204,310 _ gap wall 312 Example of Polycrystalline Silicon 314 Oxide First, referring to FIG. 3A, a semiconductor substrate 300 is provided. The material is, for example, a silicon substrate. A first silicon oxide layer 302, a first silicon nitride layer 304 are sequentially formed on the substrate 300, and The second silicon oxide layer 306. Among them, the first silicon oxide layer 302 is used as a pad silicon oxide layer, and its thickness is about 200A; the thickness of the first silicon nitride layer 304 is about 2000A; and the thickness of the second silicon oxide layer 306 is about 200 ~ 500A. . Next, please refer to Figure 3B for the lithography etching step to photoresist 8 (Please read the precautions on the back before filling this page)
本好&尺度i用中國國家標f ( CNS )八4说格（210X297公楚) 經：Ϊί部中央iT蜱而U.T-消於合作社印$t 3325twf.doc/005 八7 Γ_______ _Β7 五、發明説明（Ί ) 層307在第二氧化矽層306上定義出主動元件區域(未顯 示）’並以非等向性蝕刻法去除未被光阻層307定義之第 二氧化矽層306、第一氮化矽層304、第一氧化矽層302 與半導體基底300，在半導體基底300中形成溝渠308， 此溝渠308之深度範圍約爲0.2〜Ι.Ομιη。 ，， 之後，請參照第3C圖，於移除光阻層307以後，進 行離子植入步驟，在溝渠308底部暴露出的半導體基底300 中形成通道阻絕309。然後在溝渠308的側壁形成間隙壁 31〇’厚度約爲0.1〜〇.2μιη，材質比如爲氮化矽。形成方式， 比如全面覆蓋一層第二氮化矽層（未顯示），然後進行回鈾 刻（etching back)的步驟，貝卩可形成間隙壁310 〇 接著，請參照第3D圖，在具間隙壁310的溝渠308 中塡入多晶矽312,塡充多晶矽312的方法比如以選擇性 化學氣相沈積進行。其沈積條件比如爲在溫度爲l〇〇〇°C、 壓力爲80torr中，以二氯矽甲烷(SiCl2H2)與氯化氫(HC丨)作 爲氣體源；或是比如爲溫度600°C、壓力lmtorr，以矽甲 烷（SiH4)與氫氣(H2)作爲氣體源。由於是進行選擇性的沈 積，故多晶矽僅會形成在矽基底300暴露出來的表面上， 而不會全面性的覆蓋。 之後，請參照第3E圖，進行氧化步驟’以使多晶矽312 的上方部分反應形成氧化物314。 接著，請參照第3F圖，去除第二氧化矽層306、第一 氮化矽層304、第一氧化矽層302、部分的氧化物314，以 及部分的間隙壁310，去除方法比如爲活性離子蝕刻，藉 9 本紙張尺度適用t國國家標準（CNS ) A4規格（210X297公釐） 1^---7------ (婧先閲讀背面之注f項再填寫本頁) 訂- 3325twf.doc/005 A7 B7 五、發明説明（孓） 以完成淺溝渠隔離的結構。 此外，也可以在第3E圖所繪示的結構形成後，續以 化學氣相沈積法，在其上形成如硼磷矽化玻璃(BPSG)、或 磷矽玻璃(PSG)等氧化物，再進行平坦化製程以使表面更 爲平坦。 ，因此，本發明的特徵在於提供一種淺溝渠隔離的製造 方法，利用蝕刻步驟取代習知以化學機械硏磨達到平坦化 的效果，因爲化學機械硏磨一次僅可以進行一片晶圓的平 坦化製程，對於大量生產有其限制，本發明提供之方法可 同時對一批晶圓進行，藉此可提高其產量。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 {請先閲讀背面之注意事項再填耗本頁)The standard & scale i uses the Chinese national standard f (CNS) 8 (4) (210X297 Gongchu) by: Ϊ Ministry of Central iT ticks and UT-eliminated by the cooperative printed $ t 3325twf.doc / 005 8 7 Γ _______ _Β7 V. Description of the invention (ii) The layer 307 defines an active device region (not shown) on the second silicon oxide layer 306 and removes the second silicon oxide layer 306, A silicon nitride layer 304, a first silicon oxide layer 302, and a semiconductor substrate 300 form a trench 308 in the semiconductor substrate 300, and the depth of the trench 308 is about 0.2 to 1.0 μm. After that, referring to FIG. 3C, after removing the photoresist layer 307, an ion implantation step is performed to form a channel stop 309 in the semiconductor substrate 300 exposed at the bottom of the trench 308. Then, a partition wall 31o 'is formed on the side wall of the trench 308 to have a thickness of about 0.1 to 0.2 μm, and the material is, for example, silicon nitride. The formation method, for example, a second silicon nitride layer (not shown) is completely covered, and then a step of etching back is performed, and the bead can form a spacer 310. Then, referring to FIG. 3D, The method of filling polycrystalline silicon 312 into trench 308 of 310 and filling polycrystalline silicon 312 is performed by, for example, selective chemical vapor deposition. The deposition conditions are, for example, at a temperature of 1000 ° C and a pressure of 80torr, using dichlorosilane (SiCl2H2) and hydrogen chloride (HC 丨) as the gas source; or, for example, a temperature of 600 ° C and a pressure of lmtorr, Silane (SiH4) and hydrogen (H2) were used as gas sources. Because selective deposition is performed, polycrystalline silicon is only formed on the exposed surface of the silicon substrate 300, and it is not covered comprehensively. After that, referring to FIG. 3E, an oxidation step is performed to react the upper portion of the polycrystalline silicon 312 to form an oxide 314. Next, referring to FIG. 3F, the second silicon oxide layer 306, the first silicon nitride layer 304, the first silicon oxide layer 302, part of the oxide 314, and part of the spacer 310 are removed. The removal method is, for example, active ions Etching, borrow 9 paper sizes to apply national standards (CNS) A4 specifications (210X297 mm) 1 ^ --- 7 ------ (Jing first read the note f on the back before filling this page) Order- 3325twf.doc / 005 A7 B7 V. Description of the invention (孓) Complete the structure of shallow trench isolation. In addition, after the structure shown in FIG. 3E is formed, an oxide such as borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG) may be formed thereon by a chemical vapor deposition method and then performed. The planarization process makes the surface more flat. Therefore, the present invention is characterized by providing a manufacturing method for shallow trench isolation, using an etching step instead of the conventional chemical mechanical honing to achieve the planarization effect, because the chemical mechanical honing can only perform the planarization process of one wafer at a time. There are limitations to mass production. The method provided by the present invention can be performed on a batch of wafers at the same time, thereby increasing its yield. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling this page)
T MM部中戎«.ίν·Λ·-=ί 工消f 合作=»i印聚 本紙張尺度述用中囤國家標隼（CNS ) A4規格（2l〇X297公釐）T MM Department Zhongrong «.ίν · Λ ·-= ί 工 消 f cooperation =» i Yinju This paper uses the national standard (CNS) A4 specification (210 × 297 mm) in this paper.