經濟部中央橾準局負工消费合作社印11 五、發明説明（I) 技術領域： 本發明係有關於一種積體電路中的淺渠溝隔離 (Shallow Trench Isolation ; STI)方法，特別是有關於一 種可避免頸結效應(Kink Effect)產生的隔離方法。 發明背景： 近幾年來，由於積體電路中記憶元密度的快速增加，各 電晶體之間的間隔也越來越小。爲了確保電晶體的運作不會 受到其他電晶體的干擾，因而必須設法將所有電晶體彼此隔 離起來，以防止閉鎖(Latch Up)現象的發生，璋樣的製程技 術被稱爲隔離製程（Isolation Process)。 以往廣被業界使用的隔離製程是區域氧化法(Local Oxidation; LOCOS)。它是利用熱氧化技術在各電晶體之間 形成厚度達幾千埃的場氧化層，利用二氧化矽的不導電性來 形成各電晶體之間的阻隔。然而，上述之區域氧化法有一項 無法避免的缺點，即是在使用濕式氧化法形成場氧化層時會 有鳥嘴(Bird’s Beak)的現象發生，影響到後續主動元件區域 的製程。當積體電路的製程技術進入次微米或深次微米之 後，上述鳥嘴現象造成的不良影響將更加嚴重。另外，在形 成場氧化層之前，通常會以P型離子進行離子佈植，再藉高 溫步驟將之趨入矽基板內來形成通道阻絕(Channel Stop)。 在積體電路的製程技術進入次微米或深次微米之後，後續許 多高溫步驟將可能造成過度的熱擴散，而導致嚴重的窄寬度 效應(Narrow-Width Effects)。爲因應次微米或深次微米製 2 (請先閲讀背面之注意事項再填寫本頁}Printed by the Central Economic and Trade Standards Bureau, Ministry of Economic Affairs and Consumer Cooperatives 11 V. Description of the Invention (I) Technical Field: The present invention relates to a Shallow Trench Isolation (STI) method in integrated circuits, and more particularly to An isolation method that can avoid the Kink Effect. BACKGROUND OF THE INVENTION: In recent years, due to the rapid increase in the density of memory cells in integrated circuits, the interval between transistors has also become smaller and smaller. In order to ensure that the operation of the transistor is not interfered by other transistors, it is necessary to try to isolate all transistors from each other to prevent the occurrence of latch-up (Latch Up) phenomenon. The same process technology is called isolation process (Isolation Process ). The isolation process widely used in the industry in the past is Local Oxidation (LOCOS). It uses thermal oxidation technology to form a field oxide layer between the transistors with a thickness of several thousand angstroms, and uses the non-conductivity of silicon dioxide to form the barrier between the transistors. However, the above-mentioned area oxidation method has an unavoidable disadvantage, that is, when a field oxide layer is formed by a wet oxidation method, a bird's beak phenomenon occurs, which affects the subsequent process of the active device region. When the integrated circuit process technology enters the sub-micron or deep sub-micron, the adverse effects caused by the aforementioned bird's beak phenomenon will become more serious. In addition, before the field oxide layer is formed, ion implantation is usually performed with P-type ions, and then a high temperature step is used to inject the ions into the silicon substrate to form a channel stop. After the integrated circuit process technology enters the sub-micron or deep sub-micron, many subsequent high-temperature steps may cause excessive thermal diffusion, resulting in severe narrow-width effects. For sub-micron or deep sub-micron 2 (Please read the precautions on the back before filling this page}
、1T 本紙張尺度適用中圃國家橾準（CNS ) Α4规格（210Χ 297公釐） 經濟部中央標準局負工消费合作社印製 ____b：___________4027A1 五、發明説明（>) 程的需求，許多新的隔離製程技術被開發出來以取代區域氧 化法。 其中最被看好的一種稱爲淺渠溝隔離(Shallow Trench Isolation)。參考圖一 A，所述淺渠溝隔離技術是先在矽基 板11上依序覆蓋一層二氧化矽墊層13和氮化矽層15，然 後，進行局部蝕刻以形成淺渠溝12，再回填介電層17，並 利用化學機械研磨(Chemical Mechanical Polishing ; CMP) 進行回蝕刻步驟，便完成淺渠溝隔離，在所述淺渠溝隔離之 間爲主動元件區域14。由於氮化矽層15本身爲較硬的材 料，因而在化學機械研磨製程中，若同時磨到氮化矽層15 與介電層17時，容易造成介電層表面形成研磨傷痕 (Scratch)，而且在後續製程中，當使用濕蝕刻除去氮化矽 層15時，由於蝕刻等向（Isotropic)之特性，會在主動元件 區域14與淺渠溝12的界面上留下一凹痕19，如圖一 B所 示，此凹痕19亦會使得接下來的氧化、蝕刻製程中，在淺 渠溝12兩側形成更嚴重的氧化凹壁(〇xide-Recess)19a，如 圖一 B中之虛線所示，此即所謂的頸結效應，這對後續所形 成的電晶體，會出現不正常導通(Turn-On)或提早導通的現 象。因此以傳統淺渠溝隔離技術所後續形成的電晶體，將無 法滿足積體電路的電性需求。 發明之概述： 本發明之主要目的爲提供一種積體電路中的淺渠溝隔 離方法，以複晶矽(Polysilicon)取代氮化矽，形成一氧化 3 本紙張尺度適用中國國家揉準（CNS > A4規格（21〇Χ297公楚1 " " ---------1 裝—►---—訂 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印«. ---------------------- 五、發明説明（)) 層，並於淺渠溝形成後，在複晶矽層側壁形成一氧化側壁子 (Oxide Spacer) ’可有效避免頸結效應之發生》 本發明之次要目的爲提供一種積體電路中的淺渠溝隔 離方法，以複晶矽取代氮化矽，形成一氧化層，並於淺渠溝 形成後，在複晶矽層側壁形成一氧化側壁子，可滿足積體電 路之電性需求。 本發明之再一目的爲提供一種積體電路中的淺渠溝隔 離方法，以複晶矽取代氮化矽，作爲淺渠溝隔離中，回蝕刻 步驟之蝕刻終止層(Stop Layer)，可避免在介電層上造成研 磨傷痕。 爲了達到上述之各種目的，本發明使用了以下的方法： 首先，在矽基板上依序形成一層二氧化矽墊層和複晶矽層， 利用微影技術，定義出主動元件區域，再利用熱氧化法在基 板上裸露出含矽部份形成一氧化層，進行回蝕刻以形成淺渠 溝，使得上述複晶矽層側壁形成一氧化側壁子，然後在淺渠 溝中回填介電層，接著利用化學機械研磨法，將主動元件區 域上面的介電層磨掉，以複晶矽層作爲蝕刻終止層，去除主 動元件區域上之複晶矽層後，於淺渠溝兩側會有上述氧化層 形成之氧化側壁子，在後續的氧化、蝕刻製程中能保護淺渠 溝不被侵蝕，避免頸結效應之產生。 式簡要說明： 圖一 A爲習知技藝形成淺渠溝隔離之晶圓剖面圖； 圖一 B爲習知技藝淺渠溝隔離技術於主動元件區域與淺 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） ---------LV----：--.~ 訂------,1 (請先閱讀背面之注意事項再填寫本頁) 五、發明説明（ 402781 渠溝界面上留下凹痕之晶圓剖面圖； 圖二A爲本發明淺渠溝隔離技術形成二氧化矽墊層和複 晶矽層之晶圓剖面圖； 圖二B爲本發明淺渠溝隔離技術定義主動元件區域之晶 圓剖面圖； 圖二C爲本發明淺渠溝隔離技術於基板上形成氧化層之 晶圓剖面圖； 圖二D爲本發明淺渠溝隔離技術形成淺渠溝之晶圓剖面 Igl · 圖， 圖二E爲本發明淺渠溝隔離技術回填介電餍之晶圓剖面 ιβ · 圖， 圖二F爲本發明淺渠溝隔離技術磨去主動元件區域上方 介電層且磨到複晶矽層之晶圓剖面圖； 圖二G爲本發明淺渠溝隔離技術去除複晶矽層及二氧化 矽墊層後之晶圓剖面圖。 ---------;/w-- (請先閱讀背面之注意事項再填寫本頁)、 1T This paper size is applicable to China National Standards for Standards (CNS) Α4 (210 × 297 mm) Printed by the Central Consumers Bureau of Ministry of Economic Affairs and Consumer Cooperatives ____b: ___________4027A1 V. Demand for Invention (>) Process requirements, many New isolation process technology was developed to replace the area oxidation method. One of the most promising is called Shallow Trench Isolation. Referring to FIG. 1A, in the shallow trench isolation technology, a silicon dioxide pad layer 13 and a silicon nitride layer 15 are sequentially covered on the silicon substrate 11 in sequence, and then a partial etching is performed to form the shallow trench 12 and then backfilled. The dielectric layer 17 is subjected to an etch-back step using Chemical Mechanical Polishing (CMP) to complete the shallow trench isolation, and the active device region 14 is between the shallow trench isolations. Since the silicon nitride layer 15 itself is a harder material, if the silicon nitride layer 15 and the dielectric layer 17 are simultaneously ground during the chemical mechanical polishing process, it is easy to cause a scratch on the surface of the dielectric layer. Moreover, in the subsequent process, when the silicon nitride layer 15 is removed by wet etching, a dent 19 is left on the interface between the active device region 14 and the shallow trench 12 due to the characteristic of isotropic etching, such as As shown in FIG. 1B, this dent 19 will also cause a more severe oxidation-recess wall 19a on both sides of the shallow trench 12 during the subsequent oxidation and etching processes, as shown in FIG. 1B. As shown by the dashed line, this is the so-called neck-knot effect, which will cause the phenomenon of abnormal turn-on or early turn-on of the transistor formed later. Therefore, the transistor formed by the traditional shallow trench isolation technology cannot meet the electrical requirements of the integrated circuit. Summary of the invention: The main purpose of the present invention is to provide a method for isolating shallow trenches in integrated circuits. Polysilicon is used instead of silicon nitride to form monoxide. This paper is applicable to Chinese national standards (CNS > A4 specification (21〇 × 297 公 楚 1 " " --------- 1 installed —► ---— order (please read the precautions on the back before filling this page) Central Bureau of Standards, Ministry of Economic Affairs Shelley Consumer Cooperatives printed «. ---------------------- V. Description of the invention ()) layer, and after the formation of the shallow trench, the polycrystalline silicon Oxide Spacer is formed on the side wall of the layer, which can effectively prevent the occurrence of the neck knot effect. The secondary object of the present invention is to provide a method for isolating shallow trenches in integrated circuits, replacing silicon nitride with polycrystalline silicon. An oxide layer is formed, and after the shallow trench is formed, an oxide sidewall is formed on the side wall of the polycrystalline silicon layer, which can meet the electrical requirements of integrated circuits. Another object of the present invention is to provide a shallow layer in integrated circuits. The trench isolation method uses polycrystalline silicon instead of silicon nitride as the etch stop layer in the etch-back step in shallow trench isolation (Sto p Layer), which can avoid grinding scars on the dielectric layer. In order to achieve the above-mentioned various purposes, the present invention uses the following methods: First, a silicon dioxide pad layer and a polycrystalline silicon layer are sequentially formed on a silicon substrate. Using photolithography technology to define the active device area, and then using thermal oxidation to expose a silicon-containing portion on the substrate to form an oxide layer, and etch back to form a shallow trench, so that the sidewalls of the polycrystalline silicon layer form an oxide. Sidewall, and then backfill the dielectric layer in the shallow trench, and then use chemical mechanical polishing to remove the dielectric layer above the active device area, and use the polycrystalline silicon layer as an etch stop layer to remove the After crystallizing the silicon layer, there will be oxidized sidewalls formed by the above-mentioned oxide layer on both sides of the shallow trench, which can protect the shallow trench from being eroded in the subsequent oxidation and etching processes, and avoid the occurrence of the neck knot effect. Figure 1A is a cross-sectional view of a wafer with shallow trenches formed by conventional techniques; Figure 1B is a shallow trench isolation technique with conventional techniques in the active device area and shallow Home Standard (CNS) A4 Specification (210X 297 mm) --------- LV ----:-. ~ Order ------, 1 (Please read the precautions on the back first (Fill in this page) V. Description of the invention (402781 Cross section of the wafer leaving a dent on the trench interface; Figure 2A is a cross section of the wafer formed by the shallow trench isolation technology of the present invention to form a silicon dioxide cushion layer and a polycrystalline silicon layer Figure 2B is a cross-sectional view of a wafer defining the active device region of the shallow trench isolation technology of the present invention; Figure 2C is a cross-sectional view of a wafer forming an oxide layer on the substrate by the shallow trench isolation technology of the present invention; Figure 2D is Igl · diagram of the wafer section formed by the shallow trench isolation technology of the present invention. Fig. 2E is a diagram of the wafer section of the shallow trench isolation technology backfilling dielectric ιβ. · Fig. 2F is the shallow channel of the invention. The trench isolation technology is a cross-sectional view of a wafer where the dielectric layer above the active device region is removed and the compound silicon layer is polished. Circle section view. ---------; / w-- (Please read the notes on the back before filling this page)
、1T 經濟部中央標準扃員工消費合作社印裝 明搬明： 11-矽基板 13-二氧化矽墊層 15-氮化矽層 19-凹痕 21-複晶矽層 23a-氧化側壁子 12-淺渠溝 14-主動元件區域 17-介電層 19a-氧化凹壁 23-氧化層 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 五、發明説明（ 發明胖緬說明： 本發明是有關於一種積體電路中的淺渠溝隔離方法，在 詳細說明中是運用具體實施例說明本發明的原則與精神^ 參考圖二，首先，在矽基板11上依序沉積一層二氧化 矽墊層13和一層複晶矽層21，如圖二A所示’該複晶=層 21通常爲摻雜有磷離子的複晶矽，其摻雜濃度約爲if〜 10Mcm3，其厚度大約爲1000至2000埃之間，但是’該複 晶矽層21也可以是無摻雜的複晶矽，只要是與其下的二氧 化矽蝕刻速率比(Etch Rate Ratio)夠大即可。接著’利用 微影蝕刻技術，蝕刻上述之複晶矽層21及；氧化矽墊層 13，定義出主動元件區域14，如圖二B所示。 經濟部中央標準局貝工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 然後，利用熱氧化法，在上述矽基板11表面與複晶矽 層21表面及側壁上，形成一層氧化層23，如圖二C所示， 該熱氧化製程使用的溫度約爲850 °C至900 °C之間，而位 於複晶矽層21表面及側壁上之該氧化層23，是一種複晶矽 的氧化物，其厚度約爲6GG埃左右，此步驟是本發明的重 點，因爲該氧化層23的存在，接下來，在使用對矽(Si)與 二氧化矽(Si〇2)蝕刻速率比大於20的溶液，繼續進行濕蝕 刻，以形成隔離所需的淺渠溝12(如圖二D所示)時，位於複 晶矽層21側壁上之該氧化層23，會形成一氧化側壁子23a， 其寬度L2約爲3GG至800埃之間，該足夠寬度L2的氧化側壁 子23a，可防止淺渠溝12兩側，產生上述之氧化凹壁19a。 接著’在淺渠溝12中回填出一層介電層Π，該介電層 17乃是利用電槳化學氣相沉積法（Plasma-Enhanced 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局貝工消费合作社印簟 402781 五、發明说明（i)、 1T Central Standards of the Ministry of Economic Affairs and Employees ’Cooperatives, printed and removed: 11-silicon substrate 13-silicon dioxide cushion layer 15-silicon nitride layer 19-dents 21-polycrystalline silicon layer 23a-oxidized sidewall 12- Shallow trench 14-Active element area 17-Dielectric layer 19a-Oxidation recessed wall 23-Oxidation layer This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) 5. Description of the invention The invention relates to a method for isolating shallow trenches in integrated circuits. In the detailed description, specific embodiments are used to illustrate the principles and spirit of the present invention. Referring to FIG. 2, first, a layer of dioxide is sequentially deposited on the silicon substrate 11. The silicon pad layer 13 and a polycrystalline silicon layer 21 are shown in FIG. 2A. The polycrystalline layer = layer 21 is usually polycrystalline silicon doped with phosphorus ions. Its doping concentration is about if ~ 10Mcm3, and its thickness is about It is between 1000 and 2000 Angstroms, but 'the polycrystalline silicon layer 21 may also be undoped polycrystalline silicon, as long as the Etch Rate Ratio is sufficiently large below it. Then' Lithographic etching technology is used to etch the above-mentioned polycrystalline silicon layer 21 and silicon oxide Layer 13 defines the active component area 14, as shown in Figure 2B. Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Then, use the thermal oxidation method above An oxide layer 23 is formed on the surface of the silicon substrate 11 and the surface and side walls of the polycrystalline silicon layer 21, as shown in FIG. 2C. The temperature of the thermal oxidation process is about 850 ° C to 900 ° C, and it is located in the complex The oxide layer 23 on the surface and the sidewall of the crystalline silicon layer 21 is an oxide of polycrystalline silicon, and its thickness is about 6GG angstroms. This step is the focus of the present invention because of the existence of the oxide layer 23. Next, When a solution with an etching rate ratio of silicon (Si) to silicon dioxide (SiO2) greater than 20 is used, wet etching is continued to form a shallow trench 12 (as shown in FIG. 2D) required for isolation. The oxide layer 23 on the sidewall of the polycrystalline silicon layer 21 will form an oxide sidewall 23a with a width L2 of about 3GG to 800 angstroms. The oxide sidewall 23a with a sufficient width L2 can prevent the shallow trench 12 Side, the above-mentioned oxidized concave wall 19a is generated. Then, 'backfill in the shallow trench 12' Layer dielectric layer Π, the dielectric layer 17 is made by the electric paddle chemical vapor deposition method (Plasma-Enhanced) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) Cooperative seal 402781 V. Description of invention (i)
Chemical Vapor Deposition ; PECVD)沉積而成的二氧化 矽層，再利用化學機械研磨法，對於上述之介電層17，進 行回蝕刻步驟，待磨到複晶矽層21後即停止蝕刻，如圖二F 所示。最後，去除上述之複晶矽層21以及二氧化砂塾層13， 如圖二G所示，如此，便可進行電性元件如：閘氧化層之製 作。 本發明使用複晶矽來取代氮化矽，乃是因爲複晶矽可以 很容易形成氧化層23，因而利用該氧化層23形成之氧化側 壁子23a，以其足夠之寬度，在後續的氧化、蝕刻製程中能 保護淺渠溝12不被侵蝕，避免形成上述之氧彳I；凹壁19a， 可達到良好的隔離效果，進而防止了頸結效應之產生。 上述說明係以較佳實施例來闡述本發明，而非限制本發 明，並且熟知半導體技藝之人士皆能明瞭，適當而作些微的 改變及調整，仍將不失本發明之要義所在，亦不脫離本發明 之精神和範圍。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁)Chemical Vapor Deposition; PECVD) silicon dioxide layer, and then chemical mechanical polishing method, the above dielectric layer 17 is subjected to an etch-back step. After the polycrystalline silicon layer 21 is ground, the etching is stopped, as shown in the figure. Shown in F. Finally, the above-mentioned polycrystalline silicon layer 21 and sand dioxide layer 13 are removed, as shown in FIG. 2G. In this way, an electrical component such as a gate oxide layer can be manufactured. The present invention uses polycrystalline silicon instead of silicon nitride because the polycrystalline silicon can easily form the oxide layer 23, and therefore the oxide sidewalls 23a formed by the oxide layer 23 have a sufficient width for subsequent oxidation, During the etching process, the shallow trench 12 can be protected from being eroded, and the above-mentioned oxygen ions I can be prevented from being formed; the concave wall 19a can achieve a good isolation effect, thereby preventing the generation of a neck knot effect. The above description is to illustrate the present invention with a preferred embodiment, but not to limit the present invention. Those skilled in the art of semiconductors can understand that making appropriate changes and adjustments will still not lose the essence of the present invention. Depart from the spirit and scope of the present invention. This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page)