KR100913004B1 - Method of forming trench in semiconductor device - Google Patents

Method of forming trench in semiconductor device Download PDF

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KR100913004B1
KR100913004B1 KR1020060085771A KR20060085771A KR100913004B1 KR 100913004 B1 KR100913004 B1 KR 100913004B1 KR 1020060085771 A KR1020060085771 A KR 1020060085771A KR 20060085771 A KR20060085771 A KR 20060085771A KR 100913004 B1 KR100913004 B1 KR 100913004B1
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forming
film
trench
pattern
acl
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KR20080022398A (en
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이인노
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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Abstract

본 발명은 반도체 소자의 트랜치 형성 방법에 관한 것으로, 폴리실리콘 하드 마스크막 대신에 ACL 하드마스크를 이용함으로써 낮은 두께의 감광막을 형성할 수 있고, 마스크 패턴의 마진을 크게 향상시킬 수 있게 되어 패턴 불량에 의한 일드 손실을 최소화할 수 있는 방법을 개시하였다.The present invention relates to a method for forming a trench in a semiconductor device, and by using an ACL hard mask instead of a polysilicon hard mask film, a photoresist film having a low thickness can be formed, and the margin of the mask pattern can be greatly improved. Disclosed is a method capable of minimizing yield loss.

반도체 소자, 듀얼 트랜치, ACL 하드마스크, SiON, ISO 식각 Semiconductor Devices, Dual Trench, ACL Hardmask, SiON, ISO Etch

Description

반도체 소자의 트랜치 형성 방법{Method of forming trench in semiconductor device}Method of forming trench in semiconductor device

도 1 내지 도 9는 본 발명에 따른 반도체 소자의 트랜치 형성 방법을 나타낸 도면이다.1 to 9 are diagrams showing a trench forming method of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

101 : 반도체 기판 102 : 게이트 산화막101 semiconductor substrate 102 gate oxide film

103 : ISO 마스크막 104 : ACL 하드 마스크막103: ISO mask film 104: ACL hard mask film

105 : SiON막 106 : 제 1 감광막 패턴105 SiON film 106 First photosensitive film pattern

107 : 제 2 감광막 패턴 108 : 월 산화막107: second photosensitive film pattern 108: month oxide film

109 : ISO 갭필막109: ISO gap film

본 발명은 반도체 소자의 트랜치 형성 방법에 관한 것으로 특히, ACL(amorphous carbon layer)막을 적용하여 트랜치를 형성함으로써 후속 공정시 소 자의 특성을 향상시키는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a trench in a semiconductor device, and more particularly, to a method of improving trench characteristics by applying an amorphous carbon layer (ACL) film to form a trench.

일반적으로, 70나노 기술에서 SA-FG(self aligned floating gate) ISO 식각은 두꺼워진 ISO 질화막을 식각하기 위하여 폴리실리콘의 하드 마스크를 사용하여 왔다. 하지만, 집적도가 높아지면서 현재 60나노 이하급의 반도체 소자에서는 상대적으로 감광막의 두께는 더욱 낮아지게 되었다. 또한, 선폭이 줄어듦에 따라서 감광막으로 폴리실리콘 하드 마스크를 식각하는 것이 어렵게 되었다. In general, self-aligned floating gate (SA-FG) ISO etching in 70-nm technology has used polysilicon hard masks to etch thickened ISO nitride films. However, as the degree of integration increases, the thickness of the photoresist film is relatively lower in current semiconductor devices of 60 nm or less. In addition, as the line width is reduced, it becomes difficult to etch the polysilicon hard mask with the photosensitive film.

종래에는 반도체 기판 상부에 게이트 산화막, ISO 마스크막 및 폴리실리콘 하드 마스크막을 적층한다. 하드 마스크막 상부에 감광막 패턴을 형성하고 감광막 패턴에 따라 식각하여 트랜치를 형성한다. 폴리실리콘 하드 마스크막을 사용하는 이유는 SA-FG 방법에서 후속 공정시 손실되는 량까지 고려하여 ISO 질화막을 약 1500Å의 두께로 두껍게 형성하게 되는데, 감광막만으로 식각공정을 수행하기에는 감광막 마진(margin)이 부족하기 때문이다. 이러한 폴리실리콘 하드 마스크를 이용하는 SA-FG 방법에서 60나노 이하의 소자에서 감광막이 감광막 두께가 낮아져 후속 공정을 어렵게 한다. 이에 의해, 선폭은 더욱 감소 되므로 폴리실리콘 하드 마스크를 식각하는 과정에서 감광막 마진이 부족하여 후속 ISO 마스크막 식각시 폴리실리콘 하드 마스크막이 유지되기가 어렵게 된다.Conventionally, a gate oxide film, an ISO mask film and a polysilicon hard mask film are laminated on a semiconductor substrate. A photoresist pattern is formed on the hard mask layer, and the trench is etched according to the photoresist pattern. The reason for using the polysilicon hard mask film is that the ISO nitride film is formed to a thickness of about 1500Å in consideration of the amount lost during the subsequent process in the SA-FG method. Because. In the SA-FG method using such a polysilicon hard mask, the photoresist film is lowered in the device having a thickness of 60 nm or less, which makes subsequent processing difficult. As a result, since the line width is further reduced, the photoresist margin is insufficient in the process of etching the polysilicon hard mask, so that the polysilicon hard mask layer is difficult to maintain during the subsequent etching of the ISO mask layer.

또한, SA-FG의 경우에는 ISO 마스크막이 두껍게 형성되는데 높은 아스펙비(aspect ratio)로 인하여 후속 절연체를 갭필(gap fill)하기가 어렵게 된다. 이를 해결하기 위해 반도체 기판의 프로파일을 경사지도록 형성하여야 한다. 그러나, 폴리실리콘 하드 마스크를 이용하여 반도체 기판 식각을 수행할 경우에 트랜치의 경사각을 낮추기가 상당히 어렵다. 따라서, 60나노 이하급의 반도체 소자 형성시 갭필 마진을 확보하기가 어렵게 된다. In addition, in the case of SA-FG, an ISO mask film is formed thick, and it is difficult to gap fill a subsequent insulator due to a high aspect ratio. In order to solve this problem, the profile of the semiconductor substrate should be formed to be inclined. However, it is quite difficult to lower the inclination angle of the trenches when etching a semiconductor substrate using a polysilicon hard mask. Therefore, it is difficult to secure a gap fill margin when forming a 60 nm or less semiconductor device.

따라서, 본 발명은 종래의 폴리실리콘 하드 마스크막 대신에 ACL 하드마스크를 이용하여 낮은 두께의 감광막을 형성하고 마스크 패턴의 마진을 크게 향상시키도록 하는 데 있다. Accordingly, the present invention is to form a photoresist film having a low thickness by using an ACL hard mask instead of the conventional polysilicon hard mask film and to greatly improve the margin of the mask pattern.

본 발명은 반도체 소자의 트랜치 형성 방법에 관한 것으로, 반도체 기판 상부에 게이트 산화막, ISO 마스크막을 형성하는 단계, ISO 마스크막 상부에 후속 마스크 마진을 증가시키도록 ACL 하드 마스크막을 형성하는 단계, ACL 하드 마스크막 상부에 낮은 두께의 SiON막을 형성하는 단계, SiON막 상부에 제 1 감광막 패턴을 형성한 후, 제 1 감광막 패턴에 따라 식각하여 SiON막 패턴 및 ACL 하드 마스크막 패턴을 형성하는 단계, SiON막 패턴에 따라 식각하여 ISO 마스크막 패턴 및 게이트 산화막 패턴을 형성하는 단계, ACL 하드 마스크막 패턴에 따라 반도체 기판을 식각하여 셀 영역의 트랜치를 형성하는 단계, ISO 마스크막 패턴 상부에 제 2 감광막 패턴을 형성한 후, 제 2 감광막 패턴에 따라 식각하여 주변 영역의 ISO 마스크막 패턴, 게이트 산화막 패턴 및 트랜치를 형성하는 단계 및 트랜치에 갭필하는 단계를 포함하는 반도체 소자의 트랜치 형성 방법을 포함한다.The present invention relates to a method for forming a trench in a semiconductor device, the method comprising: forming a gate oxide film and an ISO mask film on a semiconductor substrate, forming an ACL hard mask film to increase a subsequent mask margin on an ISO mask film, and an ACL hard mask Forming a SiON film having a low thickness on the film, forming a first photoresist film pattern on the SiON film, and etching the film according to the first photoresist film pattern to form a SiON film pattern and an ACL hard mask film pattern, and a SiON film pattern Forming an ISO mask layer pattern and a gate oxide layer pattern by etching, forming a trench in the cell region by etching the semiconductor substrate according to an ACL hard mask layer pattern, and forming a second photoresist layer pattern on the ISO mask layer pattern After etching according to the second photoresist pattern, an ISO mask pattern, a gate oxide pattern, and a trench in the peripheral region are formed. And forming a gap and filling the trench.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

도 1 내지 도 9는 본 발명에 따른 반도체 소자의 트랜치 형성 방법을 나타낸 도면이다.1 to 9 are diagrams showing a trench forming method of a semiconductor device according to the present invention.

도 1를 참조하면, 반도체 기판(101) 상부에 게이트 산화막(102), ISO 마스크막(103), ACL 하드 마스크막(104), SiON막(105) 및 제 1 감광막 패턴(106)을 형성한다. ISO 마스크막(103)은 질화막을 사용하고 두께는 1000 내지 2500Å가 되도록 형성한다. ACL 하드 마스크막(104)은 사용 물질로 비정질 카본막(amorphous carbon layer)을 사용하고 두께는 1500 내지 2500Å이 되도록 형성한다. 온도는 250℃ 또는 500℃ 내지 600℃의 온도에서 형성한다. 제 1 감광막 패턴(106)은 셀 영역이 게이트 패턴으로 오픈 되고 주변 영역은 차폐된다. 이는 주변 영역의 경우에 고전압 트랜지스터를 형성할 지역이 존재하므로 셀 영역에 비하여 상대적으로 트랜치를 깊게 형성해야 하기 때문이다. 즉, 셀 영역을 먼저 식각한 후 주변 영역에 게이트 패턴이 오픈된 다른 감광막 패턴으로 주변 영역을 식각 해야 하기 때문이다. Referring to FIG. 1, a gate oxide film 102, an ISO mask film 103, an ACL hard mask film 104, a SiON film 105, and a first photosensitive film pattern 106 are formed on a semiconductor substrate 101. . The ISO mask film 103 is formed using a nitride film and having a thickness of 1000 to 2500 kPa. The ACL hard mask film 104 is formed to use an amorphous carbon layer as a material and have a thickness of 1500 to 2500 kPa. The temperature is formed at 250 ° C or at a temperature of 500 ° C to 600 ° C. In the first photoresist pattern 106, a cell region is opened in a gate pattern, and a peripheral region is shielded. This is because in the peripheral region, since there is a region for forming the high voltage transistor, the trench must be formed deeper than the cell region. That is, the cell region must be etched first, and then the peripheral region must be etched by another photoresist pattern having a gate pattern open in the peripheral region.

도 2를 참조하면, 제 1 감광막 패턴(106)에 따라 SiON막(105)을 식각하여 SiON막 패턴(105a)을 형성하여 오픈 영역으로 ACL 하드 마스크막(104)이 드러나도록 한다. SiON막 패턴(105a)을 형성하는 이유는 SiON막이 후속 ACL 하드 마스크막(104)의 식각시 베리어(barrier)로 작용하기 때문이다. Referring to FIG. 2, the SiON film 105 is etched according to the first photoresist pattern 106 to form a SiON film pattern 105a so that the ACL hard mask film 104 is exposed to the open area. The reason for forming the SiON film pattern 105a is that the SiON film acts as a barrier during the etching of the subsequent ACL hard mask film 104.

도 3을 참조하면, 제 1 감광막 패턴(106)에 따라 ISO 마스크막(103)이 드러나도록 ACL 하드 마스크막(104)을 식각하여 ACL 하드 마스크막 패턴(104a)을 형성한다. 이때, 제 1 감광막 패턴(106)과 ACL 하드 마스크막(104)은 성분이 비슷하기 때문에 ACL 하드 마스크막(104) 식각시 제 1 감광막 패턴(106)은 쉽게 제거될 수 있다. 제 1 감광막 패턴(106)이 제거되어 SiON막 패턴(105a)이 상부에 드러나도록 한다. Referring to FIG. 3, the ACL hard mask film 104 is etched to expose the ISO mask film 103 according to the first photoresist pattern 106 to form an ACL hard mask film pattern 104a. In this case, since the components of the first photoresist layer pattern 106 and the ACL hard mask layer 104 are similar, the first photoresist layer pattern 106 may be easily removed when the ACL hard mask layer 104 is etched. The first photoresist layer pattern 106 is removed to expose the SiON layer pattern 105a thereon.

도 4를 참조하면, SiON막 패턴(105a)에 따라 ISO 마스크막(103) 및 게이트 산화막(102)을 식각하여 오픈 영역 사이로 반도체 기판(101)이 드러나도록 ISO 마스크막 패턴(103a) 및 게이트 산화막 패턴(102a)을 형성한다. SiON막 패턴(105a)은 ISO 마스크막 패턴(103)형성을 위한 식각시 쉽게 제거된다. SiON막 패턴(105a)이 제거된 이후에는 ACL 하드 마스크막 패턴(104)이 주요한 베리어로 작용하여 ISO 마스크막 패턴(103a), 게이트 산화막 패턴(102a)을 형성한다. ACL 하드 마스크막 패턴(104a)에 따라 반도체 기판(101)을 소정 깊이로 식각한다. Referring to FIG. 4, the ISO mask film 103 and the gate oxide film are etched according to the SiON film pattern 105a to expose the semiconductor substrate 101 between the open regions by etching the ISO mask film 103 and the gate oxide film 102. The pattern 102a is formed. The SiON film pattern 105a is easily removed during etching for forming the ISO mask film pattern 103. After the SiON film pattern 105a is removed, the ACL hard mask film pattern 104 acts as a major barrier to form the ISO mask film pattern 103a and the gate oxide film pattern 102a. The semiconductor substrate 101 is etched to a predetermined depth according to the ACL hard mask film pattern 104a.

한편, ACL 하드 마스크막 패턴(104a)에 따라 게이트 산화막 패턴(102a) 형성을 위한 식각시에 카본 폴리머(carbon polymer)가 많이 발생하므로 TCR(트렌치의 탑코너를 라운딩(rounding) 처리하는 기술) 형성이 유용하다. 또한, 반도체 기판(101) 식각 시에도 경사각을 증가시킬 수 있다. Meanwhile, since a large amount of carbon polymer is generated during etching for forming the gate oxide layer pattern 102a according to the ACL hard mask layer pattern 104a, TCR (a technique of rounding the top corner of the trench) is formed. This is useful. In addition, the inclination angle may be increased even when the semiconductor substrate 101 is etched.

도 5를 참조하면, ACL 하드 마스크막 패턴(104a)을 제거하고 전체구조 상부에 제 2 감광막 패턴(107)을 형성한다. 제 2 감광막 패턴(107)의 셀 영역 부분은 모두 차폐되어 있고 주변 영역 부분은 게이트 형성 패턴에 따라 오픈 되어 있다. Referring to FIG. 5, the ACL hard mask layer pattern 104a is removed and a second photoresist layer pattern 107 is formed on the entire structure. The cell region portions of the second photoresist pattern 107 are all shielded and the peripheral region portions are opened according to the gate formation pattern.

도 6을 참조하면, 제 2 감광막 패턴(107)에 따라 ISO 하드 마스크막 패턴(103a), 게이트 산화막 패턴(102a) 및 반도체 기판(101)을 식각한다. 이때, 주변 영역의 반도체 기판(101) 식각 깊이는 셀 영역보다 트랜치를 깊게 형성하도록 한다. Referring to FIG. 6, the ISO hard mask layer pattern 103a, the gate oxide layer pattern 102a, and the semiconductor substrate 101 are etched according to the second photoresist layer pattern 107. At this time, the etching depth of the semiconductor substrate 101 in the peripheral region is to form a trench deeper than the cell region.

도 7을 참조하면, 제 2 감광막 패턴(107)을 제거한 후 전면부 표면을 따라 월 산화막(wall oxide; 108)을 형성한다. 트랜치가 매립되도록 ISO 갭필막(109)을 형성한다. ISO 갭필막(109) 형성 물질로는 HDP(High density Plasma)/PSZ(perhydropolysilszane) 또는 PSZ/HDP의 더블 층(double layer)을 사용하거나 HDP/PSZ/HDP의 삼중 층(triple layer)을 사용한다. 또는 화학적기상증착법(CVD)으로 O3 TEOS(tetra ethyl ortho silicate glass)를 이용하여 형성할 수도 있다. 갭필 공정 후 CMP 공정을 통하여 ISO 마스크막 패턴(103a)이 드러나도록 연마한다. 습식 식각을 실시하여 ISO 마스크막 패턴(103a)을 리세스(recess) 한다. 전체 구조 상부에 플로팅 게이트용 폴리실리콘막(110)을 형성한다. 폴리실리콘막(110)은 약 1500 내지 3000Å의 두께로 형성하여 액티브 및 소자분리막을 완전히 덮도록 한다. CMP 공정을 수행하여 ISO 갭필막(109)이 드러나도록 연마한다. Referring to FIG. 7, after removing the second photoresist pattern 107, a wall oxide 108 is formed along the front surface. An ISO gap fill film 109 is formed to fill the trench. As the material for forming the ISO gap fill layer 109, a double layer of HDP (High density Plasma) / PSZ (perhydropolysilszane) or PSZ / HDP is used, or a triple layer of HDP / PSZ / HDP is used. . Alternatively, it may be formed using O 3 TEOS (tetra ethyl ortho silicate glass) by chemical vapor deposition (CVD). After the gap fill process, the ISO mask film pattern 103a is polished through the CMP process. The wet etching is performed to recess the ISO mask film pattern 103a. The floating silicon polysilicon layer 110 is formed on the entire structure. The polysilicon film 110 is formed to a thickness of about 1500 to 3000Å to completely cover the active and device isolation film. The CMP process is performed to polish the ISO gap fill film 109 to be exposed.

상기에서 설명한 본 발명의 기술적 사상은 바람직한 실시예에서 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술적 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같이 본 발명에 의하면 폴리실리콘 하드마스크막 대신에 ACL 하드 마스크막을 형성함으로써 감광막 형성 두께를 줄일 수 있으므로 마스크 패턴 마진이 증가되어 패턴 불량에 의한 일드 손실을 최소화할 수 있다. As described above, according to the present invention, since the photoresist film thickness can be reduced by forming an ACL hard mask film instead of the polysilicon hard mask film, the mask pattern margin is increased to minimize yield loss due to a poor pattern.

Claims (9)

반도체 기판 상부에 게이트 산화막, ISO 마스크막을 형성하는 단계;Forming a gate oxide film and an ISO mask film on the semiconductor substrate; 상기 ISO 마스크막 상부에 후속 마스크 마진을 증가시키도록 ACL 하드 마스크막을 형성하는 단계;Forming an ACL hard mask film over said ISO mask film to increase subsequent mask margin; 상기 ACL 하드 마스크막 상부에 낮은 두께의 SiON막을 형성하는 단계;Forming a low thickness SiON film on the ACL hard mask film; 상기 SiON막 상부에 제 1 감광막 패턴을 형성한 후, 상기 제 1 감광막 패턴에 따라 식각하여 SiON막 패턴 및 ACL 하드 마스크막 패턴을 형성하는 단계;Forming a first photoresist pattern on the SiON layer and then etching the first photoresist pattern to form a SiON layer pattern and an ACL hard mask layer pattern; 상기 SiON막 패턴에 따라 식각하여 ISO 마스크막 패턴 및 게이트 산화막 패턴을 형성하는 단계;Etching according to the SiON layer pattern to form an ISO mask layer pattern and a gate oxide layer pattern; 상기 ACL 하드 마스크막 패턴에 따라 상기 반도체 기판을 식각하여 셀 영역의 트랜치를 형성하는 단계;Etching the semiconductor substrate according to the ACL hard mask layer pattern to form a trench in a cell region; 상기 ISO 마스크막 패턴 상부에 제 2 감광막 패턴을 형성한 후, 상기 제 2 감광막 패턴에 따라 식각하여 주변 영역의 상기 ISO 마스크막 패턴, 게이트 산화막 패턴 및 트랜치를 형성하는 단계; 및Forming a second photoresist pattern on the ISO mask layer pattern, and etching the second photoresist pattern to form the ISO mask layer pattern, a gate oxide layer pattern, and a trench in a peripheral region; And 상기 트랜치에 갭필하는 단계를 포함하는 반도체 소자의 트랜치 형성 방법.Forming a trench in the trench; and forming a gap fill in the trench. 제 1 항에 있어서,The method of claim 1, 상기 ISO 마스크막은 질화막을 사용하고 두께는 1000 내지 2500Å가 되도록 형성하는 반도체 소자의 트랜치 형성 방법.The method of forming a trench in a semiconductor device, the ISO mask film is formed using a nitride film and the thickness is 1000 to 2500 내지. 제 1 항에 있어서,The method of claim 1, 상기 ACL 하드 마스크막은 비정질 카본막으로써 1500Å 내지 2500Å의 두께로 형성하는 반도체 소자의 트랜치 형성 방법.The ACL hard mask film is an amorphous carbon film, the trench forming method of a semiconductor device to form a thickness of 1500Å to 2500Å. 제 1 항에 있어서,The method of claim 1, 상기 ACL 하드 마스크막은 250℃의 온도에서 형성하는 반도체 소자의 트랜치 형성 방법.And forming the ACL hard mask film at a temperature of 250 ° C. 제 1 항에 있어서,The method of claim 1, 상기 ACL 하드 마스크막은 500℃ 내지 600℃의 온도에서 형성하는 반도체 소자의 트랜치 형성 방법.The ACL hard mask film is a trench forming method of a semiconductor device formed at a temperature of 500 ℃ to 600 ℃. 제 1 항에 있어서,The method of claim 1, 상기 제 1 감광막 패턴은 셀 영역에 게이트 패턴이 형성되어 있고, 주변 영역은 차폐되어 있는 반도체 소자의 트랜치 형성 방법.The first photoresist pattern has a gate pattern is formed in the cell region, the peripheral region is a trench forming method of the semiconductor device is shielded. 제 1 항에 있어서,The method of claim 1, 상기 제 2 감광막 패턴은 주변 영역에 게이트 패턴이 형성되어 있고, 셀 영역은 차폐되어 있는 반도체 소자의 트랜치 형성 방법.The second photoresist pattern has a gate pattern formed in the peripheral region, the cell region is a trench forming method of the semiconductor device is shielded. 제 1 항에 있어서,The method of claim 1, 상기 갭필은 HDP/PSZ, PSZ/HDP의 더블 층, HDP/PSZ/HDP의 삼중 층 및 O3 TEOS 중 어느 하나로 형성할 수 있는 반도체 소자의 트랜치 형성 방법.The gap fill is a trench forming method of a semiconductor device which can be formed of any one of a double layer of HDP / PSZ, PSZ / HDP, a triple layer of HDP / PSZ / HDP, and O 3 TEOS. 제 8 항에 있어서,The method of claim 8, 상기 O3 TEOS는 화학적기상증착법으로 형성할 수 있는 반도체 소자의 트랜치 형성 방법.The O 3 TEOS is a trench formation method of a semiconductor device that can be formed by chemical vapor deposition.
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