KR100753125B1 - Method for manufacturing saddle type fin transistor - Google Patents

Abstract

The present invention is to provide a saddle-type fin transistor that can improve the characteristics of the device by preventing both ends of the long axis of the gate and the neighboring active region overlap each other. In the saddle-type fin transistor manufacturing method of forming a saddle-type fin by performing a pin etching process using a pin mask formed to be orthogonal to the direction, the pin mask and both ends adjacent to the long axis direction in the etching process during the pin etching process A method of manufacturing a saddle-type fin transistor using a first dummy mask overlapping one side of two active regions and overlapping in a direction orthogonal to the fin mask is provided.

Pin Transistor, Recess Transistor, Saddle Pin Transistor

Description

Saddle-type pin transistor manufacturing method {METHOD FOR MANUFACTURING SADDLE TYPE FIN TRANSISTOR}

1 is a cross-sectional view showing a general fin transistor.

2 is a cross-sectional view of a typical recess transistor.

3 is a cross-sectional view showing typical transistors.

4 is a plan view illustrating a saddle-type fin transistor according to the prior art.

5 is an enlarged perspective view illustrating a portion 'A' shown in FIG. 4.

FIG. 6 is a cross-sectional view taken along the line II ′ and II-II ′ of FIG. 5.

7A to 7E are perspective views illustrating a method of manufacturing the saddle-type fin transistor shown in FIG. 5.

FIG. 8 is an enlarged SEM photograph of the portion 'B' shown in FIG. 4. FIG.

9 is a plan view illustrating a saddle-type fin transistor according to an embodiment of the present invention.

10 is a cross-sectional view illustrating a technical principle according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view schematically illustrating a region in which the first dummy mask DM1 illustrated in FIG. 9 is overlapped.

FIG. 12 is a perspective view illustrating a saddle fin structure formed through the second dummy mask DM2 shown in FIG. 9.

13 is a plan view illustrating a saddle-type fin transistor according to another embodiment of the present invention.

14 is a plan view illustrating a saddle-type fin transistor according to another embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

10, 110: substrate

11: device separator

12, FM: pin mask

14: saddle pin

15: gate oxide film

16: polysilicon film

17: conductive film

DM1: first dummy mask

DM2: second dummy mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a saddle type transistor in which a fin type and a recessed type are mixed.

In general, a transistor having a horizontal channel widely applied to a transistor has various limitations as the design rule is reduced, thereby limiting the size of the transistor. The biggest problems of the reduced horizontal channel transistors include short channel effects and drain induced barrier lower (DIBL) effects caused by shorter channel lengths. In conventional transistors, when the channel length is reduced to 50 nm or less, the dispersion of device characteristics is increased by process variables, and when the channel length is 30 nm or less, the short channel effect and the DIBL effect become severe and it is known that the transistor is difficult to operate normally.

In order to overcome the problems of horizontal channel transistors, double gate transistors have been proposed. The double gate transistor has a channel having a thickness of 30 nm or less, and a structure surrounding the channel or having gates disposed on both sides of the channel.

In the above-described horizontal channel transistor, since the gate electrode is formed only on the upper portion of the horizontal channel, an electric field is vertically asymmetrically applied to the channel, and thus there is a lot of difficulty in effectively controlling the on / off operation of the transistor by the gate electrode. As a result, the smaller the channel size, the greater the influence of the short channel effect. In contrast, in the double gate transistor having the vertical channel, since gate electrodes are formed on both sides of the thin channel, all regions of the channel are affected by the gate electrode. Therefore, since the charge flow between the source and the drain can be suppressed when the transistor is off, power consumption can be reduced, and the on / off operation of the transistor can be effectively controlled.

One of the transistors having a vertical channel is a fin transistor. A typical pin transistor is shown in FIG. As shown in FIG. 1, the fin transistor has a structure in which an upper portion of the substrate between the device isolation layers 3 is formed in the form of a fin 2, and both sides of the fin 2 function as a channel. The short channel effect problem can be solved by increasing the channel area. However, this structure can reduce the body effect, but there is a limit to increasing the effective channel length. On the other hand, another of the transistors having the vertical channel is a recessed (or trench type) transistor shown in FIG. Unlike a fin transistor, a recessed transistor has a transistor structure in which a threshold voltage is determined regardless of a gate length. However, the threshold voltage is lowered or the short channel effect cannot be solved freely as a recessed transistor.

As shown in FIG. 3, the structure in which the fin transistor and the recess transistor are mixed is a saddle-type fin transistor. The saddle-type pin transistor is a structure that can solve the problem of the pin transistor, the low threshold voltage and the short effective channel length in parallel with the recess transistor. Accordingly, it is advantageous to apply a saddle-type pin transistor rather than a pin transistor in a dynamic random access memory (DRAM) device in consideration of operating characteristics of the device.

Hereinafter, the structure and manufacturing method of the saddle-type fin transistor according to the prior art will be described.

4 is a plan view illustrating a structure of a saddle-type fin transistor according to the prior art, FIG. 5 is an enlarged perspective view of a portion 'A' shown in FIG. 4, and FIGS. b) is a cross-sectional perspective view, taken along the line II ′ and II-II ′, respectively, shown in FIG. 5. 7A to 7E are process perspective views for explaining the manufacturing method.

4 to 6 and 7A, an isolation layer 11 is formed in the substrate 10 by performing a shallow trench isolation (STI) process. At this time, the STI process is performed in the following manner. First, a pad oxide film and a pad nitride film (not shown) are sequentially stacked on the substrate 10 (the oxidation process and the deposition process are performed), and then an etching process using an STI mask is performed to form trenches in the substrate 10. Form. Thereafter, an HDP (High Density Plasma) oxide film is deposited as a single layer to fill the trench, and then a CMP (Chemical Mechanical Polishing) process is performed to form an isolation device 11 in the trench.

Subsequently, a photomask is performed to form a fin mask 12 having the same shape as that of the gate illustrated in FIG. 5 on the substrate 10. In this case, the photo process includes a photoresist coating process, an exposure process using a photo mask, and a developing process.

Subsequently, as shown in FIGS. 4 to 6 and 7B, an etching process using the fin mask 12 is performed to form the saddle-shaped fin 14. In this case, the etching process is performed under the condition that the etching selectivity between the silicon substrate 10 and the device isolation layer 11 is as high as possible to etch the device isolation layer 11 and then etch the silicon substrate 10 or first the silicon substrate 10. ) And the device isolation layer 11 is etched.

Then, as shown in FIGS. 4-6 and 7C, the pin mask 12 is removed.

Subsequently, as shown in FIGS. 4 to 6 and 7D, the gate oxide film 15 is formed on the exposed surface of the substrate 10 by performing a gate oxidation process.

Next, as shown in FIGS. 4 to 6 and 7E, the polysilicon film 16 and the conductive film 17 functioning as gates are sequentially deposited so that the fins 14 are embedded.

Subsequently, an etching process using a gate mask for forming a gate is performed to form a gate having a profile as shown in FIGS. 5 and 6.

However, in the saddle-type fin transistor manufacturing method according to the related art described above, there are regions in which the fin mask 112 is shorted to both ends of the long axis of the adjacent active region (see 'B' in FIG. 4). As a result, as shown in FIG. 8, the active region and the neighboring gates overlap to increase the capacitance of the word line, while the coupling ratio between the word line and the storage node is increased. coupling ratio) increases. In addition, the overlapping area between neighboring gates and the active region is increased, thereby increasing the gate induced drain leakage (GIDL) current, thereby deteriorating device characteristics.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and provides a saddle-type fin transistor which can improve the characteristics of the device by preventing both ends of the long axis of the gate and the neighboring active region from overlapping each other. The purpose is.

According to an aspect of the present invention, there is provided a saddle-type fin transistor manufacturing method of forming a saddle fin by performing a pin etching process using a fin mask formed to orthogonal to an active region in a long axis direction in a vertical direction. The first dummy mask formed as an etch mask during the fin etching process, the pin mask and a first dummy mask formed to overlap one side of two active regions adjacent to each other in a long axis direction and overlap in a direction orthogonal to the pin mask. A method of manufacturing a saddle-type pin transistor is provided.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

9 is a plan view illustrating a method of manufacturing a saddle-type fin transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 9, a method of manufacturing a saddle-type fin transistor according to an exemplary embodiment of the present invention includes two multi masks, first and second dummy masks DM1, in addition to the fin mask FM. A pin etching process is performed using DM2) to form a saddle pin.

The first dummy mask DM1 is formed on the fin mask FM so that both ends thereof overlap one end of two neighboring active regions in a long axis direction (a direction perpendicular to the gate).

The second dummy mask DM2 is formed in a region where the fin mask FM and the active region overlap.

The first and second dummy masks DM1 and DM2 may be simultaneously formed or not simultaneously formed through a photo process. If formed at the same time as follows. First, a photosensitive film is coated on the fin mask FM, and then formed by performing an exposure and development process using a photo mask.

Hereinafter, operations of the first and second dummy masks DM1 and DM2 will be described with reference to FIG. 10.

As shown in FIG. 10, a hard mask 111, an antireflection film 112, and a fin mask FM are sequentially formed on the silicon substrate 110, and a second dummy is formed on a portion of the fin mask FM. The mask DM2 is formed. That is, a photosensitive film having a thickness twice that of the region where only the fin mask FM is formed is coated on the region where the second dummy mask DM2 is formed.

In this state, when the etching process 114 is performed, the silicon substrate 110 is etched to have a profile 120 corresponding to the difference in thickness of the photoresist film. Specifically, an area (hereinafter referred to as a first region) that is not covered by any mask is etched most deeply, and an area where only the fin mask FM is covered (hereinafter referred to as a second region) is less than the first region. Less deeply etched, the region (hereinafter referred to as a third region) in which the fin mask FM and the second dummy mask DM2 are covered with the stacked structure is etched less deeply than the second region. That is, the depth is 'first area> second area> third area' and a profile having a stepped structure is formed.

That is, as shown in FIG. 11, both ends of the active region are etched to have a stepped shape by using the first dummy mask DM1. This minimizes the etch rate at both ends of the active region in the long axis direction overlapping the gate to prevent overlapping of the active region and neighboring gates, thereby increasing the capacitance of the word line, while providing a couple between the word line and the storage node. It is possible to prevent the ring ratio from increasing. In addition, the GIDL current increases as the overlapping area between the neighboring gate and the active region increases.

In addition, as shown in FIG. 12, when the second dummy mask DM2 is used, the protrusion 121 may be formed on the fin, thereby increasing the length of the channel than the conventional fin gate structure.

13 and 14 are embodiments in which only the shape of the second dummy mask DM2 is changed in FIG. 9. 13 and 14 may secure a larger channel length than the second dummy mask DM2 shown in FIG. 9.

In FIG. 10, '110' indicates a substrate, '111' indicates a hard mask, '111a' indicates an amorphous carbon film, '111b' indicates a SiON film, and '112' indicates an antireflection film (BARC).

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the gate line adjacent to the active region is overlapped by minimizing an etch rate at both ends of the active region in the long axis direction overlapping the gate using the first dummy mask DM1. Can increase the capacitance. In addition, the coupling ratio between the word line and the storage node may be prevented from increasing. In addition, the GIDL current increases as the overlapping area between the neighboring gate and the active region increases.

In addition, according to the present invention, when the second dummy mask DM2 is used, the protrusion 121 may be formed on the fin, thereby increasing the length of the channel than the conventional fin gate structure.

Claims (4)

In the saddle-type fin transistor manufacturing method of forming a saddle-type fin by performing a pin etching process using a pin mask formed to orthogonal to the active region in the long axis direction in the vertical direction, A saddle type using the first dummy mask formed as an etch mask during the fin etching process, the pin mask and a first dummy mask formed to overlap one side of two active regions adjacent to each other in a long axis direction and overlapping in a direction orthogonal to the pin mask. Pin transistor manufacturing method. The method of claim 1, And using a second dummy mask formed in an area where the fin mask and the active region overlap with each other as an etching mask during the fin etching process. The method of claim 2, A saddle-type fin transistor manufacturing method in which a hard mask is further formed below the fin mask. The method of claim 3, wherein The hard mask is a saddle-type fin transistor manufacturing method comprising amorphous carbon.

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