DE4336869C2 - Method of manufacturing a MOS transistor - Google Patents

Description

The invention relates to a method for producing a Semiconductor device, more specifically a method of manufacture len of an LDD-MOS transistor, with which it is possible to Increase integration density and combine process steps fold.

Successes in the field of electronics have led that information-storing semiconductor chips of high quality, with multiple functions and large storage capacity must be available. These goals are technically assisted of semiconductor chip integration technology. In the In recent years, this technology has been improving performed in the manufacture of semiconductor chips.

To semiconductor devices of general kind with high integra dense density, it is necessary to dimension to reduce the individual functional elements. Furthermore, it is required the width and area of an insulating  area for mutual isolation of neighboring functions reduce elements, d. H. a field area.

Because the cell size depends on the extent of such a reduction it is no exaggeration to say that the Functional element insulation technology is one of the most important factors ren is the size of a semiconductor memory cell Right. Insulation technology is the technology used in manufacturing len integrated components, through the individual functional elements structurally and electrically separated from each other be, which ensures that individual functional parts independently of one another without any interaction of neighboring Functional parts work.

Various isolation techniques have been proposed so far. The diversity stems from different isolation conditions forth as required for different types of ICs are like for NMOS, PMOS and bipolar semiconductor devices te. In other words, different isolation techniques have been used depending on the purpose of each component.

As an isolation technique, an isolation technique for a p ⁺ / n junction is known, as is used in bipolar semiconductor components, and a technique with local oxidation of silicon (LOCOS = Local Oxidation of Silicon), an isolation technique as used in MOS Components is used. So far, the LOCOS technology has been used continuously, whereby it was known that there are no difficulties in producing 1M DRAMs with a minimum line width of 1 μm. However, when manufacturing 4M DRAMs with a minimum line width of 0.8 µm, there is a limit to the use of LOCOS technology.

Figs. 2A to 2H are sectional views for illustrating a manufacturing method for an n-MOS transistor using a conventional LOCOS technique. This process is carried out in the following order of steps: an isolation step using LOCOS technology, a gate formation step, a source / drain region forming step, and an electrode formation step as described below in connection with the above Fig. 2A is described to 2H.

In the known method, a p-well is first formed, as shown in Fig. 2A. In this step, boron ions are implanted in a substrate 11 to produce a p-well 12 .

Fig. 2B illustrates a step of forming field oxide films Ka nalstoppbereichen and using the well known LOCOS insulation. Boron ions are implanted in selected sections of the p-well 12 in order to produce channel stop regions 13 . Thereafter, field oxidation is performed to produce field oxide films 14 that are configured to separate adjacent functional elements from each other. In Fig. 2B, reference numeral 15 denotes an active area, and reference numeral 16 denotes field areas.

Thereafter, a gate oxide film 17 is formed over the active region 15 , as shown in FIG. 2C.

Then, a polysilicon film is deposited on the gate oxide film 17 , which is patterned to form a gate 18 , as shown in Fig. 2D. Using the gate 18 as a mask, phosphorus ions are implanted in the active region 15 to form n-diffusion regions 19 of low concentration.

Then, an oxide film is deposited over the entire surface of the resulting structure by CVD and then anisotropically etched to form gate sidewalls 20 as shown in FIG. 2E. Using the gate sides walls 20 as a mask, arsenic (As) ions are implanted into the diffusion areas 19 , thereby forming n-diffusion areas 21 of high concentration. The diffusion regions 19 of low concentration and the diffusion regions 21 of high concentration serve as the source / drain region of an LDD structure.

As shown in FIG. 2F, an oxide film 23 is deposited as an insulating film over the entire surface of the resulting structure.

Thereafter, the oxide film 23 is partially etched to form contact holes 24 in the source / drain region 22 , as shown in FIG. 2G.

A metal layer is then formed over the entire surface of the resulting structure. The metal layer is patterned to produce conductive layers 25 for electrodes as shown in FIG. 2H. A MOS transistor with an n-LDD structure is thus produced.

In the conventional method described above, isolation between adjacent functional elements is achieved using the well known LOCOS technique as illustrated by Fig. 2B.

Figs. 3A to 3D are cross-sections which illustrate veran a process for forming the field oxide film 14 for Funktionselementisolie propagation using the LOCOS technique shown in FIG. 2B. This process will now be described in connection with the aforementioned FIGS. 3A to 3D.

In this process, a cushion oxide film 31 , which serves as a voltage reduction layer in a subsequent field oxidation process step, and a CVD nitride film 32 , which is used in the subsequent field oxidation process step as an oxidation mask, are first placed over the silicon substrate 11 with the p-well 12 serves, deposited as shown in Fig. 3A.

The nitride film 32 is then coated with a photoresist film 33 , as shown in FIG. 3B. The photo resist film 33 is patterned to define the active area 15 and the field areas 16 . In this case, a region in which the photoresist film 33 remains becomes the active region 15 . Subsequently, the film 32 serving as an oxidation mask is etched under the condition that the photoresist film 33 is used as a mask in such a way that its parts lying above the field regions 16 are removed. Boron ions are then implanted in the substrate 11 to form channel stop regions 14 in the respective field regions 16 .

Thereafter, the remaining photoresist film 33 is removed as shown in Fig. 3C. An oxidation step is then carried out in order to form field oxide films 14 in respective field regions 16 .

Then, as shown in Fig. 3D, the CVD nitride film 32 and the cushion oxide film 31 are successively removed.

However, in the above process using the conventional LOCOS technique, a so-called bird beak phenomenon occurs, according to which the field oxide films 14 pass over to the active region 15 in the field oxidation step. Because of this bird's beak phenomenon, the area of the functional element isolation area becomes larger than that of the design, which leads to a limitation of what can be planned. As a result, this process is not suitable for manufacturing highly integrated semiconductor devices with a design specification for line widths not exceeding 1 µm.

To overcome this difficulty, new isolators were created techniques designed on components with integrations dimensions in the submicrometer range can be applied. For example, improved insulation technology and a Gra insulation technology proposed. However, the trench iso ing technology, in which a silicon substrate for formation a trench is etched, which is opened with an insulating film is because of their technical difficulties with the Manufacture of highly integrated semiconductor components in the Practice rarely used. On the other hand, the improved LOCOS insulation technology for the purpose of minimizing the bird thus developed beak phenomenon in field oxidation the oxide film less laterally across the active area attacks. A typical example of such an improved LOCOS insulation technology is one with a polysilicon pole steric layer as described by Nishihara, T., et al .: A 0.5 µm Isolation Technology Using Advanced Poly Silicon Pad LOCOS (APPL), in IEDM 1988, pp. 100-103.

FIGS. 4A to 4D are cross-sectional views illustrating a process of fabricating a n-LDD MOS transistor using such an improved LOCOS technique with polysilicon cushion layer. Here, FIGS. 4A to 4F process steps for forming a field oxide film on a silicon substrate.

According to this process, p-type impurity ions are implanted in a silicon substrate 61 so that a p-well 62 is formed. Then, a cushion oxide film 63 is grown on the silicon substrate 61 for stress relief as shown in FIG. 4A. A polysilicon film 64 and a nitride film 65 are successively formed over the cushion oxide film 63 using a low pressure CVD (LPCVD) process. The cushion oxide film 63 serves to limit crystal defects which occur in the nitride film 65 during a subsequent field oxide production step. The polysilicon film 64 serves as a voltage buffer for buffering voltages as they occur in the field oxide production step, whereas the nitride film 65 serves as an oxidation mask in the field oxide production step.

Thereafter, the nitride film 65 is coated with a photoresist film 66 as shown in Fig. 4B. The photoresist film 66 is patterned to define an active area 67 and field areas 68 .

Then, the nitride film 65 is partially etched away using the patterned photoresist film 66 as a mask, so that its portions over the respective field areas 68 are removed as shown in FIG. 4C. By removing these parts of the nitride film, the polysilicon film 64 is partially exposed in its parts that correspond to the removed parts of the nitride film.

As shown in FIG. 4D, 64 foreign matter ions are then implanted in the exposed parts of the polysilicon film lying over the respective field areas 68 in order to form channel stop areas.

A field oxidation step is then performed to produce field oxide films 69 and channel stop regions 70 as shown in FIG. 4E.

Following the production of the field oxide films 69 , the nitride film 65 , the polysilicon film 64 and the cushion oxide film 63 are successively removed, as illustrated by FIG. 4F. Here, the nitride film 65 is removed using a wet etching process, while the polysilicon film 64 is removed using a dry etching process. When removing the polysilicon film 65 , an exact etching time must be observed in order to avoid etching damage to the silicon substrate 61 . However, this interferes with even removal of the polysilicon film 64 . For this purpose, after the polysilicon film 65 has been removed, an oxidation layer is produced, which is sacrificed. The cushion oxide film 63 is removed by HF.

After the nitride film 65 , the polysilicon film 64 and the cushion oxide film 63 are removed following the field oxidation, a gate oxide film 71 is grown on the active region 67 as shown in FIG. 4G.

Then, a polysilicon film 72 is deposited on the entire surface of the resulting structure, as illustrated by FIG. 4H.

The polysilicon film 72 is coated with a photoresist film 73 which is then patterned as shown in FIG. 4I.

Using the patterned photoresist film 73 as a mask, the polysilicon film 72 is partially etched to form a gate 74 as shown in Fig. 4J.

Thereafter, phosphorus ions are implanted into the substrate 61 using the gate 74 as a mask to form low concentration diffusion regions 75 as illustrated by FIG. 4K.

An oxide film 76 is then deposited over the entire surface of the resulting structure, as shown in FIG. 4L.

The oxide film 76 is anisotropically etched to form gate sidewalls 77 as shown in FIG. 4M.

Thereafter, arsenic ions are implanted into the substrate 61 to form high concentration diffusion regions 78 , as illustrated by FIG. 4N. As a result, a source / drain region 72 with an LDD structure with the diffusion regions 75 of low concentration and the diffusion regions 77 of high concentration is obtained.

Then, an insulating film 80 is deposited over the entire surface of the resulting structure, as shown in FIG. 40.

Subsequently, steps for forming contact holes, a gate electrode 81 over the gate 74 and a source / drain electrode 82 on the source / drain region 79 are carried out, as illustrated by FIG. 4P.

Thus, an n-LDD MOS transistor according to an improved LOCOS insulation technology manufactured.

The extent of the bird's beak phenomenon that occurs when manufacturing a MOS transistor using LOCOS isolation technology depends on various LOCOS process parameters as follows:

• 1. increase with smaller thickness of the cushion oxide film;
• 2. Decrease with greater thickness of the nitride film or greater Thickness ratio of nitride film to cushion oxide film;
• 3. decrease in the thickness of the field oxide film;
• 4. decrease with higher temperature during field oxidation;

and

• 1. Increase with higher pressure during field oxidation.

In view of this, in the improved LOCOS technology, as illustrated by FIGS . 4A to 4P, the polysilicon film 64 is formed between the nitride film 65 and the cushion oxide film 63 . Due to the polysilicon film 64 , the cushion oxide film 63 for stress relief, which limits the occurrence of crystal defects, can have a reduced thickness. As a result, lateral oxidation by the cushion oxide film 63 can be reduced, which makes it possible to reduce the bird's beak phenomenon. In other words, the polysilicon film 64 sorbs voltages such as occur between the nitride film 65 and the substrate 61 during a heating cycle. Accordingly, the stress relieving cushion oxide film 63 may have a reduced thickness. As mentioned, this has the consequence that the extent of the bird's beak phenomenon can be reduced.

However, the improved LOCOS isolation process involves the addition of new process steps resulting from the formation of polysilicon film 63 between cushion oxide film 62 and nitride film 64 . In addition, if a MOS transistor is to be manufactured using the above-mentioned improved LOCOS process, steps for depositing and removing a polysilicon film for contact area are required. As a result, the total number of process steps increases, which increases the manufacturing cost of the product ultimately obtained.

According to Murphy's exploitation rule, the yield can be represented by the following equation:

where Y is the yield, D the defect density, Ac the effective Area and f (D) represent a defect density distribution function  sentieren.

According to Murphy's exploitation rule, the defect density increases when the Number of process steps increases. Such an increase in defect density leads to reduced yield.

A method for producing a MOS transistor is already known from JP 63-293850 A, which has the following steps:

• Forming a first insulating film on a silicon substrate,
• Deposition of a polysilicon film doped with foreign substances from the two th conduction type on the first insulating film,
• - Deposition of a second insulating film on the polysi doped with foreign substances liziumfilm,
• - sequential patterning of the second insulating film and the polysili ziumfilm to define an active area and field areas,
• - Deposit a third insulating film on the entire surface of the resulting structure and etching back of the insulating film, by pages walls on the side surfaces of the polysilicon film, and
• - Perform a field oxidation to produce field oxide films in the Field areas.

EP 0 520 703 A1 describes a method for producing field oxide preparation Chen known using a poly-buffered LOCOS process.

EP 0 547 908 A2 describes a further method for producing Field oxide areas using an improved poly-buffered LOCOS process.

The invention has for its object a method for producing a Specify MOS transistor through which the yield and the integration can be increased densely.

This object is achieved by the method according to claim 1. advantageous Further developments and refinements of the invention are in the Unteran sayings described.

With the inventive method, the same number of process steps, as when using a conventional LOCOS process  ses, the bird's beak phenomenon can be avoided, creating structure widths of 0.4 µm can be achieved.

In the method according to the invention, when producing a field oxide film LOCOS insulation technology using a polysilicon film. A stress-relieving cushion oxide film and a tension are created gene abpuffenden polysilicon film, as in the production of the field oxide films are used as a gate oxide film or as a gate. Accordingly, no separate manufacturing steps for the field oxide film, the gateiso lier film and the gate executed.

The invention is illustrated below with reference to the drawing Embodiments explained in more detail.

Fig. 1A to 1N are sectional views illustrating a procedural proceedings of fabricating a n-LDD MOS transistor according to an exporting approximately example of the invention;

Figs. 2A to 2H are sectional views for illustrating a method of manufacturing a MOS transistor according to the prior art;

Figs. 3A to 3D are cross sections for illustrating a method for fabricating an isolation region in a semiconductor device using a known LOCOS technique; and

FIGS. 4A to 4D are cross sections illustrating a method of fabricating a MOS transistor of a known application, improved LOCOS technique Ver.

In the method of the present invention, a p-well 92 is formed in a silicon substrate 91 , which is then thermally oxidized to thereby produce a thin oxide film 93 with a thickness of approximately 6 to 10 nm (60-100 Å), as shown in Fig. 1A , The oxide film 93 serves as a Pol-oxide film for voltage reduction in a subsequent field oxidation step, and it also serves as a gate oxide film. Thereafter, a polysilicon film 34 having a thickness of approximately 200 to 300 nm is deposited on the oxide film 93 . It consists of a phosphorus-doped polysilicon film and is manufactured using an LPCVD process. The polysilicon film is doped with phosphorus ions by an in-situ doping process in which phosphorus ions are doped into the polysilicon film during the deposition. The polysilicon film 94 serves as a layer for buffering voltages in the field oxidation step, and also serves as a gate. A nitride film 95 with a thickness of approximately 50 to approximately 100 nm is deposited over the polysilicon film 94 using an LPCVD process, which serves as a mask layer in the subsequent field oxidation step.

The nitride film 95 is coated with a photoresist film 96 , which in turn is photo-etched to define an active region 97 and field regions 98 , as shown in FIG. 1B. In this case, an area in which the photoresist film 96 remains is set as the active area 97 , while areas corresponding to distant portions of the photoresist film 96 are field areas 98 .

Then, using the photoresist film 96 as a mask, the nitride film 95 and the polysilicon film 94 are patterned as shown in Fig. 1C. Then the photoresist film 96 is completely removed.

To protect the side surfaces of the patterned polysilicon film 94 , another nitride film 99 is deposited on the entire surface of the resulting structure, as shown in FIG. 1D.

Thereafter, the nitride film 99 is etched back to form side walls 100 of the polysilicon film 94 as shown in FIG. 1E. The nitride film side walls 100 serve in the subsequent field oxidation step together with the nitride film 95 as an oxidation mask. The polysilicon film 94 is covered by the nitride films 95 and 100 , so that it is subsequently protected in the field oxidation step.

This is followed by field oxidation at a temperature between 600 and 1000 ° C. in order to form field oxide films 101 with a thickness of approximately 450 to 600 nm in the field regions 98 for isolation, as illustrated by FIG. 1F. The field oxidation step for producing the field oxide films 101 is carried out by oxidation under high pressure, whereby a high growth rate of the oxidation layer can be aimed at when a temperature of 600 to 900 ° C is used. At a temperature of 900 to 1000 ° C, the field oxidation step is carried out in a H ₂ / O ₂ atmosphere at atmospheric pressure in a pyro-oxidation manner.

After the field oxidation, the nitride film 95 and the side walls 100 , which served as an oxidation mask, are removed by immersion in hot phosphoric acid (H ₃ PO ₄ ) solution of 80 ° C, as illustrated by FIG. 1G. Subsequently, the entire surface of the resulting structure is coated with a photoresist film 102 , and this is subjected to a pattern formation process.

Using the photoresist film 102 as a mask, the polysilicon film 94 , which served as a voltage buffering layer in the field oxidation step, is partially etched away to form a gate 103 , as shown in FIG. 1H.

Then, phosphorus ions are implanted into the substrate 91 using the gate 103 as a mask, as shown in FIG. 1I.

As shown in Fig. 1J, the device with the in the planted impurity ions is subsequently annealed to form n-diffusion regions 104 with a low concentration in the substrate 91 .

Then, an oxide film 105 is deposited on the entire surface of the resulting structure using an LPCVD process. This oxide film 105 is anisotropically etched to form gate sidewalls 106 , as shown in FIG. 1K.

Then arsenic ions are implanted into the substrate 91 , as illustrated by FIG. 1L.

As shown by FIG. 1M, the device with the implanted impurity ions is annealed to form n-type diffusion regions 107 of high concentration in the substrate 91 . Thereafter, an interlayer insulating film 109 is deposited on the entire surface of the resulting structure. The insulating film 109 is photo-etched to form contact holes 110 and 111 for a source / drain electrode and a gate.

Then, a metal film is deposited on the entire surface of the resulting structure, and this is patterned so that a source / drain electrode 112 and a gate electrode 113 are formed in the contact holes 110 and 111, respectively, as shown in Fig. 1N , An n-LDD-MOS transistor is thus obtained in a manner according to the invention.

The n-LDD-MOS transistor has a source / drain region 108 with an LDD structure with diffusion regions 104 of low concentration and diffusion regions 107 of high concentration. In the ion implantation to form the source / drain region 108 , phosphor ions with a dose of 2.0-3.0 × 10 ¹³ ions / cm ² and an energy of 20-40 keV are implanted in the diffusion region 104 of low concentration, and Arsenic ions are implanted in the high concentration diffusion region 107 with a dose of 2.0-5.0 × 10 ¹⁵ ions / cm ² and an energy of 20-40 keV. The annealing step for producing the source / drain region 108 is carried out in an H ₂ / O ₂ atmosphere at a temperature of 700 to 900 ° C.

The interlayer insulating film 109 is two-layered, with a first layer made of an undoped oxide film produced by an LPCVD process and a second layer made of a BPSG film produced by a CVD process.

According to the invention, insulation of functional elements is under Use of an improved LOCOS process instead of well-known LOCOS process achieved only for semi-lead Subcomponents with structural dimensions of approximately 1.0 µm  is usable. Manufacturing steps for insulation areas, the The gate oxide film and the gate do not become independent of each other the, but executed in connection with each other. Accordingly, it is possible to simplify the process steps and the total number of steps from that to he low, as required for improved LOCOS processes is such.

As a result, functional element isolation can be used an improved LOCOS process can be achieved without that the number of process steps is increased. This enables light it, 64M DRAMs with structure dimensions of 0.4 µm to deliver. This leads to the advantages of high integration dense and mass producibility.

Since diesel in the improved LOCOS process according to the invention be number of process steps is used as in the forth conventional LOCOS process it is possible to increase costs due to an increased number of process steps as well a reduction in yield according to the yield rule of Avoid Murphy as they otherwise would when producing high Integrated semiconductor devices occur.

Claims (17)

1. A method of manufacturing a MOS transistor by the following steps:

• - Forming a trough ( 92 ) of the first conductivity type in a silicon substrate ( 91 );
• - Forming a first insulating film ( 93 ) on the silicon substrate ( 91 );
• - depositing a polysilicon film ( 94 ) of second conductivity type doped with foreign substances on the first insulating film ( 93 );
• - depositing a second insulating film ( 95 ) on the polysilicon film ( 94 );
• - sequentially patterning the second insulating film ( 95 ) and the polysilicon film ( 94 ) to define an active region ( 97 ) and field regions ( 98 );
• - depositing a third insulating film ( 99 ) on the entire surface of the resulting structure and etching back the third insulating film ( 99 ) to form side walls ( 100 ) on side surfaces of the polysilicon film ( 94 );
• - performing a field oxidation to produce field oxide films ( 101 ) in the field areas;
• - removing the second insulating film ( 95 ) and the side walls ( 100 ) on the polysilicon film ( 94 );
• - patterning the polysilicon film ( 94 ) to form a gate electrode ( 103 );
• - implanting impurity ions of the second conductivity type into the silicon substrate ( 91 ) and annealing the structure in order to produce a source region ( 104 ) and a drain region ( 104 ) of low impurity ion concentration;
• - depositing a fourth insulating film ( 105 ) on the entire surface of the resulting structure, and anisotropically etching the same to form the side walls ( 106 ) of the gate electrode ( 103 );
• - implanting impurity ions of the second conductivity type into the silicon substrate ( 91 ) and annealing the component to form a source region ( 107 ) and a drain region ( 107 ) of high impurity ion concentration;
• - depositing an interlayer insulating film ( 109 ) on the entire surface of the resulting structure;
• - Partial etching of the interlayer insulating film ( 109 ) to form contact holes ( 110 , 111 ) in the source region ( 107 ) and in the drain region ( 107 ) of high impurity ion concentration and on the gate electrode ( 103 ); and
• - Coating the entire surface of the resulting structure with a metal film and patterns of the metal film to form a source connection ( 112 ), a drain connection ( 112 ) and a gate electrode connection ( 113 ) in the contact holes ( 110 , 111 ).

2. The method according to claim 1, characterized in that a thin oxide film is used as the first insulating film ( 93 ). 3. The method according to claim 2, characterized in that the first insulating film ( 93 ) is formed by oxidizing the silicon substrate ( 91 ) in a thermal manner with a thickness of approximately 6 to 10 nm. 4. The method according to claim 3, characterized in that the polysilicon film ( 94 ) with a thickness of approximately 200 to approximately 300 nm is produced. 5. The method according to any one of claims 3 or 4, characterized in that the polysilicon film ( 94 ) is produced in that phosphor ions are doped into a polysilicon film which is deposited using a low-pressure CVD process. 6. The method according to any one of the preceding claims, characterized in that the second insulating film ( 95 ) is a nitride film. 7. The method according to any one of the preceding claims, characterized in that the second insulating film ( 95 ) is made with a thickness of about 50 to about 100 nm using a low pressure CVD process. 8. The method according to any one of the preceding claims, characterized in that the side walls ( 100 ) consist of a nitride film. 9. The method according to any one of the preceding claims, characterized in that the field oxidation for producing the field oxide films ( 101 ) is carried out at a temperature of 600 to 1000 ° C. 10. The method according to claim 9, characterized in that the field oxidation as an oxidation at high pressure at a temperature of 600 to 900 ° C or as a pyro-oxidation at a temperature of 900 to 1000 ° C in an H ₂ / O ₂ atmosphere of atmospheric pressure. 11. The method according to any one of the preceding claims, characterized in that the field oxide film ( 101 ) has a thickness of 450 to 600 nm. 12. The method according to any one of the preceding claims, characterized in that the second insulating film ( 95 ) on the polysilicon film ( 94 ) and the side walls ( 100 ) of the polysilicon film are removed by immersion in a 80 ° C hot phosphoric acid solution. 13. The method according to any one of the preceding claims, characterized in that the ion implantation for forming the source region ( 104 ) and the drain region ( 104 ) of low impurity ion concentration is carried out in that phosphorus ions as impurity ions with a dose of 2 , 0-3.0 × 10 ¹³ ions / cm ² and an energy of 20-40 keV can be used. 14. The method according to any one of the preceding claims, characterized in that the fourth insulating film ( 105 ) is produced by a low-pressure CVD process as an oxide film. 15. The method according to any one of the preceding claims, characterized in that the ion implantation for forming the source region ( 107 ) and the drain region ( 107 ) of high impurity ion concentration using arsenic ions as impurity ions with a dose of 2, 0-5.0 × 10 ¹⁵ ions / cm ² and an energy of 20-40 keV is executed. 16. The method according to any one of the preceding claims, characterized in that the tempering steps for forming the source regions ( 104 , 107 ) and the drain regions ( 104 , 107 ) low or high impurity ion concentration at a temperature of 700 to 900 ° C in H ₂ / N ₂ atmosphere. 17. The method according to any one of the preceding claims, characterized in that the interlayer insulating film ( 109 ) has a double-layer structure, with an oxide film which is deposited by a low-pressure CVD process, and a BPSG film, which is on this oxide film is deposited using a CVD process.