JPS6141136B2 - - Google Patents
Info
- Publication number
- JPS6141136B2 JPS6141136B2 JP15033781A JP15033781A JPS6141136B2 JP S6141136 B2 JPS6141136 B2 JP S6141136B2 JP 15033781 A JP15033781 A JP 15033781A JP 15033781 A JP15033781 A JP 15033781A JP S6141136 B2 JPS6141136 B2 JP S6141136B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- oxide film
- layer
- substrate
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
本発明はシリコン基板上における選択的な酸化
膜の形成法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for selectively forming an oxide film on a silicon substrate.
従来シリコン基板等を用いた半導体装置におい
て、各素子間の分離には、しばしば、酸化シリコ
ン膜が用いられ、通常、素子間を選択的に酸化す
ることにより行なわれてきた。その方法は各種あ
るがその代表例を第１図の工程に示す。 In conventional semiconductor devices using a silicon substrate or the like, a silicon oxide film is often used to separate each element, and this is usually done by selectively oxidizing the elements. There are various methods for this, and a representative example is shown in the steps in FIG.
まず第１図ａに示すようにシリコン基板１上に
酸化シリコン膜２、さらに窒化シリコン膜３を形
成する。次に第１図ｂに示すように窒化シリコン
膜３および酸化シリコン膜２を選択的に食刻した
後、窒化シリコン膜３をマスクにして上記シリコ
ン基板１内に拡散層５を形成する。その後、第１
図ｃに示すように熱酸化工程によつてシリコン基
板の露出面を酸化することにより同所に選択的に
酸化膜を形成してきた。 First, as shown in FIG. 1A, a silicon oxide film 2 and a silicon nitride film 3 are formed on a silicon substrate 1. Next, as shown in FIG. 1B, after selectively etching the silicon nitride film 3 and the silicon oxide film 2, a diffusion layer 5 is formed in the silicon substrate 1 using the silicon nitride film 3 as a mask. Then the first
As shown in FIG. c, the exposed surface of the silicon substrate is oxidized by a thermal oxidation process to selectively form an oxide film thereon.
しかし、上述の従来方法では選択酸化膜形成時
に酸素の等方的拡散性あるいは酸化シリコン膜２
とシリコン基板界面を通してシリコン基板に酸素
が供給される等のため、前記選択酸化膜が横方向
に広がり、同時に不純物拡散層５も選択酸化膜形
成時の熱工程によりさらに横方向に広がるため、
いわゆるバーズビークが形成される。このような
バーズビークは、片側で約0.7〜1.2μｍに達し、
デザインルームが約４μｍ以上では、あまり問題
とならないが、装置の高集積化が進むにつれ、し
だいに大きな障害となる。 However, in the conventional method described above, when forming a selective oxide film, oxygen isotropically diffused or the silicon oxide film 2
Because oxygen is supplied to the silicon substrate through the interface between the selective oxide film and the silicon substrate, the selective oxide film spreads laterally, and at the same time, the impurity diffusion layer 5 also spreads further laterally due to the thermal process during the formation of the selective oxide film.
A so-called bird's beak is formed. Such a bird's beak reaches about 0.7-1.2 μm on one side,
If the design room is about 4 μm or more, this will not be much of a problem, but as devices become more highly integrated, this will gradually become a major obstacle.
本発明はこれら従来方法の問題点を解決する新
規な方法を与えるものである。その特徴点は、第
１に多結晶シリコンが基板単結晶シリコンより酸
化されやすいことを利用して選択酸化領域の単結
晶シリコン上に多結晶シリコン層を被着した２層
構造として後、通常の熱酸化法で選択酸化膜を形
成することにより横方向の広がりの少ない選択酸
化膜が形成できること、第２に、不純物導入層形
成前に窒素シリコン膜３および酸化シリコン膜２
の開口部より小さな開口部をもつ多結晶シリコン
のマスク層を形成した後、このマスクを介して不
純物導入層を選択形成することにより、同不純物
導入層は、その横方向への広がりを見越しても、
なお、多結晶シリコン層開口部寸法に対応して小
さく抑制できることである。 The present invention provides a new method that solves the problems of these conventional methods. Its characteristic points are: firstly, it takes advantage of the fact that polycrystalline silicon is more easily oxidized than the substrate single-crystal silicon, and forms a two-layer structure in which a polycrystalline silicon layer is deposited on the single-crystalline silicon in the selective oxidation region; By forming a selective oxide film using a thermal oxidation method, a selective oxide film with less lateral spread can be formed.Secondly, the nitrogen silicon film 3 and silicon oxide film 2 are
After forming a polycrystalline silicon mask layer with an opening smaller than the opening of too,
Note that this can be suppressed to a small size corresponding to the opening size of the polycrystalline silicon layer.
以下に図面を用いて、本発明の概要および実施
例の詳細な説明を行なう。 An overview of the present invention and detailed explanations of embodiments will be given below using the drawings.
第２図の工程図を参照して本発明の方法の概要
をのべる。第２図ａに示すようにシリコン基板１
上に酸化シリコン膜２および窒化シリコン膜３を
形成し、窒化シリコン膜３および酸化シリコン膜
２を選択的に食刻開口し、さらに、この開口部シ
リコン基板表面を所定の深さに食刻する。 An overview of the method of the present invention will be described with reference to the process diagram in FIG. As shown in FIG. 2a, a silicon substrate 1
A silicon oxide film 2 and a silicon nitride film 3 are formed thereon, and openings are selectively etched in the silicon nitride film 3 and silicon oxide film 2, and the surface of the silicon substrate at the openings is further etched to a predetermined depth. .
次に第２図ｂに示すように上記開口部内に多結
晶シリコン層４を被着し、さらに、この多結晶シ
リコン層４に不純物導入のための窓を上記窒化シ
リコン膜３および上記酸化シリコン膜３の開口寸
法より小さく開口して、この窓を通して不純物導
入層５を形成する。そして、第２図Ｃに示すよう
に、多結晶シリコン層及び基板シリコンを同時に
熱工程で酸化処理すればこの工程で形成される選
択酸化膜はもちろん、その直下の拡散層５の横方
向の広がりも抑制することが可能である。 Next, as shown in FIG. 2b, a polycrystalline silicon layer 4 is deposited in the opening, and a window for introducing impurities is formed in the polycrystalline silicon layer 4 using the silicon nitride film 3 and the silicon oxide film. The impurity-introduced layer 5 is formed through this window by making an opening smaller than the opening size of 3. As shown in FIG. 2C, if the polycrystalline silicon layer and the substrate silicon are simultaneously oxidized by a thermal process, not only the selective oxide film formed in this process but also the lateral spread of the diffusion layer 5 directly below it. It is also possible to suppress
以下に実施例について詳細に説明する。 Examples will be described in detail below.
第３図に実施例の工程を示す。 FIG. 3 shows the steps of the example.
まずシリコン基板１上に熱酸化法で厚さ約600
Åの酸化シリコン膜２を形成し、次にCVD法で
厚さ約1200Åの窒化シリコン膜３を形成した後、
窒化シリコン膜３及び酸化シリコン膜２を選択的
に食刻して開口部を形成し、さらに窒化シリコン
膜３及び酸化シリコン膜２をマスクにしてシリコ
ン基板１を約1000Å選択的に食刻し、さらにウエ
ハ全面にCVD法で厚さ500Åの多結晶シリコン層
４を形成する。（第３図ａ）次に食刻露出された
シリコン基板１上以外の多結晶シリコン層４を選
択的に除去すると同時に選択酸化する開口部内の
多結晶シリコン層に不純物導入のための窓を窒化
膜開口寸法より小さく開口し、この窓を通して不
純物導入層５を形成する。（第３図ｂ）最後に多
結晶シリコン層４及び基板シリコン１を同時に酸
化処理した後、窒化シリコン膜３を除去する。
（第３図ｃ）。 First, a film with a thickness of about 600 mm was deposited on a silicon substrate 1 using a thermal oxidation method.
After forming a silicon oxide film 2 with a thickness of 1,200 Å, and then forming a silicon nitride film 3 with a thickness of approximately 1200 Å using the CVD method,
The silicon nitride film 3 and the silicon oxide film 2 are selectively etched to form an opening, and the silicon substrate 1 is selectively etched by approximately 1000 Å using the silicon nitride film 3 and the silicon oxide film 2 as masks. Furthermore, a polycrystalline silicon layer 4 with a thickness of 500 Å is formed on the entire surface of the wafer by CVD. (Figure 3a) Next, the polycrystalline silicon layer 4 other than the exposed silicon substrate 1 is selectively removed, and at the same time, a window for introducing impurities into the polycrystalline silicon layer within the opening to be selectively oxidized is nitrided. An opening smaller than the film opening size is formed, and the impurity-introduced layer 5 is formed through this window. (FIG. 3b) Finally, after simultaneously oxidizing the polycrystalline silicon layer 4 and the silicon substrate 1, the silicon nitride film 3 is removed.
(Figure 3c).
本方法によれば多結晶シリコン層４により酸化
シリコン膜２と基板シリコン１との界面を通して
基板シリコン１への酸素供給が極めて少なく、ま
た多結晶シリコン層４が基板シリコン１よりも酸
化速度が速いことにより、短時間の熱工程で選択
酸化膜が形成されるから酸化膜の横方向への広が
りが著しく抑制される。さらに拡散層５があらか
じめ選択酸化膜形成用の多結晶シリコン層４に設
けられた小さい窓の直下に形成されていることに
より同拡散層５が横方法に広がつても選択酸化膜
より外側まで広がることはない。 According to this method, the supply of oxygen to the substrate silicon 1 through the interface between the silicon oxide film 2 and the substrate silicon 1 is extremely small due to the polycrystalline silicon layer 4, and the oxidation rate of the polycrystalline silicon layer 4 is faster than that of the substrate silicon 1. As a result, a selective oxide film is formed in a short heat process, so that the lateral spread of the oxide film is significantly suppressed. Furthermore, since the diffusion layer 5 is formed in advance directly under the small window provided in the polycrystalline silicon layer 4 for forming the selective oxide film, even if the diffusion layer 5 spreads laterally, it extends beyond the selective oxide film. It won't spread.
従来方法によれば選択酸化膜の横方向の広がり
は片側で0.8〜1.2μｍ程度あるが本方法によれば
0.5μｍ以下に抑えることが可能である。 According to the conventional method, the lateral spread of the selective oxide film is about 0.8 to 1.2 μm on one side, but with the present method,
It is possible to suppress the thickness to 0.5 μm or less.
第１図ａ，ｂ，ｃは従来の選択酸化膜形成方法
を示す工程図、第２図ａ，ｂ，ｃは本発明の概略
を示す工程図、第３図ａ，ｂ，ｃは本発明の実施
例を示す工程図である。
１……基板シリコン、２……シリコン酸化膜、
３……シリコン窒化膜、４……多結晶シリコン
層、５……不純物導入層。
Figures 1a, b, and c are process diagrams showing a conventional selective oxide film forming method, Figures 2a, b, and c are process diagrams showing an outline of the present invention, and Figures 3a, b, and c are process diagrams showing the present invention. It is a process diagram showing an example of. 1...Substrate silicon, 2...Silicon oxide film,
3... Silicon nitride film, 4... Polycrystalline silicon layer, 5... Impurity introduced layer.
Claims (1)
る２層マスク層に選択形成された開口部を通して
シリコン基板表面を食刻する工程と、前記シリコ
ン窒化膜およびシリコン酸化膜の開口部に前記開
口部よりも小さな開口部をもつ多結晶シリコン層
を設ける工程と、前記多結晶シリコン層小開口部
を通して前記シリコン基板に不純物導入層を形成
する工程と、前記多結晶シリコン層とシリコン基
板とを同時に酸化する工程とから成ることを特徴
とする選択酸化膜の形成法。1. Etching the surface of the silicon substrate through openings selectively formed in a two-layer mask layer consisting of a silicon nitride film and a silicon oxide film, and etching the openings in the silicon nitride film and silicon oxide film smaller than the openings. a step of providing a polycrystalline silicon layer having an opening, a step of forming an impurity introduction layer on the silicon substrate through the small opening in the polycrystalline silicon layer, and a step of simultaneously oxidizing the polycrystalline silicon layer and the silicon substrate. A method for forming a selective oxide film, characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15033781A JPS5850754A (en) | 1981-09-21 | 1981-09-21 | Formation of selective oxide layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15033781A JPS5850754A (en) | 1981-09-21 | 1981-09-21 | Formation of selective oxide layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5850754A JPS5850754A (en) | 1983-03-25 |
| JPS6141136B2 true JPS6141136B2 (en) | 1986-09-12 |
Family
ID=15494794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15033781A Granted JPS5850754A (en) | 1981-09-21 | 1981-09-21 | Formation of selective oxide layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5850754A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0361218A (en) * | 1989-07-27 | 1991-03-18 | Canon Inc | Sheet carrying device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH078311B2 (en) * | 1987-03-17 | 1995-02-01 | 株式会社テック | Electric razor with trimmer |
| US6306726B1 (en) * | 1999-08-30 | 2001-10-23 | Micron Technology, Inc. | Method of forming field oxide |
-
1981
- 1981-09-21 JP JP15033781A patent/JPS5850754A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0361218A (en) * | 1989-07-27 | 1991-03-18 | Canon Inc | Sheet carrying device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5850754A (en) | 1983-03-25 |
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