經濟部智慧財產局員工消費合作社印製 1 508722 4 · A7 ______ B7 五、發明說明（1 ) ' [發明領域] 本發明係相關於製造次微米半導體庐w Ί寸；I，而且特別 是，相關於使用修整及蝕刻方法以製造呈有 、 自仃對準通道 停止區的次微米半導體裝置。 、 [發明背景] 一 在製造積體電路裝置期間，裝置互相間係藉由厚的尸 氧化物（FOX)及通道摻雜（channel doping)的細人1 ”、 u . “ J、、、且3加以隔離 P 。需要隔離區的面積對於高積集度而言是一項限制 承 要的絕緣間隔一部分疋由於用來製造半導體裝置的制 " 果·程而 定。 當裝置幾何形狀縮小至次微米尺寸時，習知的製造過 程已達到效用的極限。例如，比較用來製造呈有1)5 微求的外觀尺寸之CMOS(互補式金屬氧化半導體）電路一的〜 製造流程，與用於具有0 · 8微米的外觀尺寸的電路之習知 製程。 . 用於製造丨·25至2微米裝置的製程係開始於圖案上的 薄氮化物層覆蓋基質，該圖案係限定主動元件及F〇x區。 其後’在通道停止區植入製程期間，在場區域的基質係選 擇性地植入諸如硼的通道停止區摻雜。在局部矽氧化（L〇 C〇S)製程期間，該場氧化物隨後成長以形成ρ〇X區。在 這個製程期間，該通道停止區係自行與F〇X區對準。氮化 物層隨後係由主動區移除，而且閘極氧化物係在閘極層的 多石夕晶沉積後而成長。 在通道植入後而實施LOCOS 由於F〇X區的成 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐) 一" '" 91795 裝 訂---------線 (靖先閱讀背面之注音？事項再填寫本頁)Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 508722 4 · A7 ______ B7 V. Description of the Invention (1) '[Field of Invention] The present invention is related to the manufacture of sub-micron semiconductors; I, and in particular, related Trimming and etching methods are used to fabricate sub-micron semiconductor devices with self-aligned channel stop regions. [Background of the Invention]-During the manufacture of integrated circuit devices, the devices are connected to each other by thick corpse oxide (FOX) and channel doping (1), u. "J ,, and 3 Isolate P. The area where the isolation area is required is a limitation for the high degree of integration. Part of the required insulation interval depends on the process used to manufacture the semiconductor device. As device geometries shrink to sub-micron dimensions, conventional manufacturing processes have reached the limit of effectiveness. For example, compare the manufacturing process for manufacturing a CMOS (Complementary Metal Oxide Semiconductor) circuit with an appearance size of 1.5 micrometers, and a conventional manufacturing process for a circuit with an appearance size of 0.8 microns. The process for manufacturing a 25 to 2 micron device begins with a thin nitride layer over a pattern covering the substrate, which pattern defines the active device and the F0x region. Thereafter 'during the channel stop region implantation process, the matrix system in the field region is selectively implanted with a channel stop region doping such as boron. During the local silicon oxide (LOCOS) process, the field oxide subsequently grows to form a ρOX region. During this process, the channel stop area is aligned with the FOX area on its own. The nitride layer is subsequently removed from the active region, and the gate oxide is grown after the stone layer of the gate layer is deposited. Implementation of LOCOS after channel implantation Due to the cost of the FOX area, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)-"&" 91795 Binding --------- Line (Jing first read the phonetic on the back? Matters and then fill out this page)
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五、發明說明（2 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 ΐ是向區的掺雜“的熱擴散。因為該裝 數量是相當小的：心較間的間隔而言，熱擴散的 影響這類大型I ^ 所引起的擴散不會負面地 人t裝置。因為由於較 自F〇x區的摻雜元去卢 刃叛在本間隔，來 ，兀素钕入主動區而且包括 製程是不合適的。 通裝置，所以該 第1八至1〇圖係為-基質的截面圖，顯示用於製迕 CMOS電路的改良贺 用於1造 又I k程，該電路具有大 外觀尺寸。如第1A …其”。圖所顯不者，首先由-層的氮化物1〇 "L積在基貝12上而且隨後加以 然只維持在主動區。第於鼠化物10仍 w 第1B圖係顯示熱氧化階（thermai 〇xlde 柳）f逍後進行生成介於主動區間的場氧化物（F0X)11C 圖係顯不在F〇X區14已生成後，氮化物ι〇選擇性地加以 移除，而且光阻在剩餘的氮化物層形成圖案充當為通道停 止區植入製程的光罩16，如箭頭所示者。 雖然製程對於較舊的技術具有改良之處，但是該製程 承受微影光阻誤差的限制。為提供介於主動區間的適當通 道寬度，必須使用相當厚的光罩以形成具有14〇奈米的等, 級或〇」4微米的等級誤差之圖案。為防止氧化物及摻雜 元素侵犯主動區的密集間隔氮化物層，光阻藉由增加或減 少大約100奈米或0.】微米，不與氮化物層對齊。以明確 的誤差在諸如厚光阻層上形成圖案是非常困難的。再者， 在此製程中，FOX區與通道停止區不是自行對齊的。 因此，在改良的絕緣製程所需要者是適用於具有外迤 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐) ------- 2 91795 (請先闓tt背面之注意事項再填寫本頁) 麟· 訂----線！ J / I _ 508722 經濟部智慧財產局員工消費合作社印製 3 A7 B7 五、發明說明（3 ) 尺寸.3微米的半導體裝置。本發明即滿足這類需要。 [發明概述] 揭示一種具有自行對準通道停止區之次微米半導體裝 置，而且一種使用修整及蝕刻以製造半導體裝置的方法。 次微米半導體裝置係包括攀個藉由絕緣區所分開的主動 區。一種用於製造該裝置的方法是包括沉積氮化物層在基 質上’及選擇性以光罩覆蓋主動區，其中該光罩加以延伸 超過該主動區的邊界以縮小絕緣區的寬度。其後，實施通 道停止區植入以形成通道停止區。在形成通道停止區後， 光罩隨後加以修整至主動層的邊界，接著蝕刻在光罩的已 曝光區域的氮化物。場氧化物隨後在絕緣層成長，因而場 氧化物係自行對準於通道停止區。 根據本發明，放大氮化物光罩以縮小通道停正區植入 的絕緣區係有效地減少在LOCOS製程期間所擴散的摻雜 元素，這可允許製造較小的裝置。 [圖式之簡要說明] 第1A至1C圖係為一基質的截面圖，顯示用於製造 CMOS電路的改良製造流程，該電路具有大約〇 8微米的 外觀尺寸。 第2A至2E圖係為一基質的截面圖，顯示依照本發 明使用修整和蝕刻製造具有自行對準通道停止區植入的次 微米半導體裝置的製造流程。 [元件符號說明] __氮化物 12 基質 石氏張尺度顧？家標準（CNS)A4 g (210—X—297 公餐5---------- 91795 裝--------訂----------線 (請先閱讀背面之注意事項再填寫本頁) 508722 五、發明說明（ 14 20 24 F〇X區 氮化物 通道停 止區 16 22 26 光罩 光罩 場氧化物 經濟部智慧財產局員工消費合作社印說 [較佳實施例之詳細描述] 本發明係相關於一種用於製造次微米半導體裝置的潔 程以下描述使得熟習此技藝者可製造及使用本發明，.而 也提供作為專利申請之内容及其說明書。較佳實施例的 許多改良及在此描述的原理及觀點對於熟習此技藝者來說 疋非常明顯的。因此，本發明並不侷限在這些實施例，而 且本發明符合在此描述原理及觀點的最廣泛範圍。 本發明係一種具有自行對準通道停止區之次微米半導 體裝置，以及使用修整和蝕刻製造此半導體裝置之方法。 本發明係使用具有大約〇 · 3微米或更小的外觀尺寸的 CMOS裝置作為範例，但是熟習此技藝者瞭解本發明的方 法及裝置可使用其他種類的裝置。 請參照第2A至2D圖，基質的截面圖係顯示本發明使 用修整和姓刻製造具有自行對準通道停止區植入的次微米 半導體裝置的製造流程。如第2A圖所顯示，該製程係以 沉積氮化物20在基質12開始。 其次，如第2B圖所顯示，光阻係選擇性在剩餘的氮 化物20形成圖案當作光罩22。根據本發明，光罩22加以 延伸超過該主動區的每側邊界大約50奈米以縮小絕緣區 的寬度。 u_第2 C圖係顯示隨後進行通道停止區植入在光罩22的 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) ------ 4 91795 508722V. Description of the invention (2 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is doped to the area. “Thermal diffusion. Because the number of installations is quite small: in terms of interval, the effect of thermal diffusion is The diffusion caused by the large-scale I ^ will not negatively affect the device. Because the dopant element from the F0x region is not used in this interval, it is not suitable for the element to enter the active region and include the manufacturing process. Therefore, the eighteenth to tenth drawings are cross-sectional views of the substrate, showing the improvement of the CMOS circuit used in the manufacturing process and the I k process, the circuit has a large appearance size. 1A… its ". What is not shown in the figure is that the nitride of the layer-10" is first accumulated on Kibe 12 and then maintained only in the active region. The mouse compound 10 remains w Figure 1B It shows that the thermal oxidation stage (thermai 〇lde willow) f after the formation of the field oxide (F0X) 11C in the active range is shown in Figure F. After the FOX region 14 has been formed, the nitride ι〇 is selectively removed , And the photoresist forms a pattern in the remaining nitride layer as a channel The photomask 16 of the stop region implantation process is shown by the arrow. Although the process has improvements to the older technology, the process is subject to the limitations of lithographic photoresistance errors. In order to provide an appropriate channel width between the active regions It is necessary to use a fairly thick photomask to form a pattern with a level error of 14 nanometers, equal, or 0,4 microns. In order to prevent oxides and doping elements from invading the densely spaced nitride layer of the active area, photoresist By increasing or decreasing by about 100 nm or 0.] microns, it is not aligned with the nitride layer. It is very difficult to form a pattern on a thick photoresist layer with a clear error. Moreover, in this process, the FOX region It is not self-aligned with the channel stop area. Therefore, what is needed in the improved insulation process is applicable to the national standard (CNS) A4 specification (210 X 297 mm) with external paper size applicable to the country. ----- -2 91795 (Please note the precautions on the back of the page before filling out this page) Lin · Order ---- Line! J / I _ 508722 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 A7 B7 V. Description of the invention ( 3) Size. 3 micron semiconductor The present invention satisfies such needs. [Summary of the Invention] A sub-micron semiconductor device having a self-aligned channel stop region and a method for manufacturing a semiconductor device using trimming and etching are disclosed. Active area separated by an insulating area. One method for manufacturing the device includes depositing a nitride layer on the substrate and selectively covering the active area with a mask, wherein the mask extends beyond the boundary of the active area In order to reduce the width of the insulation region, a channel stop region is implanted to form a channel stop region. After the channel stop region is formed, the photomask is subsequently trimmed to the boundary of the active layer, and then etched on the exposed area of the photomask. nitride. The field oxide then grows in the insulating layer, so the field oxide is aligned with the channel stop region by itself. According to the present invention, the insulating region implanted by enlarging the nitride mask to reduce the channel stop region effectively reduces the dopant elements diffused during the LOCOS process, which may allow the manufacture of smaller devices. [Brief description of the drawings] Figures 1A to 1C are cross-sectional views of a substrate showing an improved manufacturing process for manufacturing a CMOS circuit having an appearance size of about 0.8 micrometers. Figures 2A to 2E are cross-sectional views of a substrate showing a manufacturing process for manufacturing a sub-micron semiconductor device with self-aligned channel stop region implantation using trimming and etching in accordance with the present invention. [Explanation of Symbols] __Nitride 12 Matrix Shi's Zhang Gu? Home Standard (CNS) A4 g (210-X-297 Meal 5 ---------- 91795 Pack -------- Order ---------- Line (Please Read the precautions on the back before filling this page) 508722 V. Description of the invention (14 20 24 FOX Zone Nitride Channel Stop Zone 16 22 26 Mask Mask Mask Field Oxide Ministry of Economics Intellectual Property Bureau Staff Consumer Cooperative Cooperative Seal [ Detailed description of the preferred embodiment] The present invention is related to a cleaning process for manufacturing sub-micron semiconductor devices. The following description allows those skilled in the art to make and use the present invention, and also provides the content of the patent application and its specification. Many improvements of the preferred embodiments and the principles and perspectives described herein will be apparent to those skilled in the art. Therefore, the present invention is not limited to these embodiments, and the present invention conforms to the principles and perspectives described herein. The widest range of the present invention is a sub-micron semiconductor device having a self-aligned channel stop region, and a method of manufacturing the semiconductor device using trimming and etching. The present invention uses an external dimensions of about 0.3 microns or less CMOS device As an example, but those skilled in the art understand that the method and device of the present invention can use other types of devices. Please refer to Figures 2A to 2D. The cross-sectional view of the substrate shows that the present invention uses trimming and engraving to make a self-aligning channel stop. Sub-micron semiconductor device manufacturing process. As shown in FIG. 2A, the process starts by depositing nitride 20 on substrate 12. Secondly, as shown in FIG. 2B, the photoresist is selective to the remaining nitrogen. The compound 20 is patterned as a photomask 22. According to the present invention, the photomask 22 is extended beyond the boundary of each side of the active area by about 50 nanometers to reduce the width of the insulation area. U_2C shows the subsequent channel stop This paper size implanted in the mask 22 is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) ------ 4 91795 508722
、發明說明（ 已曝光區域植入摻雜元专， 停止區24。 ，、 更在已縮小絕緣區製造通道 1請先閲讀背面之注意事頊再填寫本頁) 回主^形成通道停止區24後，修整及㈣步驟在光罩修整 主動區的邊界上加以實施。 奈米的位置，光罩22在以 伸超過邊界50 置九罩22在主動區的每側邊界修整5〇奈米。 在較佳實施例中，Α ν 杂丨# 〒籍由以下的製程將光罩22擴大超過 2區，’包括在光罩^上進行卿U2%)的濕 因’以便移除該光罩表面的薄保護層Μ吏用濕製程的原 -於該保護層無法使用乾製程加以姓刻。在濕製程 光罩22可使用習知的乾巍刻製程_ + 〇2或Ν2+〇2)加以 回叫tch back)。接者是標準石夕韻刻及標準石[氮化物蝕 刻。 如苐2D圖所顯示，蔣古罢/欠杜七 旖疋罩22修整後，隨後蝕刻氮化 物20在光罩22的已曝光區域（絕緣區）。如第2e圖所顯 不，該製程的最後步驟是進行L〇c〇s製程以便在絕緣區 生成場氧化物26。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 根據本發明，將光罩22擴大超過主動區而且蝕刻氮化 物20後，這使得在製程中實施該通道停止區植入早於習知 次微米技術，而且確定場氧化物2 6係自行對齊通道停止區 24。將光罩22擴大以縮減用於該通道停止區的絕緣區係有 效地降低在LOCOS製程期間所擴散的摻雜元素，而且因 此允許較小的裝置。本發明可減輕光罩誤差的限制。 本纸張尺度適用中國國家標準（CNS)A4規格 所揭示具有自行對準通道停止區的次微米半導體裝 置，及一種用於製造使用修整及蝕刻的半導體裝置的方 91795 508722 A7 —^____SI ___ 五、發明說明（6 ) 法。雖然本發明與所顯示的實施例一致，但是熟習此技藝 者將容易地辨認實施例的變化而且認為這些變化在本發明 製 者 藝 技 此 習 。 熟疇 由範 藉及 可神 良精 改的 多圍 許範 ， 利 此專 因請 。 中 内屬 疇附 及偏 神不 精而 的造 (請先閱t»背面之注意事項再填寫本頁) 麟. 訂· ·、 Explanation of the invention (Implanted dopant element, stop region 24 is implanted in the exposed area. 、 To manufacture the channel 1 in the reduced insulation region, please read the note on the back first, and then fill out this page) Back to main ^ Form the channel stop region 24 After that, the trimming and squaring steps are performed on the boundary of the mask trimming active area. At the position of the nanometer, the mask 22 is extended beyond the boundary 50, and the nine mask 22 is trimmed by 50 nanometers on each side of the active area. In the preferred embodiment, the Α ν 杂 ## is expanded by the following process to more than 2 zones, 'including the wet factor on the mask ^ U2%) in order to remove the surface of the mask The thin protective layer M is made using a wet process-the protective layer cannot be engraved with a dry process. In the wet process, the photomask 22 can be called back tch back) using the conventional dry-etching process (+2 or 2 + 2). They are followed by standard Shi Xiyun engraving and standard stone [nitride etching. As shown in the 2D image, after Jiang Guba / Yu Duqi mask 3 is trimmed, nitride 20 is then etched in the exposed area (insulation area) of mask 22. As shown in Fig. 2e, the final step of the process is to perform a Locos process to generate field oxide 26 in the insulating region. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs according to the present invention, after the photomask 22 is enlarged beyond the active area and the nitride 20 is etched, this makes the implementation of the channel stop area implantation earlier in the process than the conventional submicron technology, It is determined that the field oxide 26 is aligned with the channel stop region 24 by itself. Enlarging the reticle 22 to reduce the insulating region for the channel stop region effectively reduces the doping elements diffused during the LOCOS process, and therefore allows smaller devices. The invention can alleviate the limitation of the mask error. This paper scale applies to the submicron semiconductor device with self-aligned channel stop area disclosed in the Chinese National Standard (CNS) A4 specification, and a method for manufacturing semiconductor devices using trimming and etching 91795 508722 A7 — ^ ____ SI ___ 5 Invention description (6) method. Although the present invention is consistent with the illustrated embodiment, those skilled in the art will readily recognize variations in the embodiments and consider these variations to be those of the present inventors. Familiarity is borrowed by Fan and can be modified by many people, Xu Fan, for the benefit of this special please. The Chinese are attached to the domain and are not refined (please read the precautions on the back of the t before filling out this page) Lin. Order · ·
i IM5 A8 BJB a pi I 線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 6 91795i IM5 A8 BJB a pi I Line Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 6 91795