^^9193¾ 5533twf *doc/006 A7 ____B7_ _ 五、發明説明（/ ) (請先閱讀背面之注意事項再i本頁) 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種在同一基底上，製作兩種不同厚度的閘極氧 化層之方法。 近年來隨著半導體製程技術的進步，其製造成本亦隨 .之急速下降，電子元件朝向多樣化發展等的結果，單一元 件已無法因應需求，因此目前半導體製程已逐漸朝向將邏 輯元件與記憶體元件整合在同一晶片上的趨勢，也就是所 謂的 SOC(system on chip)。 當整合邏輯元件與記憶體元件於同一晶片上時，邏輯 元件考慮的重點爲速度，通常在低電壓下操作，其電晶體 之尺寸較小，所使用的閘極氧化層厚度較薄：而記憶體元 件考慮的重點爲可靠度（也就是高穩定性），通常在高電壓 下操作，其電晶體所使用的閘極氧化層厚度較厚。 第1A圖至第1C圖繪示爲習知的一種雙閘極氧化層的 製作流程剖面圖。 經濟部智慧財產局員工消費合作社印製 請參照第1A圖，提供一半導體矽基底100，在基底100 上形成淺溝渠隔離結構102，以定義出主動區104與106 ; 其中，主動區104用以形成低操作電壓元件的區域，而主 動區106用以形成高操作電壓元件的區域。以熱氧化法在 基底100上形成一層第一閘極氧化層108。 請參照第1B圖，形成一光阻層110覆蓋欲形成高操作 電壓元件的主動區106，進行非等向性蝕刻，去除未被光 阻110覆蓋的第一閘極氧化層108,剩餘之第一閘極氧化 層標號爲10 8 a。 3 本紙張尺度適用中國國家標準（CMS ) A4規格（210X297公釐） " "" 43 91 93'^ 5533twf.doc/006 A7 _ B7 五、發明説明（> ) 請參照第1C圖，剝除光阻層110,再次進行熱氧化法， 以在基底100上形成第二閘極氧化層112，由於熱氧化法 形成的二氧化矽係由氧與基底100中的矽反應生成，因此 在具有高操作電壓元件的主動區106上的第二閘極氧化層 .112位於剩餘的第一閘極氧化層108a與基底100之間。此 時，低操作電壓元件的主動區104上方只有第二閘極氧化 層112，而高操作電壓元件的主動區106上方具有第一閘 極氧化層108a與第二閘極氧化層112，如此就形成厚度不 相同的元件區域。 然而，使用上述方法形成的雙閘極氧化層，由於欲形 成高操作電壓元件的主動區上之閘極氧化層係由兩步驟彤 成的氧化層組成，在第一閘極氧化層與第二閘極氧化層之 間會有界面存在，會使厚的閘極氧化層耐電壓的強度會變 差，習知通常會利用一道回火步驟來改善厚的閘極氧化層 的品質，但並無法完全消除界面的存在造成的影響。 此外，由於形成第二閘極氧化層，在具有高操作電壓 元件的主動區進行熱氧化法時，氧必須擴散穿過第一閘極 氧化層才能夠與基底反應形成二氧化矽，因此在欲形成高 操作電壓元件的主動區上的第二閘極氧化層會比欲形成低 操作電壓元件的主動區上的第二閘極氧化層薄，如此一來 閘極氧化層的厚度便不易控制。 有鑑於此，本發明提供一種製作雙閘極氧化層的方法， 在欲形成高操作電壓元件的主動區上形成的閘極氧化層並 不會有界面，且閘極氧化層的厚度容易控制，因此可以得 4 本紙張只波適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再梦tis本頁)^^ 9193¾ 5533twf * doc / 006 A7 ____B7_ _ 5. Description of the Invention (/) (Please read the precautions on the back before this page) The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device. Method for making two gate oxide layers with different thicknesses on the same substrate. In recent years, with the advancement of semiconductor process technology, its manufacturing costs have also fallen rapidly. As a result of the diversified development of electronic components, single components have been unable to respond to demand. Therefore, the current semiconductor process has gradually moved towards integrating logic components and memory. The tendency for components to be integrated on the same chip is also known as SOC (system on chip). When integrating logic elements and memory elements on the same chip, the main consideration for logic elements is speed, which usually operates at low voltages, the size of the transistor is small, and the gate oxide layer used is thin: The main consideration for body components is reliability (that is, high stability), which usually operates at high voltages, and the gate oxide layer used in its transistors is thicker. FIG. 1A to FIG. 1C are cross-sectional views showing a manufacturing process of a conventional double-gate oxide layer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to FIG. 1A. A semiconductor silicon substrate 100 is provided, and a shallow trench isolation structure 102 is formed on the substrate 100 to define active areas 104 and 106. Among them, the active area 104 is used for A region of a low operating voltage element is formed, and an active region 106 is used to form a region of a high operating voltage element. A first gate oxide layer 108 is formed on the substrate 100 by a thermal oxidation method. Referring to FIG. 1B, a photoresist layer 110 is formed to cover the active region 106 where a high operating voltage element is to be formed, and anisotropic etching is performed to remove the first gate oxide layer 108 not covered by the photoresist 110. A gate oxide layer is labeled 10 8 a. 3 This paper size applies the Chinese National Standard (CMS) A4 specification (210X297 mm) " " " 43 91 93 '^ 5533twf.doc / 006 A7 _ B7 V. Description of the invention (>) Please refer to Figure 1C The photoresist layer 110 is stripped and a thermal oxidation method is performed again to form a second gate oxide layer 112 on the substrate 100. Since the silicon dioxide formed by the thermal oxidation method is generated by the reaction between oxygen and silicon in the substrate 100, A second gate oxide layer 112 on the active region 106 having a high operating voltage element is located between the remaining first gate oxide layer 108 a and the substrate 100. At this time, there is only the second gate oxide layer 112 above the active region 104 of the low operating voltage element, and the first gate oxide layer 108a and the second gate oxide layer 112 are above the active region 106 of the high operating voltage element. Element regions having different thicknesses are formed. However, the double-gate oxide layer formed using the above method, because the gate oxide layer on the active region of the high-operation voltage element to be formed is composed of a two-step oxide layer, the first gate oxide layer and the second gate oxide layer There will be an interface between the gate oxide layers, which will make the withstand voltage strength of the thick gate oxide layer worse. It is common practice to use a tempering step to improve the quality of the thick gate oxide layer, but it cannot Completely eliminate the impact of the presence of the interface. In addition, due to the formation of the second gate oxide layer, when the thermal oxidation method is performed in the active region of the high operating voltage element, oxygen must diffuse through the first gate oxide layer to be able to react with the substrate to form silicon dioxide. The second gate oxide layer on the active region where the high operating voltage element is formed is thinner than the second gate oxide layer on the active region where the low operating voltage element is to be formed, so that the thickness of the gate oxide layer is difficult to control. In view of this, the present invention provides a method for manufacturing a double gate oxide layer. The gate oxide layer formed on the active region of a high operating voltage element does not have an interface, and the thickness of the gate oxide layer is easy to control. Therefore, you can get 4 sheets of paper only applicable to China National Standard (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before dreaming this page)
丁 、1' 瘁， 經濟部智慧財產局員工消費合作社印製 4 3 91 93¾ 5 5 3 3 twf . doc / Ο Ο 6 A7 B7 五、發明説明（3 ) 到高品質，且高可靠度的雙閘極氧化層。 (請先閱讀背面之注意事項再济^'·本頁) 本發明提出一種製作雙閘極氧化層的方法，提供包括 第一區域與第二區域的基底，全面形成一層第一閘極氧化 層，並在第一閘極氧化層上覆蓋一層阻擋層；進行微影與 鈾刻製程，僅留下第一區域上的阻擋層與第一閘極氧化 層，其他區域則暴露出基底。形成一層第二閘極氧化層覆 蓋第一區域以外的基底，因第二閘極氧化層的厚度也可大 於第一閘極氧’化層。 由於第一區域上的第一閘極氧化層被阻擋層覆蓋住， 在形成第二閘極氧化層時，氧氣無法擴散透過阻擋層與第 一閘極氧化層，因此第一區域的氧化層厚度並不會有變 化，不論在第一區域的第一閘極氧化層，或第二區域的第 二閘極氧化層均只用到一道熱氧化法形成，因此即使是厚 的第二閘極氧化層也不會有界面。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂1 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 經濟部智慧財產局員工消費合作社印製 第1A圖至第1C圖繪示爲習知的一種雙閘極氧化層的 製作流程剖面圖；以及 第2A圖至第2E圖繪示依照本發明一較佳實施例的圖 一種雙閘極氧化層的製造方法。 圖示標記說明： 100, 200 半導體基底 5 本紙張尺度適.用中國國家標準（CNS ) A4規格（210X297公釐） 4 3 S1 9? wf.doc/006 A7 B7 五、發明説明（《） 102, 202 淺溝渠隔離結構 104, 204 第一區域 106, 206 第二區域 108, 108a, 208, 208a, 208b 第一閘極氧化層 110 光阻層 112 第二閘極氧化層 210 阻擋層 212, 212a 第二聞極氧化層 214 複晶砍層 214a, 214b 閘極 實施例 第2A圖至第2E圖繪示依照本發明一較佳實施例的圖 一種雙閘極氧化層的製造方法。 首先，請參照第2A圖，提供一半導體基底200，其較 佳比如爲具有P型摻雜之<100>矽基底。接著，在半導體 基底200上形成元件隔離結構202,定義出第一區域204 與第二區域206。第一區域204爲後續欲形成低操作電壓 元件之區域，而第二區域206爲後續欲形成高操作電壓元 件之區域。元件隔離結構202例如爲場氧化層或淺溝渠隔 離結構。在包括元件隔離結構202的基底200上全面形成 一層第一閘極氧化層208，形成的方法較佳爲熱氧化法， 其厚度約爲20-40埃。 請參照第2B圖，在第一閘極氧化層208上覆蓋一層阻 擋層210，其材質較佳爲氮化矽，厚度小於500埃，較佳 I—, 批农 [*—. I 訂 // I (請先閲讀背面之注意事項再ί本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標皁（CNS ) A4規格（210 X 297公釐） 4 3 91 3 3 5533twf.doc/006 八7 B7 五、發明说明（多） (請先閲讀背面之注意事項再¥本頁) 爲200-500埃。進行微影與蝕刻製程，去除第二區域206 上方的阻擋層210與第一閘極氧化層208，暴露出第二區 域206所在的基底200，而留下覆蓋第一區域204的阻擋 層210與第一鬧極氧化層208a。 請參照第2C圖，在暴露出來的基底200上形成一層第 二閘極氧化層212，其形成方法較佳爲熱氧化法，此熱氧 化法的溫度不超過攝氏900度，時間不超過1小時，所長 成的厚度約爲40-80埃。 成長第二閘極氧化層212時進行的熱氧化法，係在氧 氣的環境下進行，利用氧與基底200的矽反應生成二氧化 矽而來，由於第一閘極氧化層208a上覆蓋有阻擋層210， 參與反應的氧無法擴散穿過阻擋層210與第一閘極氧化層 208a，進一步與第一區域204所在的基底200中的矽反應， 因此第一閘極氧化層208a的厚度不會有變化。 經濟部智慧財產局員工消費合作社印製 請參照第2D圖，去除在第一區域204上第一閘極氧化 層208a上的阻擋餍210，去除的方法比如以濕蝕刻進行’ 較佳的蝕刻劑包括磷酸（Η3Ρ04)。之後，在第一閘極氧化層 208a與第二閘極氧化層212上覆蓋一層複晶砂層214 ^複 晶矽層214的形成方式比如爲化學氣相沈積法。 請參照第2E圖，進行罩幕微影製程，去除部分的複晶 矽層214、第一閘極氧化層208a與第二閘極氧化層212a， 以在第一區域204上定義出第一閘極214a以及位於第一 閘極214a與基底200之間的第一閘極氧化層208b ’並在 第二區域206上定義出第二閘極214b以及位於第二閘極 Ί 本紙張尺度適用中國國家標準（CNS )八4規格（2丨οχ2"公釐） 經濟部智慧財產局員工消費合作社印製Ding, 1 '瘁, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 3 91 93¾ 5 5 3 3 twf. Doc / Ο Ο 6 A7 B7 V. Description of the invention (3) To high-quality, high-reliability dual Gate oxide layer. (Please read the precautions on the back side first before ^ '· this page) The present invention proposes a method for fabricating a double gate oxide layer, providing a substrate including a first region and a second region, and forming a first gate oxide layer in an all-round way. And cover the first gate oxide layer with a barrier layer; the lithography and uranium etching processes are performed, leaving only the barrier layer and the first gate oxide layer on the first region, and the other regions expose the substrate. A second gate oxide layer is formed to cover the substrate other than the first region, because the thickness of the second gate oxide layer can also be larger than that of the first gate oxide 'layer. Because the first gate oxide layer on the first region is covered by the barrier layer, when forming the second gate oxide layer, oxygen cannot diffuse through the barrier layer and the first gate oxide layer, so the thickness of the oxide layer in the first region There will be no change, whether the first gate oxide layer in the first region or the second gate oxide layer in the second region is formed using only one thermal oxidation method, so even the thick second gate oxide There will be no interface in the layer. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible1, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: Intellectual Property Bureau, Ministry of Economic Affairs Figures 1A to 1C printed by employee consumer cooperatives are cross-sectional views of a conventional manufacturing process of a double-gate oxide layer; and Figures 2A to 2E are drawings according to a preferred embodiment of the present invention. A method for manufacturing a double-gate oxide layer. Description of the pictograms: 100, 200 semiconductor substrate 5 This paper is suitable in size. Use Chinese National Standard (CNS) A4 (210X297 mm) 4 3 S1 9? Wf.doc / 006 A7 B7 V. Description of the invention (") 102 , 202 Shallow trench isolation structure 104, 204 First region 106, 206 Second region 108, 108a, 208, 208a, 208b First gate oxide layer 110 Photoresist layer 112 Second gate oxide layer 210 Barrier layer 212, 212a The second anode oxide layer 214, the multiple crystal cutting layers 214a, 214b, and FIGS. 2A to 2E of the gate embodiment illustrate a method for manufacturing a double gate oxide layer according to a preferred embodiment of the present invention. First, referring to FIG. 2A, a semiconductor substrate 200 is provided. A preferred example is a < 100 > silicon substrate with a P-type doping. Next, an element isolation structure 202 is formed on the semiconductor substrate 200, and a first region 204 and a second region 206 are defined. The first region 204 is a region where a low operating voltage element is to be formed subsequently, and the second region 206 is a region where a high operating voltage element is to be formed subsequently. The element isolation structure 202 is, for example, a field oxide layer or a shallow trench isolation structure. A first gate oxide layer 208 is fully formed on the substrate 200 including the element isolation structure 202. The method for forming the first gate oxide layer 208 is preferably a thermal oxidation method, and the thickness is about 20-40 angstroms. Please refer to FIG. 2B, a barrier layer 210 is covered on the first gate oxide layer 208. The material is preferably silicon nitride and the thickness is less than 500 angstroms. The preferred I—, the farmer [* —. I order /// I (Please read the precautions on the back of this page before illuminating this page) Printed on the paper by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size is applicable to China National Standard Soap (CNS) A4 (210 X 297 mm) 4 3 91 3 3 5533twf .doc / 006 8 7 B7 5. Description of the invention (multiple) (Please read the precautions on the back before ¥ this page) 200-500 Angstroms. Lithography and etching processes are performed to remove the barrier layer 210 and the first gate oxide layer 208 over the second region 206, exposing the substrate 200 where the second region 206 is located, and leaving the barrier layer 210 and The first anode oxide layer 208a. Referring to FIG. 2C, a second gate oxide layer 212 is formed on the exposed substrate 200. The formation method is preferably a thermal oxidation method. The temperature of the thermal oxidation method does not exceed 900 degrees Celsius and the time does not exceed 1 hour. It grows into a thickness of about 40-80 angstroms. The thermal oxidation method performed when growing the second gate oxide layer 212 is performed in an oxygen environment. The oxygen is reacted with the silicon of the substrate 200 to generate silicon dioxide. Since the first gate oxide layer 208a is covered with a barrier Layer 210, the participating oxygen cannot diffuse through the barrier layer 210 and the first gate oxide layer 208a, and further react with the silicon in the substrate 200 where the first region 204 is located, so the thickness of the first gate oxide layer 208a will not Change. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to FIG. 2D, remove the barrier 餍 210 on the first gate oxide layer 208a on the first region 204, and the removal method is performed by wet etching Includes phosphoric acid (Q3P04). After that, the first gate oxide layer 208a and the second gate oxide layer 212 are covered with a polycrystalline sand layer 214. The formation method of the polycrystalline silicon layer 214 is, for example, a chemical vapor deposition method. Referring to FIG. 2E, a mask lithography process is performed to remove a part of the polycrystalline silicon layer 214, the first gate oxide layer 208a, and the second gate oxide layer 212a to define a first gate on the first region 204 Electrode 214a and the first gate oxide layer 208b 'located between the first gate 214a and the substrate 200, and define the second gate 214b and the second gate 214 on the second region 206. This paper scale applies to the country of China Standard (CNS) 8-4 Specification (2 丨 οχ2 " mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
4 3 91 " B533twf.doc/006 五、發明説明（6 ) 214b與基底200之間的第二閘極氧化層212a。 在第2A圖至第2E圖的圖示與上面的敘述中，是以第 一區域204作爲欲形成低操作電壓元件的區域，而第二區 域206則用以作爲欲形成高操作電壓元件的區域，因此第 一閘極氧化層208a的厚度小於第二閘極氧化層212。但在 實際的運用上，本案所提供的方法可適用於先形成較厚的 閘極氧化層，再形成厚度較薄的閘極氧化層，其形成步驟 與上面的敘述相同，僅是第一閘極氧化層的厚度與第二閘 極氧化層之厚度對調。 本發明以熱氧化法，分別在高操作電壓元件主動區與 低操作電壓元件的主動區上形成第一閘極氧化層與第二閘 極氧化層，兩層閘極氧化層分別以一個步驟形成，不僅製 程簡單，而且避免習知利用兩個步驟形成高操作電壓元件 主動區之閘極氧化層，致使厚的閘極氧化層中產生界面 (interface)，藉以避免因界面所造成的可靠性 (r e 1 i ab i 1 i t y)的問題。如此，即可提升厚的閘極氧化層 的品質（qua 1 i t y )。此外，又因本發明厚的閘極氧化層係 以一個步驟的熱氧化法形成，因此沒有界面的存在，便無 需進行另一回火步驟以改善厚的閘極氧化層的品質，使整 個製程更爲簡易。 此外，本案於進行第二閘極氧化層的熱氧化法時，第 一閘極氧化層上覆蓋有一層阻擋層，氧無法穿透過第一閘 極氧化層而與基底進一步的反應產生二氧化矽，因此無須 擔心第一閘極氧化層的厚度會產生變化，且厚的第二閘極 S A7 B7 (請先閲讀背面之注意事項再ί本頁) 丁 -s 等 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 43 3193'^ 5533twf,d〇c/006 ^ B7 五、發明説明（7) 氧化層是以單一步驟的熱氧化法形成，不會出現習知厚度 不易控制的問題。 雖然本發明已以一較佳實施例掲露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 .神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 經濟部智慧財產局員工消費合作社印製 【尺 I張 紙 ί本 準 標 家 國 國 *^i 用 適4 3 91 " B533twf.doc / 006 V. Description of the invention (6) The second gate oxide layer 212a between 214b and the substrate 200. In the illustrations of FIGS. 2A to 2E and the above description, the first region 204 is used as a region where a low operating voltage element is to be formed, and the second region 206 is used as a region where a high operating voltage element is to be formed. Therefore, the thickness of the first gate oxide layer 208a is smaller than that of the second gate oxide layer 212. However, in practical application, the method provided in this case can be applied to form a thicker gate oxide layer first, and then form a thinner gate oxide layer. The formation steps are the same as those described above, only the first gate The thickness of the polar oxide layer is opposite to the thickness of the second gate oxide layer. The invention uses a thermal oxidation method to form a first gate oxide layer and a second gate oxide layer on the active region of the high operating voltage element and the active region of the low operating voltage element, respectively. The two gate oxide layers are formed in one step, respectively. Not only is the process simple, but also avoids the conventional use of two steps to form the gate oxide layer of the active region of the high operating voltage element, resulting in an interface in the thick gate oxide layer, thereby avoiding the reliability caused by the interface ( re 1 i ab i 1 ity). In this way, the quality of the thick gate oxide layer (qua 1 i t y) can be improved. In addition, because the thick gate oxide layer of the present invention is formed by a one-step thermal oxidation method, there is no interface, so there is no need to perform another tempering step to improve the quality of the thick gate oxide layer, so that the entire process Easier. In addition, in the case of performing the thermal oxidation method of the second gate oxide layer, the first gate oxide layer is covered with a barrier layer, and oxygen cannot pass through the first gate oxide layer and further react with the substrate to generate silicon dioxide. , So there is no need to worry about the thickness of the first gate oxide layer will change, and the thick second gate S A7 B7 (please read the precautions on the back first and then this page) D-s, etc. This paper size applies Chinese national standards (CNS) A4 specification (210 × 297 mm) 43 3193 '^ 5533twf, doc / 006 ^ B7 V. Description of the invention (7) The oxide layer is formed by a single-step thermal oxidation method, and the conventional thickness cannot be easily controlled. The problem. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [I sheet of paper ί quasi-standard home country country * ^ i
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