經濟耶智慧財產局員工消費合作社印製 4 2S8 \ 〇 cj. Ο 0 6 Α7 __Β7_ 五、發明說明（/ ) 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種雙閘極介電層的製造方法。 近年來隨著半導體製程技術的進步，其製造成本亦隨 之急速的下降，電子元件朝向多樣化發展等的結果，單一 元件巳無法因應需求。因此，目前半導體製程已逐漸朝向 將邏輯元件與記憶體元件整合在同一晶片上的趨勢，即所 謂的SOC(system on a chip)。但此時仍面臨了一些問題s 當整合邏輯元件與記憶體元件於同一晶片上時，邏輯 元件考慮的重點爲速度，其電晶體所使用的閘氧化層厚度 較薄；而記憶體元件考慮的重點爲可靠性（即高穩定性）， 其電晶體所使用的閘氧化層厚度較厚。因此，通常邏輯元 件係在低電壓下操作，而記憶體元件則在高電壓下操作。 如此，由於考量的方向不同，造成元件在高電壓與低電壓 下的執行結果無法同時令人滿意。尤其是高電壓元件常無 法符合可靠性的要求。 第1A至1C圖繪示習知一種雙閘極介電層的製造流程 剖面圖。 請參照第1A圖，提供一半導體矽基底100,在基底100 上形成淺溝渠隔離結構102，以定義出主動區104與106。 主動區104爲後續欲形成低操作電壓元件之區域，而主動 區丨06爲後續欲形成高操作電壓元件之區域。接著，以熱 氧化法，於基底100上形成一層閘極氧化層108。 請參照第1B圖，形成一光阻110覆蓋欲形成高操作 電壓元件之主動區106。之後，以光阻110爲罩幕，非等 -----------------I--訂 --------I (請先間讀背面之注意事項再填寫本頁) 本紙張尺度適用令國國家標準（CN’S)A.l覘格（2]ϋ X 297公釐） Λ7 _____ Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（> ) 向性蝕刻閘極氧化層108，以去除主動區104基底丨〇〇上 的聞極氧化層108，剩餘在主動區1〇6的氧化層標號爲 108a。 請參照第1 C圖，剝除光阻層110，接著，再進行—熱 氧化步驟，於基底100與氧化層l〇8a上，形成毯覆式的鬧 極氧化層112。最後再進行一回火步驟，以改善閘極氧化 層與1.12的品質。此時，低操作電壓元件主動區ι〇4 的表面形成薄的閘極介電層，而於高操作電壓元件主動區 1⑽形成厚的閘極介電層（包括閘極氧化層1〇8&與lu)。 習知另一種閘極介電層的形成方法，係以化學氣^目& 積法（CVD)形成一具有高介電常數之材料層於基底上，去 除低操作電壓元件區的介電層之後，再以CVD法沈積另 一高介電常數材料層於基底上，而於低操作電壓元件主動 區形成薄的閘極介電層，而於高操作電壓元件主動區形成 厚的鬧極介電層。 然而，利用上述之製造方法所形成的雙閘極介電層， 使得欲形成高操作電壓元件之主動區的閘極介電層有界面 (interface)的存在，而且在形成第二氧化層之前，容易有雜 質粒子掉落於晶片上，造成閘極介電層品質不佳。而當進 行其他的後續製程時，也容易因界面的存在而使厚的閘極 介電層受影響，造成高電壓元件無法符合可靠性的要求， 而使得元件在高電壓與低電壓下的執行結果無法令人滿 意。嚴重時，將導致元件失效。 此外，習知方法採用兩個步驟形成高操作電壓元件區 4 (請先閱讀背面之注意事項再填寫本頁) -^-°Printed by the Economic and Intellectual Property Bureau employee consumer cooperative 4 2S8 \ 〇cj. 〇 0 6 Α7 __Β7_ V. Description of the invention (/) The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a dual-gate dielectric Manufacturing method of electric layer. In recent years, with the advancement of semiconductor process technology, its manufacturing costs have also fallen rapidly, and as a result of the diversified development of electronic components, a single component cannot meet the demand. Therefore, the current semiconductor manufacturing process has gradually moved towards the trend of integrating logic elements and memory elements on the same chip, the so-called SOC (system on a chip). But at this time, there are still some problems. When integrating logic elements and memory elements on the same chip, the main consideration for logic elements is speed. The thickness of the gate oxide layer used by the transistor is thin; The emphasis is on reliability (that is, high stability), and the gate oxide layer used in the transistor is thick. Therefore, usually logic elements operate at low voltages, while memory elements operate at high voltages. In this way, due to different consideration directions, the execution results of the device under high voltage and low voltage cannot be satisfied at the same time. In particular, high-voltage components often fail to meet reliability requirements. 1A to 1C are cross-sectional views showing a conventional manufacturing process of a dual-gate dielectric layer. Referring to FIG. 1A, a semiconductor silicon substrate 100 is provided, and a shallow trench isolation structure 102 is formed on the substrate 100 to define active regions 104 and 106. The active area 104 is an area where a low operating voltage element is to be formed later, and the active area 06 is an area where a high operating voltage element is to be formed subsequently. Next, a gate oxide layer 108 is formed on the substrate 100 by a thermal oxidation method. Referring to FIG. 1B, a photoresist 110 is formed to cover the active region 106 which is to form a high operating voltage element. After that, use the photoresistor 110 as the screen, wait ------ I--order -------- I (please read the back notice first Please fill in this page again for this matter) This paper size applies the national standard (CN'S) AlS grid (2) ϋ X 297 mm) Λ7 _____ Β7 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economy The gate oxide layer 108 is etched to remove the gate oxide layer 108 on the substrate 104 of the active region 104. The remaining oxide layer 108 in the active region 104 is labeled 108a. Referring to FIG. 1C, the photoresist layer 110 is stripped, and then, a thermal oxidation step is performed to form a blanket type oxide oxide layer 112 on the substrate 100 and the oxide layer 108a. Finally, a tempering step is performed to improve the gate oxide and the quality of 1.12. At this time, a thin gate dielectric layer is formed on the surface of the active region of the low operating voltage element ι04, and a thick gate dielectric layer (including the gate oxide layer 108 & With lu). It is known that another method for forming a gate dielectric layer is to form a material layer having a high dielectric constant on a substrate by a chemical gas deposition method (CVD), and remove the dielectric layer of a low operating voltage device region. Then, another high dielectric constant material layer is deposited on the substrate by CVD, and a thin gate dielectric layer is formed on the active region of the low operating voltage element, and a thick anode dielectric is formed on the active region of the high operating voltage element. Electrical layer. However, the dual-gate dielectric layer formed by using the above manufacturing method makes the gate dielectric layer of the active region of the high operating voltage element to have an interface, and before the second oxide layer is formed, It is easy for impurities to fall on the wafer, resulting in poor quality of the gate dielectric layer. When performing other subsequent processes, it is also easy to affect the thick gate dielectric layer due to the existence of the interface, causing the high-voltage components to fail to meet the reliability requirements, which makes the components perform at high and low voltages. The results were unsatisfactory. In severe cases, it will cause component failure. In addition, the conventional method uses two steps to form a high operating voltage element area 4 (Please read the precautions on the back before filling this page)-^-°
T 良 本紙張尺度適用中國國家標準（CNSM.l規格（210 X 297公复> 經濟部智慧財產局員工消費合作社印製 五、發明說明（> ) 的閘極介電層，製程繁瑣複雜。 因此本發明的目的就是在提供一種雙閘極介電層的製 造方法，可得到品質更容易控制，且可靠性更高的雙閘極 介電層。 本發明的另一目的是在提供一種更爲簡易的雙閘極介 電層之製造方法。 本發明的再一目的是在提供一種雙金氧半導體電晶體 製造方法，其可解決上述習知的問題，簡化製程，並提升 元件的可靠性。 根據本發明之上述目的，提出一種雙閘極介電層的製 造方法1其包括提供一包括第一區域與第二區域之基底， 之後選擇性於第一區域的基底上，形成一具有高介電常數 之介電層，之後，進行一熱氧化步驟，於第一區域基底上 形成一氧化層，其中氧化層的厚度大於介電層的厚度。 本發明又提出一種雙金氧半導體電晶體製造方法，其 包括提供一包括第一區域與第二區域之基底，之後，選擇 性於第一區域之基底上，形成一具有高介電常數之介電 層，然後進行一熱氧化步驟，於第一區域基底上形成一氧 化層，其中氧化層的厚度大於介電層的厚度，接著，分別 於第一區域基底上形成第一閘極，於第二區域基底上形成 第二閘極，分別於第一閘極與第二閘極兩旁之基底中，形 成第一輕摻雜區與第二輕摻雜區，其後，分別於第一閘極 與第二閘極側壁上，形成第一間隙壁與第二間隙壁，續分 別於第一間隙壁與第二間隙壁外之基底中形成第一重摻雜 ----------I I. --------"訂--------! (請先閒讀背面之注意事項再填寫本頁) 本纸張&度適用中國因家標阜（CNS)A;規格（210x297公釐） 經濟部智慧財產局員工消費合作社印製 42694 丨 Π7 五、發明說明（+) 區與第二重摻雜區 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下：The paper size of the good paper is in accordance with the Chinese national standard (CNSM.l specification (210 X 297 public comment) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The gate dielectric layer of the invention description (>), the process is complicated and complicated Therefore, the object of the present invention is to provide a method for manufacturing a double-gate dielectric layer, which can obtain a double-gate dielectric layer with easier quality control and higher reliability. Another object of the present invention is to provide a double-gate dielectric layer. A simpler method for manufacturing a double-gate dielectric layer. Another object of the present invention is to provide a method for manufacturing a double metal-oxide semiconductor transistor, which can solve the conventional problems, simplify the manufacturing process, and improve the reliability of the device. According to the above object of the present invention, a method for manufacturing a dual-gate dielectric layer is provided. The method includes providing a substrate including a first region and a second region, and then selectively forming a substrate having the first region on the substrate. A dielectric layer with a high dielectric constant is then subjected to a thermal oxidation step to form an oxide layer on the substrate of the first region, wherein the thickness of the oxide layer is greater than the thickness of the dielectric layer. The invention also proposes a method for manufacturing a double metal oxide semiconductor transistor, which includes providing a substrate including a first region and a second region, and then selectively forming a dielectric with a high dielectric constant on the substrate of the first region. Layer, and then performing a thermal oxidation step to form an oxide layer on the substrate of the first region, wherein the thickness of the oxide layer is greater than the thickness of the dielectric layer, and then forming a first gate electrode on the substrate of the first region, and A second gate is formed on the region substrate, and a first lightly doped region and a second lightly doped region are formed in the substrates on both sides of the first gate and the second gate, respectively, and thereafter, the first gate and the second gate are formed respectively. A first gap wall and a second gap wall are formed on the side wall of the second gate, and a first heavy doping is formed in the substrate outside the first gap wall and the second gap wall, respectively. I I. -------- " Order --------! (Please read the precautions on the back before filling out this page) This paper & degree is applicable to China's family standard ( CNS) A; Specifications (210x297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 42694 丨 Π7 (+) Region and the second heavily doped region In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings for detailed description. as follows:
圖式之簡單說明Z 第1A至1C圖繪示習知一種雙閘極介電層的製造流程 剖面圖， 第2A至2D圖繪示依照本發明較佳實施例之一種雙閘 極介電層的製造流程剖面圖；以及 第3A至3C圖繪示依照本發明較佳實施例之一種雙金 氧半導體電晶體的製造流程剖面圖。 圖式之標記說明： 10〇、200 :基底 102 :淺溝渠隔離結構 104、106、204、206 :主動區 108、108a、112、212 :氧化層 H0、210 :光阻 202 :元件隔離結構 208、208a :介電層 214、216 :聞極 218、220 :輕摻雜區 222、224 :重摻雜區 第一實施例 第2A至2D圖繪示依照本發明較佳實施例之一種雙閘 6 ------------^ 裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度滷用1P國囡家標準（CNSMl規恪（2丨(J X四7公S ) A7 B7 42694 1 五、發明說明（艾） 極介電層的製造流程剖面圖。 請參照第2A圖，首先’提供一基底200，其較佳的爲 具有p型摻雜之<100>矽基底°接著’在基底200上形成 元件隔離結構202 ’定義出主動區204與206。主動區204 爲後續欲形成低操作電壓元件之區域，而主動區206爲後 續欲形成高操作電壓元件之區域°元件隔離結構2〇2例如 爲場氧化層或淺溝渠隔離結構。之後’於基底200中形成 井區（未顯示），其電性係根據所欲形成的電晶體電性來決 定。 請參照第2B圖’於基底200上，形成一具有高介電 常數之薄的介電層208’用以作爲低操作電壓元件之閘極 介電層。高介電常數之介電層208的材質例如爲氮氧化矽 (SiON)、氮化矽（SiN)、五氧化二鉬(Ta2〇5)、與氧化鈦(Ti02)， 其形成方法例如使用化學氣相沈積法。以〇,18μιη的半導 體製程爲例，薄介電層208的厚度約爲30埃。介電層208 採用高介電常數的介電材料，其具有較高抗崩潰能力的優 點。 請參照第2C圖’以微影蝕刻方法，選擇性去除欲形 成高操作電壓元件之主動區206之介電層208。其去除方 法例如包括形成一光阻2〗〇,覆蓋後續欲形成低操作電壓 元件之主動區204，接著，以光阻210爲罩幕，非等向性 蝕刻介電層208，去除主動區206表面之介電層208，暴露 出高電壓元件主動區2〇6之基底200。此時，剩餘的介電 層208a仍覆蓋於低操作電壓元件主動區2〇4之基底2〇〇 U氏中關家標準（CNS)A丨規格观公衫） ------------^ 裝 *-------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作枝印製 經濟部智慧財產局員工消費合作社印*,J^Brief description of the drawings Z. FIGS. 1A to 1C are cross-sectional views showing a conventional manufacturing process of a dual-gate dielectric layer. FIGS. 2A to 2D show a dual-gate dielectric layer according to a preferred embodiment of the present invention. And FIGS. 3A to 3C are cross-sectional views illustrating a manufacturing process of a dual metal-oxide-semiconductor transistor according to a preferred embodiment of the present invention. Description of the drawing symbols: 100, 200: substrate 102: shallow trench isolation structure 104, 106, 204, 206: active area 108, 108a, 112, 212: oxide layer H0, 210: photoresist 202: element isolation structure 208 , 208a: dielectric layers 214, 216: smell poles 218, 220: lightly doped regions 222, 224: heavily doped regions 2A to 2D of the first embodiment show a double gate according to a preferred embodiment of the present invention 6 ------------ ^ Loading -------- Order --------- Line (Please read the precautions on the back before filling this page) This paper size 1P National Standard for Halogens (CNSM1 Regulations (2 丨 (JX 4 7 S)) A7 B7 42694 1 V. Description of the Invention (Ai) Cross-sectional view of the manufacturing process of the polar dielectric layer. Please refer to Figure 2A, first ' A substrate 200 is provided, which is preferably a < 100 > silicon substrate with p-type doping followed by 'forming an element isolation structure 202 on the substrate 200' to define active regions 204 and 206. The active region 204 is to be formed subsequently The region of the low operating voltage element, and the active region 206 is a region where a high operating voltage element is to be formed later. The element isolation structure 202 is, for example, a field oxide layer or a shallow trench isolation structure. 'The formation of a well region (not shown) in the substrate 200 is determined by the electrical properties of the transistor to be formed. Please refer to FIG. 2B' on the substrate 200 to form a thin, high dielectric constant The dielectric layer 208 'is used as a gate dielectric layer of a low operating voltage element. The material of the high dielectric constant dielectric layer 208 is, for example, silicon oxynitride (SiON), silicon nitride (SiN), and molybdenum pentoxide (Ta205) and titanium oxide (Ti02), for example, a chemical vapor deposition method is used. Taking a semiconductor process of 0.18 μm as an example, the thickness of the thin dielectric layer 208 is about 30 angstroms. The use of a high dielectric constant dielectric material has the advantage of higher resistance to collapse. Please refer to FIG. 2C ', using a lithographic etching method, to selectively remove the dielectric layer 208 of the active region 206 where a high operating voltage element is to be formed. The removal method includes, for example, forming a photoresist 2 to cover the active area 204 of a subsequent low-operation voltage element, and then, using the photoresist 210 as a mask, the dielectric layer 208 is anisotropically etched to remove the active area. Dielectric layer 208 on the surface of 206, exposing high voltage components active Substrate 200 in area 206. At this time, the remaining dielectric layer 208a still covers the substrate of the low operating voltage element active area 208 in 2000U's Zhongguanjia Standard (CNS) A specifications specifications. ------------ ^ Install * ------- Order --------- (Please read the notes on the back before filling this page) Intellectual Property Bureau of the Ministry of Economic Affairs Employee Consumption Cooperation Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumption Cooperatives *, J ^
4 2 694 I 49U 丨 \\ i (iOi) 五、發明說明（6 ) 上c 請參照第2D圖，去除光阻210後，進行一熱氧化 (thermal oxidation)步驟，於欲形成高操作電壓元件之基底 200上形成一熱氧化層212，其中熱氧化層212的厚度大於 介電層208a。以0.1 8μπι的半導體製程爲例，熱氧化層212 的厚度約爲60-70埃。由於具有高介電常數之介電層208a 覆蓋欲形成低操作電壓元件之主動區204，在形成熱氧化 層212時，具有高介電常數之介電層208a將禁制氧氣進入， 而避免低操作電壓元件主動區204基底發生氧化，使具有 高介電常數之介電層208a的厚度保持一定，不會發生變 化。因此，只有暴露出的高操作電壓元件主動區206之基 底200發生氧化，而形成熱氧化層212。至此，具有高介 電常數且較薄的介電層208a係作爲低操作電壓元件主動 區204之閘極介電層，而較厚的熱氧化層212係作爲高操 作電壓元件主動區206之閘極介電層。 本發明以熱氧化法，於高操作電壓元件主動區206基 底20Q上形成熱氧化層212，氧化層212係以一個步驟形 成，不僅製程簡單，而且避免習知利用兩個步驟形成高操 作電壓元件主動區206之閘極介電層，致使厚的閘極介電 層中產生界面（interface)，藉以避免因界面所造成的可靠性 (re丨lability)的問題。如此，即可提升厚的閘極介電層的品 質（quality)。此外，又因本發明厚的聞極介電層無介面的 存在，便無需進行另一回火步驟以改善厚的閘極介電層的 品質，使整個製程更爲簡易。 ------------裝—-----訂-------!線 {請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS),\.l規格（2]ϋ X四7公釐） 經濟部智慧財產局員工消費合作社印製 五、發明說明（/)) 第二實施例 第3A至3C圖繪示依照本發明較佳實施例之一種雙金 氧半導體電晶體的製造流程剖面圖。 請參照第3A圖，提供第2D圖之具有薄的閘極介電層 208a與厚的閘極介電層212的半導體基底200，此薄的閘 極介電層208^1與厚的閘極介電層212係以第一較佳實施例 之方法所形成，由於其形成方法已詳細地揭露於第一較佳 實施例中，在此便省略其說明。第3Α至3C圖標號與第2Α 至2D圖標號相同者，代表具有相同之材質或相同之區域》 請繼續參照第3Α圖，分別於低操作電壓元件主動區 204(即具有較薄之閘極介電層208a的區域）之基底200上 形成一閘極214,而於高操作電壓元件主動區206(即具有 較厚之閘極介電層212的區域）之基底200上形成一閘極 216。其形成方法例如包括於基底200上形成一複晶矽層’ 續定義此複晶矽層，以分別於閘極介電層208a與216上形 成複晶砂閘極214與216。 請參照第3B圖，分別於閘極214與216兩旁之基底2〇〇 中，形成輕摻雜區218與220。其形成方法包括例如使用 一光阻（未繪示）覆蓋其中之一主動區，接著’以暴露出的 主動區的閘極爲罩幕，進行離子植入法而形成輕摻雜區’ 其摻質的電性端看所需形成電晶體的電性來決定。剝除上 述光阻後，再以另一光阻覆蓋另一主動區，以相同方法而 形成另一輕摻雜區。 請參照第3C圖，分別於該閘極214與216側壁上’ y 本紙張尺度適用中國國家標準（CNS)A丨規格（210 X 297公釐） -----：---------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制衣 2¾4 7 4 4 'Ί1- tl。。/ |丨()6 五、發明說明（沴） 形成間隙壁218與220。之後，亦以相同於輕摻雜汲極的 形成方法，分別於間隙壁218與220外之基底200中形成 重摻雜區222與224。如此，完成了雙金氧半導體電晶體 的製作。 本發明之雙金氧半導體電晶體分別以具有高介電常數 之介電層及氧化矽作爲閘極介電層的材質，而且高操作電 壓元件區厚的閘極介電層係以熱氧化法一個步驟形成，不 會造成厚的閘極介電層中有界面存在，提升厚的閘極介電 層的品質’進而增加元件的可靠性。而薄的閘極介電層使 用具有高介電常數的介電材料1亦可增加其抗電崩潰 (breakdown)的能力。此外，由於本發明厚的閘極介電層僅 需以一個熱氧化步驟形成，沒有界面的存在，便無需進行 另一回火步驟以改善厚的閘極介電層的品質，使整個製程 更爲簡易。 在此實施例中，係以雙金氧半導體電晶體爲例，然本 發明並不限於此’其他如嵌入式快閃記憶體(embedded flash memory)'嵌入式動態隨機存取記憶體(embedded DRAM)及 欺入式靜態隨機存取記憶體（embedded SR AM)等的閘極介 電層，均可適用於本發明。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 I ϋ 本紙張&度適用中國國家標準（CNS)Ai規格（210 ycj7公釐） ------------裝--------訂---------I (請先閱讀背面之注意事項再填寫本頁>4 2 694 I 49U 丨 \\ i (iOi) 5. Description of the invention (6) Please refer to Figure 2D. After removing the photoresist 210, perform a thermal oxidation step to form a high operating voltage element. A thermal oxide layer 212 is formed on the substrate 200. The thickness of the thermal oxide layer 212 is greater than that of the dielectric layer 208a. Taking a semiconductor process of 0.1 8 μm as an example, the thickness of the thermal oxide layer 212 is about 60-70 angstroms. Since the dielectric layer 208a with a high dielectric constant covers the active region 204 of the element to be formed with a low operating voltage, when the thermal oxide layer 212 is formed, the dielectric layer 208a with a high dielectric constant will inhibit oxygen from entering and avoid low operation. The substrate of the voltage element active region 204 is oxidized, so that the thickness of the dielectric layer 208a having a high dielectric constant is kept constant and does not change. Therefore, only the exposed substrate 200 of the high operating voltage element active region 206 is oxidized to form a thermal oxide layer 212. So far, the thinner dielectric layer 208a having a high dielectric constant is used as the gate dielectric layer of the active region 204 for the low operating voltage element, and the thicker thermal oxide layer 212 is used as the gate of the active region 206 for the high operating voltage element Polar dielectric layer. In the present invention, a thermal oxidation method is used to form a thermal oxide layer 212 on the substrate 20Q of the active region 206 of the high operating voltage element. The oxide layer 212 is formed in one step. The gate dielectric layer of the active region 206 causes an interface to be generated in the thick gate dielectric layer, so as to avoid reliability problems caused by the interface. In this way, the quality of the thick gate dielectric layer can be improved. In addition, since the thick smelling dielectric layer of the present invention has no interface, there is no need to perform another tempering step to improve the quality of the thick gate dielectric layer, making the whole process easier. ------------ Installation ------- Order -------! Line {Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards ( CNS), \ .l Specifications (2) ϋ X 47 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (/)) Figures 3A to 3C of the second embodiment A cross-sectional view of a manufacturing process of a double metal-oxide semiconductor transistor in a preferred embodiment. Referring to FIG. 3A, a semiconductor substrate 200 having a thin gate dielectric layer 208a and a thick gate dielectric layer 212 is provided in FIG. 2D. The thin gate dielectric layer 208 ^ 1 and the thick gate The dielectric layer 212 is formed by the method of the first preferred embodiment. Since the method of forming the dielectric layer 212 has been disclosed in detail in the first preferred embodiment, its description is omitted here. The 3A to 3C icon numbers are the same as the 2A to 2D icon numbers, which means that they have the same material or the same area. Please continue to refer to Figure 3A in the active area of the low operating voltage element 204 (that is, have a thinner gate) A gate 214 is formed on the substrate 200 in the region of the dielectric layer 208a), and a gate 216 is formed on the substrate 200 in the active region 206 of the high operating voltage element (that is, a region having a thicker gate dielectric layer 212). . The formation method includes, for example, forming a polycrystalline silicon layer on the substrate 200. The polycrystalline silicon layer is further defined to form polycrystalline sand gates 214 and 216 on the gate dielectric layers 208a and 216, respectively. Referring to FIG. 3B, lightly doped regions 218 and 220 are formed in the substrate 200 on both sides of the gate electrodes 214 and 216, respectively. The formation method includes, for example, covering one of the active regions with a photoresist (not shown), and then 'lightly doped regions are formed by performing ion implantation with a gate electrode of the exposed active regions' and its dopants The electrical end depends on the electrical properties required to form the transistor. After stripping the photoresist, another active region is covered with another photoresist, and another lightly doped region is formed in the same way. Please refer to Figure 3C, on the side walls of the gates 214 and 216, respectively. Y This paper size applies Chinese National Standard (CNS) A 丨 specifications (210 X 297 mm) -----: ------ --------- Order --------- line (please read the precautions on the back before filling this page) Printed clothing by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2¾4 7 4 4 'Ί1 -tl. . / | 丨 () 6 V. Description of the invention (沴) Form the partition walls 218 and 220. After that, heavily doped regions 222 and 224 are formed in the substrate 200 outside the spacers 218 and 220, respectively, by the same method of forming the lightly doped drain. In this way, the fabrication of the double metal oxide semiconductor transistor is completed. The double metal oxide semiconductor transistor of the present invention uses a dielectric layer with high dielectric constant and silicon oxide as the material of the gate dielectric layer, and the gate dielectric layer with a high operating voltage element region thickness is thermally oxidized. Forming in one step will not cause an interface to exist in the thick gate dielectric layer, and improve the quality of the thick gate dielectric layer, thereby increasing the reliability of the device. The use of a dielectric material 1 having a high dielectric constant for a thin gate dielectric layer can also increase its ability to resist electrical breakdown. In addition, since the thick gate dielectric layer of the present invention only needs to be formed in one thermal oxidation step, and there is no interface, there is no need to perform another tempering step to improve the quality of the thick gate dielectric layer and make the whole process more For simplicity. In this embodiment, a double metal oxide semiconductor transistor is used as an example, but the present invention is not limited to this 'others such as embedded flash memory' embedded dynamic random access memory (embedded DRAM) ), And gate dielectric layers such as embedded static random access memory (embedded SR AM) can be applied to the present invention. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. I ϋ This paper & degree applies Chinese National Standard (CNS) Ai specification (210 ycj7 mm) ------------ installation -------- order -------- --- I (Please read the notes on the back before filling in this page>