/ / 經濟部智慧財產局員工消費合作社印製 4 3 91 087 A7 57S2twf,doc/0〇8 β7 五、發明説明（| ) 本發明是有關於一種半導體元件的製造方法’且特別 是有關於一種具有雙重閘極氧化物層（dual gate oxide)的 製造方法。 在目前的半導體元件中，嵌入式動態隨機存取記憶體 (embedded DRAM)由於係將邏輯電路區（logic circuit)與動 態隨機存取記憶體區（DRAM)建構在同—晶片上’可具有 較佳的操作效能之故’已逐漸發展成半導體領域中頗爲重 要的技術。 邏輯電路區與動態隨機存取記憶體區對於製程的要求 不盡相同，例如，由於其上形成元件的需求，動態隨機存 取記億體區的閘極氧化層往往需較邏輯電路區爲厚，因此 使得嵌入式動態隨機存取記憶體的製程較爲複雜。 第1A-1B圖所示爲一種具有雙重閘極氧化層的製造流 程剖面圖。請參照第1圖’在一基底100上形成隔離結構 102以定義記憶體區104以及邏輯電路區106 ’其中記憶 體區104係用以形成動態隨機存取記憶體，而邏輯電路區 106係用以形成邏輯電路。接著’在基底上形成一第 一閘極氧化物層108,覆蓋記憶體區1〇4與邏輯電路區 106,續在邏輯電路區106上形成一氮化砂層110’利用氮 化矽層110爲罩幕，去除記憶體區1〇1 2的第一閘極氧化物 層，如第1A圖所示。 之後，在氮化矽層丨10的覆蓋下’而在記憶體區104 形成一第二閘極氧化物層112’其中第二閘極氧化物層U2 可具有較第一閘極氧化物層108爲厚的厚度，如第1B圖 (請先閲讀背面之注意事項再填寫本頁) 訂 1 — 2 本紙張適用中國國( CNS ) A视^ ( 21〇><297公釐] " ' 4 j t 5 8? 43 91 58 A7// Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 3 91 087 A7 57S2twf, doc / 0〇8 β7 V. Description of the Invention (|) The present invention relates to a method for manufacturing a semiconductor element, and in particular to A method for manufacturing a dual gate oxide layer. In the current semiconductor devices, the embedded dynamic random access memory (embedded DRAM), because the logic circuit area and the dynamic random access memory area (DRAM) are constructed on the same chip, can The reason for better operation efficiency has gradually developed into a very important technology in the semiconductor field. The logic circuit area and the dynamic random access memory area have different requirements for the manufacturing process. For example, due to the requirements of forming components thereon, the gate oxide layer of the dynamic random access memory area often needs to be thicker than the logic circuit area. Therefore, the manufacturing process of the embedded dynamic random access memory is more complicated. Figures 1A-1B are cross-sectional views of a manufacturing process with a double gate oxide layer. Please refer to FIG. 1 'forming an isolation structure 102 on a substrate 100 to define a memory area 104 and a logic circuit area 106', where the memory area 104 is used to form a dynamic random access memory, and the logic circuit area 106 is used To form a logic circuit. Then 'form a first gate oxide layer 108 on the substrate, covering the memory region 104 and the logic circuit region 106, and continue to form a nitride nitride layer 110 on the logic circuit region 106' using the silicon nitride layer 110 as The mask is used to remove the first gate oxide layer of the memory region 102, as shown in FIG. 1A. Afterwards, a second gate oxide layer 112 is formed in the memory region 104 under the cover of the silicon nitride layer 10 ′, wherein the second gate oxide layer U2 may have a higher value than the first gate oxide layer 108. For thick thickness, as shown in Figure 1B (please read the precautions on the back before filling this page) Order 1-2 This paper is applicable to China (CNS) A view ^ (21〇 > < 297mm] " '4 jt 5 8? 43 91 58 A7
5782twf.doc/00S 五、發明説明（> ) (請先閱讀背面之注意事項再填寫本頁) 所示。亦即，利用上述之製程可在同一晶片上形成具有不 同厚度之閘極氧化物層。隨後，再進行形成閘極以及電容 器等相關製程。 上述形成不同厚度的閘極氧化物層108、112的製程步 驟較多，使得記憶體區104與與邏輯電路區106製程的整 合上更胗複雜。 此外，由於閘極（未繪出）係利用電漿蝕刻進行，且電 漿蝕刻係一種高能的離子轟擊，因此在蝕刻閘極時，容易 連帶地破壞閘極氧化物層108、112，造成閘極氧化物層 108、112的電性品質不佳，甚而影響閘極氧化物層108、 112厚度的均勻度，而導致產品良率降低。 有鑑於此，本發明就是在提供一種具有雙重閘極氧化 物層的半導體元件的製造方法，除了提供較爲簡易的製程 步驟外，更可兼具閘極氧化物層的品質以及均勻度等問 題。 經濟部智慧財產局員工消費合作社印製 本發明提供一種具有雙重閘極氧化物層厚度之半導體 元件的製造方法，在具有一第一主動區與一第二主動區的 基底上分別彤成一第一閘極以及一第二閘極，其中第一閘 極與第二閘極以一第一閘極氧化物層與基底隔開。之後， 在第一閘極與第二閘極上覆蓋一第一絕緣材料與一第二 絕緣材料，再將第一絕緣材料去除，而使第一閘極之側壁 暴露出。之後，再進行一氧化步驟，利用一熱製程使氧氣 擴散進入第一閘極下方的第一閘極氧化物層與閘極介面 而使閘極氧化物層變厚。 4 - 本紙張尺度適用中國國家標準（CNS ) A4規格（2I0X297公釐） 3 91 58 , A7 5782twf.doc/008 D / 五、發明説明（g ) (請先聞讀背面之注意事項再填寫本頁) 本發明再提供一種具有雙重閘極氧化物層厚度之半導 體元件的製造方法，在具有一第一主動區與一第二主動區 的基底上分別形成一第一閘極以及一第二閘極，其中第一 閘極與第二閘極以一第一閘極氧化物層與基底隔開。之 後，在基底上形成一毯覆式絕緣材料，再將位於第一主動 區的毯覆式絕緣材料去除，而使第一閘極之側壁暴露出。 之後，再進行一氧化步驟，利用一熱製程使氧氣擴散進入 第一閘極下方的第一閘極氧化物層與閘極介面而使閘極 氧化物層變厚。 本發明係在第二閘極側壁上覆蓋絕緣材料，而暴露出 第一閘極側壁，而在進行氧化製程時，氧氣可在高溫下擴 散進入第一閘極下方而加厚閘極氧化物層。由於第二閘極 側壁上有絕緣材料覆蓋，因此可阻擋氧氣的擴散，故第二 閘極下的閘極氧化物層不致變厚。因此藉由上述之製程， 可在同一晶片上提供具有不同厚度之閘極氧化物層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 經濟部智慧財產局員工消費合作社印製 圖式之簡單說明： 第1A-1B圖係顯示一種雙重閘極氧化物層的製造流程 剖面圖； 第2A-2D圖係顯示根據本發明一第一較佳實施例具有 雙重閘極氧化物層之半導體元件之製造流程剖面圖；以及 第3A-3C圖係顯示根據本發明一第二較佳實施例具有 5 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210><297公釐） 4 3 91 5 8 * j A7 B7 i 57 82twf. doc/008 五、發明説明（v〇 雙重閘極氧化物層之半導體元件之製造流程剖面圖。 其中，各圖標號之簡單說明如下： (請先閱讀背面之注意事項再填寫本頁} 100、200 :基底 102、202 :隔離結構 108、208、208a、112 :閘極氧化物層 110、216 :氮化矽層 204a、204b :第一主動區、第二主動區 206 :井區 210 :導電層 212/214 :複晶矽層/矽化鎢 218a、218b :第一聞極、第二閘極 220、220a、220b :絕緣材料 222、222a :光阻 224 :氧化物層 實施例 經濟部智慧財產局員工消費合作社印製 在積體電路高積集度與高效能的要求下，近來已逐漸 發展出將原本在不同晶片上的電路整合在同一晶片上之 半導體製程。然而，基於元件對於傳輸速度或是可靠度 (reliability)等不同的需求，各種電路所需的製程條件亦不 盡相同，其中之一即爲不同的主動區需要不同厚度的閘極 氧化物層。 因此本發明之較佳實施例係提供在同一晶片上形成不 同厚度的閘極氧化物層的製造方法，其係在具有一第一主 動區與一第二主動區的基底上分別形成閘極後，在第二主 6 - 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） ί 4 3 9 ί 5 8 j 广， 5782twf.doc/008 五、發明説明（t) 動區閘極的側壁上覆蓋一薄絕緣材料，而使第一主動區的 閘極暴露在氧氣的環境中，之後進行氧化步驟，使環境中 的氧擴散進入第一主動區的閘極與閘極氧化物層介面，而 與閘極中的複晶矽層反應，加厚第一主動區閘極氧化物層 的厚度。其中’由於第二主動區的閘極覆蓋有絕緣材料阻 隔氧氣的擴散，因此第二主動區閘極氧化物層的厚度不致 改變，故在同一晶片上，可在第一主動區與第二主動區提 供具有不同厚度之閘極氧化物層。 第一較佳實施例 第2A-2D圖所示，爲根據本發明一第一較佳實施例具 有雙重閘極氧化物層的半導體元件之製造流程剖面圖。請 參照第2A圖’在一基底200上形成隔離結構202以定義 出一第一主動區204a以及一第二主動區204b。其中，基 底200例如爲矽等之半導體材質，隔離結構200例如爲淺 溝渠隔離結構（shallow trench isolation, STI)。第一主動區 204a例如爲形成動態隨機存取記憶體之記憶體區，而第二 主動區204b則爲形成邏輯電路之邏輯電路區，將動態隨 機存取記憶體與邏輯電路整合在同一晶片上而構成所謂 的嵌入式動態隨機存取記憶體。 請參照第2A圖，接著，在基底200中進行通道植入 (channel implant)或井區（well)等習知製程。之後’在基底 200上形成一閘極氧化物層208，覆蓋第一主動區204a與 第二主動區204b的基底200。閘極氧化物層208例如以熱 氧化法形成，而當製程線寬爲〇.25μιη時’閘極氧化物層 7 — (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐} 經濟部智慧財產局員工消费合作社印製 u 58> 43 9t 58、 δ 7 5782tWf.d〇C/〇°8 _B7__ 五、發明説明（l ) 208厚度約爲55埃左右。續在閘極氧化物層2〇8上形成— 導電層210，導電層210覆蓋在閘極氧化物層208上，例 如以化學氣相沉積法形成摻雜複晶矽（doped poly)或摻雜 複晶矽212/矽化鎢214等導電材料，其中複晶矽212之厚 度約在800-1000埃左右，矽化鎢厚度約爲550_75〇埃 .左右。之後，在導電層210上形成一厚度約爲2000埃左 右的氮化矽層216，例如以化學氣相沉積法形成。 接著，利用微影蝕刻法定義氮化矽層216與導電層 210,而分別在第一主動區204a與第二主動區204b形成一 第一閘極218a與一第二閘極2i8b，如第2A圖所示。之後， 在基底200上形成一與底下結構共形沉積的毯覆式絕緣材 料22〇 ’覆蓋第一閘極218a與第二閘極218b，此毯覆式絕 緣材料220的厚度相當薄，例如以化學氣相沉積法形成厚 度約爲40-100埃左右的TEOS氧化物層。 之後’對毯覆式絕緣材料22〇進行回蝕刻（etch back) 的步驟’例如利用反應性離子蝕刻（RIE)，而將氮化矽層 216上以及閘極氧化物層208表面的絕緣材料220去除， 留下薄薄的絕緣材料22〇a覆蓋在第一閘極218a與第二閘 極218b的側壁上，如第2B圖所示。其中，由於絕緣材料 220a的厚度夠薄，因此其覆蓋在第一閘極218a與第二閘 極218b側壁上並不會影響後續製程中淡摻雜離子植入 (LDD)的形成。 請參照第2C圖，之後，在第二主動區2〇41?上覆蓋一 光阻222 ’光阻222係利用微影定義’而接著在光阻222 8 < 本紙張尺度適用tii]*料（CNS ) ( 210X297公釐） " -- (請先閲讀背面之注意事項再填窝本頁)5782twf.doc / 00S V. Description of the invention (>) (Please read the precautions on the back before filling this page). That is, gate oxide layers having different thicknesses can be formed on the same wafer by using the above-mentioned processes. Subsequently, related processes such as forming a gate and a capacitor are performed. The above steps for forming the gate oxide layers 108 and 112 with different thicknesses make the integration of the process of the memory region 104 and the logic circuit region 106 more complicated. In addition, since the gate (not shown) is performed by plasma etching, and plasma etching is a high-energy ion bombardment, when the gate is etched, it is easy to damage the gate oxide layers 108 and 112 together and cause the gate The electrical quality of the electrode oxide layers 108 and 112 is not good, and even affects the thickness uniformity of the gate oxide layers 108 and 112, which results in a decrease in product yield. In view of this, the present invention is to provide a method for manufacturing a semiconductor device having a dual gate oxide layer. In addition to providing a relatively simple process step, it can also have the quality and uniformity of the gate oxide layer. . Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics The present invention provides a method for manufacturing a semiconductor device having a thickness of a double gate oxide layer, forming a first on a substrate having a first active region and a second active region, respectively. The gate and a second gate, wherein the first gate and the second gate are separated from the substrate by a first gate oxide layer. After that, the first gate electrode and the second gate electrode are covered with a first insulating material and a second insulating material, and then the first insulating material is removed to expose the sidewall of the first gate electrode. Then, an oxidation step is performed, and a thermal process is used to diffuse oxygen into the first gate oxide layer and the gate interface below the first gate to make the gate oxide layer thicker. 4-This paper size applies Chinese National Standard (CNS) A4 specification (2I0X297 mm) 3 91 58, A7 5782twf.doc / 008 D / V. Description of invention (g) (Please read the precautions on the back before filling in this The present invention further provides a method for manufacturing a semiconductor device having a double gate oxide layer thickness. A first gate and a second gate are respectively formed on a substrate having a first active region and a second active region. Electrode, wherein the first gate and the second gate are separated from the substrate by a first gate oxide layer. After that, a blanket-type insulating material is formed on the substrate, and the blanket-type insulating material located in the first active region is removed, so that the sidewall of the first gate electrode is exposed. Then, an oxidation step is performed, and a thermal process is used to diffuse oxygen into the first gate oxide layer and the gate interface below the first gate to make the gate oxide layer thicker. In the present invention, the second gate sidewall is covered with an insulating material to expose the first gate sidewall. During the oxidation process, oxygen can diffuse under the first gate at a high temperature to thicken the gate oxide layer. . Since the sidewall of the second gate is covered with an insulating material, it can block the diffusion of oxygen, so the gate oxide layer under the second gate does not become thick. Therefore, by the above process, gate oxide layers having different thicknesses can be provided on the same wafer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in conjunction with the accompanying drawings and described in detail as follows: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Brief description of the drawings: Figures 1A-1B are cross-sectional views showing a manufacturing process of a double gate oxide layer; Figures 2A-2D are views showing a dual gate oxide layer according to a first preferred embodiment of the present invention A cross-sectional view of a semiconductor device manufacturing process; and FIGS. 3A-3C show that according to a second preferred embodiment of the present invention, the paper size is 5-this paper size applies to the Chinese National Standard (CNS) A4 specification (210 > < 297 mm). ) 4 3 91 5 8 * j A7 B7 i 57 82twf. Doc / 008 V. Description of the invention (v〇 Cross-section view of the manufacturing process of a semiconductor device with a double gate oxide layer. Among them, a brief description of each icon number is as follows: ( Please read the notes on the back before filling in this page} 100, 200: Substrate 102, 202: Isolation structure 108, 208, 208a, 112: Gate oxide layer 110, 216: Silicon nitride layer 204a, 204b: First Active zone, second active 206: Well area 210: Conductive layer 212/214: Polycrystalline silicon layer / Tungsten silicide 218a, 218b: First smell electrode, second gate electrode 220, 220a, 220b: Insulating material 222, 222a: Photoresistor 224: Oxide Under the requirements of high integration and high efficiency of integrated circuits, employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs have recently developed semiconductor processes that integrate circuits originally on different chips on the same chip. However, based on different requirements of components for transmission speed or reliability, the process conditions required for various circuits are also different. One of them is that different active regions require gate oxide layers of different thicknesses. Therefore, a preferred embodiment of the present invention provides a method for manufacturing gate oxide layers having different thicknesses on the same wafer, which are formed after forming gates on a substrate having a first active region and a second active region, respectively. In the second main 6-this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ί 4 3 9 ί 5 8 j wide, 5782twf.doc / 008 5. Description of the invention (t) Gates in the moving zone of The wall is covered with a thin insulating material, and the gate of the first active region is exposed to the environment of oxygen, and then an oxidation step is performed to diffuse the oxygen in the environment into the gate and gate oxide layer interface of the first active region. In response to the polycrystalline silicon layer in the gate, the thickness of the gate oxide layer in the first active region is thickened. 'Because the gate of the second active region is covered with an insulating material to block the diffusion of oxygen, the second active region The thickness of the region gate oxide layer does not change. Therefore, on the same wafer, gate oxide layers having different thicknesses can be provided in the first active region and the second active region. First Preferred Embodiment Figures 2A-2D are cross-sectional views showing a manufacturing process of a semiconductor device having a dual gate oxide layer according to a first preferred embodiment of the present invention. Referring to FIG. 2A ', an isolation structure 202 is formed on a substrate 200 to define a first active region 204a and a second active region 204b. The substrate 200 is, for example, a semiconductor material such as silicon, and the isolation structure 200 is, for example, a shallow trench isolation structure (STI). The first active area 204a is, for example, a memory area forming a dynamic random access memory, and the second active area 204b is a logic circuit area forming a logical circuit. The dynamic random access memory and the logic circuit are integrated on the same chip. The so-called embedded dynamic random access memory is formed. Referring to FIG. 2A, a conventional process such as channel implant or well is performed in the substrate 200. After that, a gate oxide layer 208 is formed on the substrate 200 to cover the substrate 200 of the first active region 204a and the second active region 204b. The gate oxide layer 208 is formed by, for example, a thermal oxidation method, and when the process line width is 0.25 μm, the gate oxide layer 7 — (Please read the precautions on the back before filling this page) Order the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size printed by the employee consumer cooperative is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economy u 58 > 43 9t 58, δ 7 5782tWf.d〇C / 〇 ° 8 _B7__ 5. Description of the invention (l) The thickness of 208 is about 55 Angstroms. Continued to be formed on the gate oxide layer 208-a conductive layer 210, which is covered on the gate oxide layer 208, for example, with chemical gas Conductive materials such as doped poly or doped polycrystalline silicon 212 / tungsten silicide 214 are formed by phase deposition. The thickness of the polycrystalline silicon 212 is about 800-1000 angstroms, and the thickness of tungsten silicide is about 550_75. After that, a silicon nitride layer 216 with a thickness of about 2000 angstroms is formed on the conductive layer 210, for example, by a chemical vapor deposition method. Next, a lithographic etching method is used to define the silicon nitride layer 216 and the conductive layer. Layer 210, while in the first active area 204a A first gate 218a and a second gate 2i8b are formed with the second active region 204b, as shown in FIG. 2A. Thereafter, a blanket-type insulating material 22 is formed on the substrate 200 conformally deposited with the underlying structure. 'Covering the first gate electrode 218a and the second gate electrode 218b, the blanket insulation material 220 is relatively thin, for example, a TEOS oxide layer having a thickness of about 40-100 angstroms is formed by a chemical vapor deposition method.' The step of performing an etch back on the blanket insulating material 22 ′ is, for example, using reactive ion etching (RIE) to remove the insulating material 220 on the silicon nitride layer 216 and the surface of the gate oxide layer 208. The thin insulating material 22a is left to cover the sidewalls of the first gate electrode 218a and the second gate electrode 218b, as shown in FIG. 2B. Among them, because the thickness of the insulating material 220a is thin enough, it is covered in the first The gates of one gate 218a and the second gate 218b do not affect the formation of lightly doped ion implantation (LDD) in subsequent processes. Please refer to FIG. 2C, and then cover the second active region 2041? A photoresist 222 'Photoresist 222 is defined by lithography' Resistance 222 8 < This paper size is suitable for tii] * material (CNS) (210X297 mm) "-(Please read the precautions on the back before filling this page)
、發明説明（η ^391 5 8 »-,Description of the invention (η ^ 391 5 8 »-,
N 5782tWfd〇c/〇〇g ΑΊ B7 五 的®棻下，去除第一主動區川乜第—閘極218a側壁的絕 緣材料220a，例如以濕触刻法去除，而使第—閘極 側嬖暴露出。續再將光阻222剝除。 請參照第2D圖，在將光阻222去除後，接著進行—氧 化歩驟，氧化步驟係利用溫度約爲85〇-1〇85。<：的熱製程， 氧化層厚度控制在4〇〜1 〇〇A左右’使環境中的氧氣因加溫 擴散進入複晶矽層2U與閘極氧化物層2〇8介面，而氧化 複晶矽層212,使閘極氧化物層208變厚成如第2D圖所示 之閘極氧化物層208a，而在第二主動區2(Mb第二閘極2l8b 的側壁覆蓋有絕緣材料2〗2a，因此在進行上述氧化製程 時’氧氣不致通過絕緣材料220a，故第二閘極218b下的 鬧極氧化物層208將不致變厚。故，上述的氧化製程可提 供第一主動區2〇4a與第二主動區2〇4b形成不同厚度的蘭 極氧化物層208a、208。此外，氧化的熱製程可順勢修補 在定義第一閘極218a與第二閘極218b的乾飩刻對閘極氧 化物層208、208a造成的損害。再者，複晶矽層212暴露 出的側壁因氧化亦會形成一薄氧化物層覆蓋其上。 續則進行習知的製程，包括淡摻雜汲極區之植入，間 隙壁之形成以及源/汲極區之植入等步驟。至於電容器，不 限於堆疊式電容器（stack capacitor)或是深溝渠式電容器 (deep trench capacitor) 〇 本較佳實施例係在第二閘極218b側壁上覆蓋絕緣材 料220a，使得在後續氧化製程時，氧氣僅與第一閘極218a 的複晶矽層212反應而使閘極氧化物層208加厚，而可形 9 — 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公i " (諳先聞讀背面之注意事項再填寫本頁) -訂 經濟部智慧財產局員工消費合作社印製 4 3 91 5 8- 5782twf.dc>c/008 A? ___ B7 五、發明説明（分） 成具有較閘極氧化物層2〇8爲厚的閘極氧化物層2〇8a。其 中，由於LDD的植入步驟係在絕緣材料22〇a形成後始進 行’因此絕緣材料220a的厚度需較薄，以避免影響到LDD 的植入。 第二較佳實施例 第3A-3C圖所示，爲根據本發明〜第二較佳實施例具 有雙重閘極氧化物層的半導體兀件之製造流程剖面圖。第 3Α圖之製程與第2Α圖相同’標號亦沿用第2Α圖之標示， 因此在此不再贅述。 請參照第3Β圖，在第二主動區2〇4b上覆蓋一光阻 222a，光阻222a係利用微影定義，而接著在光阻22仏的 覆蓋下’去除第一主動區204a的絕緣材料220，例如使用 濕蝕刻法，使第一閘極218a側壁暴露出。之後，進行將光 阻222a剝除的步驟。 請參照第3C圖，在將光阻222a去除後，接著進行一 氣化步驟’氧化步驟係利用溫度約爲8 5 0 -10 8 5。C的熱製 程，氧化層厚度控制在40-100A左右，使環境中的氧氣因 加溫擴散進入第一閘極218a的複晶砂層212與閘極氧化物 層208介面，而氧化複晶砂層212，使閘極氧化物層208 變厚成如第3C圖所示之閘極氧化物層2〇8b。而在第二主 動區204b第二閘極218b的側壁覆蓋有絕緣材料220b，因 此在進行上述氧化製程時，氧氣不致通過絕緣材料220b， 故第二閘極218b下的閘極氧化物層2〇8將不致變厚。故， 上述的氧化製程提供第一主動區204a與第二主動區204b 10 本紙張尺度適用中國國家標华（CNS ) Α4規格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁) - 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 -^3915 8-s ' A7 57 82twf, doc/008 五、發明説明（q ) 上形成不同厚度的閘極氧化物層208a、208。此外，氧化 的熱製程可順勢修補在定義第一閫極218a與第二閘極 218b的乾蝕刻對閘極氧化物層208、208a造成的損害，且 複晶矽層212暴露出的側壁亦會形成一薄氧化物層。 續則進行習知的製程，包括淡摻雜汲極區之植入，間 隙壁之形成以及源/汲極區之植入等步驟。至於電容器，不 限於堆疊式電容器（stack capacitor)或是深溝渠式電容器 (deep trench capacitor) ° 本較佳實施例係在第二閘極218b側壁上覆蓋絕緣材 料220b ’使得在後續氧化製程時，氧氣僅與第一閘極218a 的複晶矽層212反應而使閘極氧化物層208加厚，而可形 成具有較閘極氧化物層208爲厚的閘極氧化物層208a。其 中’由於LDD的植入步驟係在絕緣材料22〇b形成後始進 行’因此絕緣材料220b的厚度需較薄，以避免影響到LDD 的植入。 本發明係在閘極完成後，且在邏輯電路區的閘極側壁 覆蓋絕緣材料後’利用熱製程加厚記憶體區的閘極氧化物 層’而可依主動區元件的需求製造具有不同厚度的閘極氧 化物層。 本發明提出之製程步驟，不僅較爲簡易，且在閘極完 成進行氧化’使得閘極氧化物層更可維持較佳的品質。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內’當可作各種之更動與潤飾，因此本發明之保護 本紙張尺度適用中國國豕標準（CNS ) A4規格（210x297公釐） (請先閲讀背面之注意事項再填寫本頁)N 5782tWfd〇c / 〇〇g Ί 7 7 7 7 7 7 7 7 7 7 7, remove the insulating material 220a on the side wall of the first active region—the gate 218a—for example, by wet-etching, and make the first gate 嬖Exposed. Continue to remove the photoresist 222. Referring to FIG. 2D, after the photoresist 222 is removed, an oxidation step is performed. The oxidation step uses a temperature of about 850-108. <: In the thermal process, the thickness of the oxide layer is controlled to about 40 ~ 100A ', so that the oxygen in the environment diffuses into the interface between the polycrystalline silicon layer 2U and the gate oxide layer 208 due to the heating, and the oxide is The crystalline silicon layer 212 thickens the gate oxide layer 208 to a gate oxide layer 208a as shown in FIG. 2D, and the side wall of the second active region 2 (Mb second gate 2118b is covered with an insulating material 2 [2a] Therefore, during the above-mentioned oxidation process, 'oxygen will not pass through the insulating material 220a, so the anode oxide layer 208 under the second gate electrode 218b will not be thickened. Therefore, the above-mentioned oxidation process can provide the first active region 2 〇4a and the second active region 204b form different thicknesses of the blue oxide layers 208a, 208. In addition, the thermal process of oxidation can be used to repair the dry-etched pairs defining the first gate 218a and the second gate 218b. Damage caused by the gate oxide layers 208, 208a. Furthermore, the exposed sidewalls of the polycrystalline silicon layer 212 will also form a thin oxide layer covering it due to oxidation. Continued conventional processes, including light doping, are performed. The implantation of the drain region, the formation of the gap wall, and the implantation of the source / drain region. For the capacitor, it is not limited to a stack capacitor or a deep trench capacitor. This preferred embodiment covers the side wall of the second gate electrode 218b with an insulating material 220a, so that during the subsequent oxidation process, Oxygen only reacts with the polycrystalline silicon layer 212 of the first gate 218a to thicken the gate oxide layer 208, and it can be shaped 9 — This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 male i " (闻 First read the notes on the back before filling out this page)-Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 4 3 91 5 8- 5782twf.dc > c / 008 A? ___ B7 V. Description of the invention (minutes) It has a gate oxide layer 208a which is thicker than the gate oxide layer 208. Among them, since the LDD implantation step is performed after the formation of the insulating material 22a, the thickness of the insulating material 220a needs to be Thin to avoid affecting the implantation of LDD. The second preferred embodiment, shown in Figures 3A-3C, is a manufacturing process of a semiconductor element having a dual gate oxide layer according to the present invention ~ the second preferred embodiment. Sectional view. Process of Figure 3A and The same reference numerals in Figure 2A are also used in Figure 2A, so it will not be repeated here. Please refer to Figure 3B. A photoresist 222a is covered on the second active area 204b. The photoresist 222a is defined by lithography. Then, the insulating material 220 of the first active region 204a is removed under the covering of the photoresist 22 仏, for example, the sidewall of the first gate electrode 218a is exposed using a wet etching method. Then, a step of stripping the photoresist 222a is performed. Please refer to FIG. 3C. After the photoresist 222a is removed, a gasification step is performed. The oxidation step uses a temperature of about 8 5 0 -10 8 5. In the thermal process of C, the thickness of the oxide layer is controlled at about 40-100A, so that oxygen in the environment diffuses into the interface between the polycrystalline sand layer 212 and the gate oxide layer 208 of the first gate 218a due to heating, and oxidizes the polycrystalline sand layer 212. The gate oxide layer 208 is thickened to a gate oxide layer 208b as shown in FIG. 3C. The side wall of the second gate electrode 218b in the second active region 204b is covered with an insulating material 220b. Therefore, during the above-mentioned oxidation process, oxygen does not pass through the insulating material 220b, so the gate oxide layer 2 under the second gate electrode 218b. 8 will not thicken. Therefore, the above-mentioned oxidation process provides the first active area 204a and the second active area 204b. 10 This paper size applies to China National Standards (CNS) A4 specifications (210 × 297 mm) (Please read the precautions on the back before filling this page) -Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-^ 3915 8-s' A7 57 82twf, doc / 008 V. Description of the invention (q) Gate oxides of different thicknesses are formed物 层 208a 、 208。 Object layers 208a, 208. In addition, the thermal process of oxidation can repair the damage to the gate oxide layers 208 and 208a caused by the dry etching that defines the first gate electrode 218a and the second gate electrode 218b, and the exposed sidewalls of the polycrystalline silicon layer 212 will also A thin oxide layer is formed. Next, the conventional process is performed, including the steps of implanting the lightly doped drain region, forming the gap wall, and implanting the source / drain region. As for the capacitor, it is not limited to a stack capacitor or a deep trench capacitor. In the preferred embodiment, the sidewall of the second gate electrode 218b is covered with an insulating material 220b, so that during the subsequent oxidation process, Oxygen only reacts with the polycrystalline silicon layer 212 of the first gate 218a to thicken the gate oxide layer 208, and a gate oxide layer 208a having a thicker thickness than the gate oxide layer 208 can be formed. Among them, since the LDD implantation step is performed after the insulating material 22b is formed, the thickness of the insulating material 220b needs to be thin to avoid affecting the LDD implantation. After the gate electrode is completed and the gate side wall of the logic circuit region is covered with an insulating material, the present invention can use the thermal process to thicken the gate oxide layer in the memory region, and can be manufactured with different thicknesses according to the requirements of the active region components. Gate oxide layer. The process steps provided by the present invention are not only relatively simple, but also the gate electrode is oxidized, so that the gate oxide layer can maintain better quality. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The size of this paper applies to China National Standard (CNS) A4 (210x297 mm) (Please read the precautions on the back before filling this page)
4391 58 A7 5 7 8 21 wf. do c/008 五、發明説明（p) 範圍當視後附之申請專利範圍所界定者爲準。 (請先聞讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐）4391 58 A7 5 7 8 21 wf. Do c / 008 5. Description of invention (p) The scope shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm)