4 6094 8 A7 B7 五、發明説明（） 5·1發明領域 本發明係有關於一種形成電晶體閘極的方法，特別 是有關於一種形成電晶體閘極的方法，可以避免因為所 形成之閘極氧化層厚度改變，而使電晶體臨界電壓 (threshold)漂移。 5-2發明背景 在形成電晶體的製程當中，首先參考第一圖，提供 —個具有結晶方向< 1 00>的單晶矽基底 1 00，傳統的方法 是在其表面形成一厚的場氧化層（Field oxide : FOX )，以 提供基底1 00上的元件間之電性隔絕。接著，在基底1 00 表面形成一第一氧化層102，以作為後續所要形成的金氧 半場效電晶禮（Metal Oxide Semiconductor Field Effect Transistor ·· MOSFET)的閘氧化層（gate oxide)之用。 接著.下一個_步驟是形成第一複晶梦層103於第 一氧化層102上’然後是形成一矽化鎢層1〇4於第二介電 層1 03表面上》接著是以標準的曝光顯影及蝕刻等步驟以 定義(patterning)將要製作的金氡半場效電晶體之閘極結 經濟部中央梯準局男工消费合作社印裂 (請先閱讀背面之注意事項再填寫本頁) 構。參考第二圖’定義所要形成的金氧半場效電晶體的閘 極結構時，是以一個標準的微影及蝕刻製程，用光阻圖樣 層1 13為蝕刻罩幕（mask)，以形成閘極矽化鎮層1〇4以及 閘極複晶矽層1 03。在閘極矽化鎢層1 〇4以另 A久閘極複晶矽 層103形成之後’光阻圖樣層彳13被去除掉·，並且接著要 本紙張尺度適用中國國家榇準（CNS).A4規格（21〇χ297公蝥· 460948 A7 B7 經濟部中央標準局員工.消费合作社印製 五、發明説明（ 進：-離子植入步驟’ u定義出電晶趙(亦 金氧半場效電晶體）的源極區域以及汲極區域。 、 下一個步驟，參考第三圖，熹 12 0» w ^ 是進订第一離子植入 ^閘極们b鶴層1G4以及閘極複晶⑪層1Q 子 植入時的罩幕<mask)之用。在 ·" 隹淥後a 你返仃弟離子植入時，離子 ^第：氧…〇2’在基惠100中形成輕摻雜區122。 植二11〇中’是以填為離子源，其濃度大約為 個扪禋镠雜所形成。然後再進行溫度约 為攝氏900至1000度的回火步驟，以恢復在第一離子植 入1 20步驟中被破壞的部分晶片表面之矽原子結構。 如第四圖所示，形成第二氧化層13〇於整個晶圓表 面上，並利用蝕刻法，定義出後續製程步驟所要形成的側 間，壁（3丨(^西3|丨3口3<^.「）。其中第二氧化層13〇所用的材 質是二氧化矽（silicon dioxide) ’然後用一個非等向性蝕刻 對第二氧化層1 30進行蝕刻，蝕刻之後的結果可參考第五 圖’其中已經於閘極矽化鎢層104以及閘極複晶梦層1〇3 的側壁上形成間隙壁1 4Ό。接著參考第六圖，進行第二離 子植入160’以形成第二摻雜區161。在上述第二離子植 入1 60步驟中，是以閘極矽化鎢層彳〇4、閘極複晶硬層，〇3 以及間隙壁1 40作為的罩幕（mask)。第二摻雜區161可以 用砷離子濃度大約為每平方公分1015個的摻雜所形成。 然後參考第七圖，下一個步驟是先行成一氧化層（未 圖示）再形成硼磷矽玻璃（BPSG)層165於整個晶圓表面， 然後以傳統钱刻方式’對领填梦玻璃（BPSG丨層165進行 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) J.--11^ 、-!! A7 B7 經濟部中央標準局只工消費合作社印製 46094 8 五、發明説明（） 蝕刻’以形成接觸窗1 6 7。上述的傳統蝕刻步驟是先形成 光阻圖案層，並且對硼磷矽玻璃（BPSG)層165進行蝕刻。 接著參考第八圖，形成金屬圖案層17〇，並接著形成保護 層175於金屬圖案層17〇以及硼磷矽玻@(BPSG)層165 上’其中的保護層175 —般是由氮化矽（Si NX)或是磷矽玻 璃（PSG)所形成，於是形成了電晶體的閘極、汲極以及源 極。 在上述製作電晶體的製程中，形成第一氧化層102、 閘極複晶矽層1 〇3之後，可以使用單矽曱烷（monosilane) 製程或是二氣矽曱烷（dich0|0sj|ane)製程，以形成電晶體閘 極的閘極梦化鶴層1 〇4。當使用單石夕曱烧（monosilane)製程 以形成閘極矽化鎢層1 〇4時，其反應式如下：4 6094 8 A7 B7 V. Description of the Invention (5.1) Field of the Invention The present invention relates to a method for forming a transistor gate, and in particular to a method for forming a transistor gate, which can avoid the formation of gates. The thickness of the polar oxide layer changes, so that the threshold voltage of the transistor drifts. 5-2 Background of the Invention In the process of forming a transistor, first referring to the first figure, a single crystal silicon substrate 100 having a crystal orientation < 1 00 > is provided. The traditional method is to form a thick field on its surface. An oxide layer (Field oxide: FOX) is provided to provide electrical isolation between components on the substrate 100. Next, a first oxide layer 102 is formed on the surface of the substrate 100 to serve as a gate oxide of a metal-oxide-semiconductor field-effect transistor (MOSFET) to be formed later. Next. The next step is to form a first polycrystalline dream layer 103 on the first oxide layer 102, and then to form a tungsten silicide layer 104 on the surface of the second dielectric layer 103. Next, a standard exposure is used. The steps of development and etching are used to define the pattern of the gate junction of the gold field half-effect transistor that will be produced. The printed circuit of the male labor consumer cooperative of the Central Ladder Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Referring to the second figure, when defining the gate structure of the metal-oxide-semiconductor field-effect transistor to be formed, a standard lithography and etching process is used, and a photoresist pattern layer 113 is used as an etching mask to form a gate. The siliconized ballast layer 104 and the gate polycrystalline silicon layer 103. After the gate tungsten silicide layer 104 was formed with another long-term gate polycrystalline silicon layer 103, the photoresist pattern layer 彳 13 was removed, and then the Chinese paper standard (CNS) .A4 was applied to this paper standard. Specifications (21 × 297297 蝥 460948 A7 B7 Employees of the Central Bureau of Standards of the Ministry of Economic Affairs. Printed by the Consumer Cooperative. V. Invention Description (Into:-Ion Implantation Steps' u Define the Electron Crystal (also a Metal Oxide Half Field Effect Transistor) Source region and drain region. In the next step, referring to the third figure, 熹 12 0 »w ^ is the first ion implantation ^ gates b crane layer 1G4 and gate complex osmium layer 1Q The use of the mask during the implantation. After the " aa, when you return to the younger ion implantation, the ion ^ th: oxygen ... 〇2 'forms a lightly doped region 122 in the base 100 Plant II 110 is filled with ions as an ion source, and its concentration is formed by an impurity. Then, a tempering step is performed at a temperature of about 900 to 1000 degrees Celsius to restore the first ion implantation. The silicon atomic structure on the surface of the part of the wafer that was damaged in step 1 20. As shown in the fourth figure, a second oxide layer 13 is formed. On the surface of each wafer, and using an etching method, the side walls (3 丨 (^ 西 3 | 丨 3 口 3 < ^. ") To be formed in the subsequent process steps are defined. Among them, the second oxide layer 13 is used The material is silicon dioxide. Then the second oxide layer 1 30 is etched with an anisotropic etch. For the results after the etching, please refer to the fifth figure. Among them, the tungsten silicide layer 104 and the gate are already used. A spacer 14 is formed on the sidewall of the polycrystalline dream layer 103. Then, referring to the sixth figure, a second ion implantation 160 'is performed to form a second doped region 161. In the above-mentioned first ion implantation step 160, It is a mask using a gate tungsten silicide layer 彳 04, a gate complex crystalline hard layer, 〇3, and a spacer 140. The second doped region 161 may have an arsenic ion concentration of about 1 cm <2>. 1015 doping is formed. Then referring to the seventh figure, the next step is to first form an oxide layer (not shown) and then form a borophosphosilicate glass (BPSG) layer 165 on the entire wafer surface, and then use the traditional money engraving method. 'For collar-filling dream glass (BPSG 丨 layer 165 in this paper size application National Standard (CNS) A4 specification (210X297 mm) (Please read the notes on the back before filling this page) J .-- 11 ^,-!! A7 B7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, only Consumer Cooperatives 46094 8 V. Description of the invention () Etching 'to form a contact window 1 6 7. The above-mentioned traditional etching step is to first form a photoresist pattern layer and etch a borophosphosilicate glass (BPSG) layer 165. Then refer to the eighth figure, A metal pattern layer 17 is formed, and then a protective layer 175 is formed on the metal pattern layer 17 and the borophosphosilicate glass (BPSG) layer 165. The protective layer 175 is generally made of silicon nitride (Si NX) or Formed by phosphosilicate glass (PSG), which forms the gate, drain, and source of the transistor. In the above-mentioned manufacturing process of the transistor, after the first oxide layer 102 and the gate polycrystalline silicon layer 10 are formed, a monosilane process or a two-gas silane (dich0 | 0sj | ane) can be used. ) Process to form the gate dream transistor layer 104 of the transistor gate. When a monosilane process is used to form the gate tungsten silicide layer 104, the reaction formula is as follows:
SiH4+WF6 WSix+HF 當使用二氯矽甲烷（dicholosilane)製程以形成電晶體 閘極的閘極矽化鎢層1〇4時，其反應式如下：SiH4 + WF6 WSix + HF When the dicholosilane process is used to form the transistor gate, the gate tungsten silicide layer 104 has the following reaction formula:
SiH2CI2+WF6+H2 WSix+HCl+HF 參考第三圖，在進行了對閘極複晶矽層103的退火 (annealing)步驟之後，若是閘極矽化鎢層彳04是由上述的 單矽曱烷（monosilane)製程所形成，則鄰近於被定義圖樣 (patterned)之後的閘極複晶矽層1〇3之第一氧化層1〇2, 在進行上述退火步驟之後，其厚度會增加，所以依據傳統 方法所形成的電晶體之鄰限電壓（threshold voltage)，與 原先設計者不同’上述是依據傳統方法所形成的電晶體閉 極之第一個缺點。除此之外，當用以形成閘極矽化鎮層’ 〇4 的矽化金屬步驟進行退火之後，閘極複晶矽層1〇3的厚度 4 本紙張尺度適用中國國家標隼（CNS ) A4規格（2丨0X 297公釐） (請先閲讀背面之注意事項再填寫本頁)SiH2CI2 + WF6 + H2 WSix + HCl + HF Referring to the third figure, after the annealing process of the gate polycrystalline silicon layer 103 is performed, if the gate tungsten silicide layer 彳 04 is composed of the above monosilicone (Monosilane) is formed, and the first oxide layer 10, which is adjacent to the gated polycrystalline silicon layer 103 after the patterned pattern, has an increased thickness after the above annealing step. The threshold voltage of the transistor formed by the traditional method is different from the original designer. 'The above is the first disadvantage of the closed-circuit of the transistor formed according to the traditional method. In addition, the thickness of the gate polycrystalline silicon layer 10 is 4 after the step of annealing the silicidation metal used to form the gate silicided layer 〇4. 4 This paper is in accordance with China National Standard (CNS) A4 (2 丨 0X 297 mm) (Please read the notes on the back before filling in this page)
B7 _____ 經濟部中央標準局貝工消费合作社印製 4 6094 8 A7 五、發明説明（） 會減少_ » 5 ·3發明目的及概述 一種製造電晶體的方法’可以防止所形成的電晶體 之閉極下的氧化層經過後續製程之後而厚度增加’此電晶 體係形成在一底材上，此方法包含下列步驟：首先形成一 氧化層於此底材上，接著形成第一複晶矽層於氧化層上’ 此第一複晶矽層係用矽甲烷（silane〉氣流所形成。接著形 成第二複晶矽層於第一複晶矽層上，此第二複晶石夕層係用 PH3(phosphine)氣流以及矽甲烷（silane)氣流以-流量比 沉積所形成，此PH3氣流對矽甲烷氣流之流量比大約為百 分之十五以上。第一複晶矽層以及第二複晶矽層係形成於 同一機台中，第二複晶矽層以及第一複晶矽層之總厚度大 約為800至2000埃。 械嫌將此 接著形成矽化金屬層於第二複晶矽層上’然佚 矽化金屬層、第二複晶矽層以及第一複晶矽層圖樣化’ 裸露第一部份之底材。然後執行第一離子植入步麻於裸& 的第一部份底材，以形成一第一摻雜區於裸露的第〆部份 此底材中。然後形成第一介電層於矽化金屬層以及禪露# 第一部份底材上，並以非等向性蝕刻此第一介電層’以於 矽化金屬層、第二複晶矽層以及第一複晶矽層側璧上形成 間隙壁（spacer)，裸露第二部分底材，並形成電晶禮之閉 極。然後用閘極為罩幕，以進行第二離子植入驟’用以 在裸露的第二部分底材中形成第二摻雜區。接著形成第二 (請先閱讀背面之注意事項再填寫本頁) trB7 _____ Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 6094 8 A7 V. The description of the invention () will be reduced _ »5 · 3 Purpose of the invention and outline a method of manufacturing a transistor 'can prevent the formation of the transistor The oxide layer under the electrode increases in thickness after subsequent processes. The electro-crystalline system is formed on a substrate. The method includes the following steps: first forming an oxide layer on the substrate, and then forming a first polycrystalline silicon layer on the substrate. On the oxide layer 'This first polycrystalline silicon layer is formed by silane gas flow. Then a second polycrystalline silicon layer is formed on the first polycrystalline silicon layer, and the second polycrystalline silicon layer is made of PH3. (phosphine) gas flow and silane gas flow are deposited at a flow rate ratio, and the flow ratio of this PH3 gas flow to the silane gas flow is about 15% or more. The first polycrystalline silicon layer and the second polycrystalline silicon The layer system is formed in the same machine, and the total thickness of the second polycrystalline silicon layer and the first polycrystalline silicon layer is about 800 to 2000 angstroms. It is suspected that a silicide metal layer is then formed on the second polycrystalline silicon layer.佚 Silicon metal layer, second The pattern of the polycrystalline silicon layer and the first polycrystalline silicon layer is to expose the substrate of the first portion. Then, a first ion implantation step is performed on the first portion of the substrate to form a first doped substrate. The impurity region is in the exposed second part of the substrate. Then a first dielectric layer is formed on the silicided metal layer and the first part of the substrate, and the first dielectric layer is anisotropically etched. 'To form a spacer on the silicided metal layer, the second polycrystalline silicon layer, and the side of the first polycrystalline silicon layer, exposing the second part of the substrate, and forming the closed electrode of the electric crystal. Then use the gate electrode Mask to perform the second ion implantation step to form a second doped region in the exposed second part of the substrate. Then form a second (please read the precautions on the back before filling this page) tr
本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 經濟部中央標準局貝工消费合作社印製 4 6 0 948 Α7 Β7 五、發明説明（） 介電層於閘極以及裸露的第二部分底材上。然後將第二介 電層圖樣化，以裸露第二部分底材，並且形成導電層於第 二介電層以及裸露的第二部分底材上，最後將此導電層圖 案化，以形成電晶體的源極以及汲極，其中源極以及汲極 電性偶合至第二摻雜區。 5-4圈式簡單說明 第一圖顯示依據傳統製作電晶體的方法中，形成氧 化矽層、第一複晶矽層以及矽化鎢層於一基底上之後的晶 圓截面圖。 第二圖顯示依據傳統製作電晶體的方法中，以標準 微影及蝕刻步驟對矽化鎢層以及複晶矽層進行蝕刻形成 圖樣，以形成閘極結構於晶圓上之後的截面圖。 第三圖顯示依據傳統製作電晶體的方法中，在基底 中形成第一摻雜區域之後的晶圓截面圖。 第四圖顯示依據傳統製作電晶體的方法中，在整個 晶圓表面形成一個二氧化矽層之後的晶圓截面圖。 第五圖顯示依據傳統製作電晶體的方法中，形成對 二氧化矽層進行蝕刻以形成閘極結構的間隙壁，以形成半 導體元件閘極之後的晶圓截面圖。 第六圖顯示依據傳統製作電晶體的方法中，以第二 離子植入步驟，並用半導體元件的閘極為罩幕，以形成第 二摻雜區於底材之後的晶圓截面圖。 ' 第七圖顯示依據傳統製作電晶體的方法中，具有接 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 4 60948 經濟部中央標準局只工消费合作社印製 A7 B7 五、發明説明（） 觸窗的磷矽玻璃（PSG)形成於底材上之後的晶圓截面圖。 第八圖顯示依據傳統製作電晶體的方法中，對形成 的導電層蝕刻圖樣於晶圓上，並且形成一保護層於整個晶 圓表面上而形成電晶體之後的圓裁面圖。 第九 A圖顯示依據本發明的一較佳實施例之方法 中’形成氧化矽層以及未摻雜複晶矽層於底材上之後的晶 圓截面圖。 第九 B圖顯示依據本發明的一較佳實施例之方法 中’形成經摻雜複晶矽層於未摻雜複晶矽層上之後的晶圓 截面圖。 第十圖顯示依據本發明的較佳實施例中，形成矽化 鎮層於經摻雜複晶矽層之後的晶圓截面圖。 第十一圖顯示以標準微影及蝕刻步驟處理矽化鎢層 以及複晶矽層，以形成閘極結構於晶圓之後的載面圖。 第十二圖顯示本發明..的較佳實施例中，實行第一離 子植入’以在基底中形成.第一摻雜區域之後的晶圓截面 圖。 第十三圖顯示本發明的較佳實施例中，在整個晶圓 表面形成一氧化矽層之後的晶圓截面圏。 第十四圖顯示本發明的較佳實施例中，於閘極結構 側壁上形成氧化矽的間隙壁，以形成電晶體閘極之後的晶 圓截面圖。 第十五圖顯示本發明的較佳實施例中，以第二離子 植入步驟’並用電晶體的閘極為罩幕，以形成第二摻雜區 本紙張尺度適用中國國家樣率（（Ns ) μ規格（ho〆297公楚 (請先閱讀背面之注意事項再填{?$本頁) 訂 Μ Β7 460948 五、發明説明（） 於底材之後的晶圓截面囷。 第十六圖顯示本發明的較佳實施例中，具有接觸窗 的磷矽玻璃（PSG)形成於底材上之後的晶圓截面圖。 第十七圖顯示依據傳統製作電晶體的方法中，形成 一導電層於晶圓上，並且蝕刻導電層以形成電晶體源極辉 汲極，並形成一保護層於整個晶圓表面上的之後的圓截面 圖。. 5-5發明詳細說明 因為鄰接於被定義圖樣（patterned)之後的閉極複 晶矽層111之部分第一氧化層102，在進行上述退火步 驟之後，其厚度會增加，所以依據傳統方法所製作的電 晶體，要控制其臨限電壓（threshold voltage)是相當不容 易的，所以本發明所提供的方法可以用來形成電晶體閑 極，而不會使得電晶體閘極下的閘極氧化層之厚度増 加。此外’依據傳統方法所形成的電晶體之問極的問極 複晶矽層的厚度，在用以形成閘極矽化鎢層的功入 …七/化金屬 (silicidation)步驟進行之後’閘極複晶矽層的電性厚产 減少。所以本發明提供一種用來形成電晶器 a 妨· 極的方 法，可以避免對閘極矽化鎢層進行的矽化合思止 經濟部中央標準局只工消费合作社印製 龙屬步称之 後’閘極複晶梦層的厚度因而減少。 本發明的實施例所提供的方法用在形忐 ^取電晶體的4 個步驟中時，其步驟如下所述。參考第九A窗 、提供一Ίε 具有結晶方向<100>的單晶矽基底400，左甘+ 仕其表面形成- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 4 60 94 8 A7 B7 五、發明説明（） 場氧化層（Field Oxide: FOX)區域401，以提供基底400 上的元件間之電性隔絕。場氧化層區域4 0 1之製作可以先 形成氮化矽層，然後再用曝光顯影以及乾蝕刻的方式蝕刻 氮化矽層，以形成出場氧化層區域4 0 1。在將光阻去除， 並且將晶圓經過濕式蝕刻之後，以熱氧化法在高溫氧氣中 形成氧化層區域401，並去除氮化矽層。而其中的場氧化 層區域401也可以使用其他隔絕方法，例如隔離溝（trench isolation)。 接著，在基底400表面形成一第一介電層402，以 作為後續所要形成的金氧半場效電晶體（Metal Oxide Semiconductor Field Effect Transistor : MOSFET)的閘 氧化層（gate oxide)之用。第一介電層402形成時，是以 大約攝氏800-1 1 00度的氧，將晶圓置入其中，以形成第 一介電層402。另一種形成第一介電層402的方法是對晶 圓實施適合的氧化物形成步驟，以形成第一介電層402。 場氧化層區域 401 之厚度大約為 3000-8000 埃 (angstroms) >而第一介電層之厚度大約為45-250埃。 經濟部中央橾涞局只工消费合作社印製 (請先閱讀背面之注意事項再填寫本頁) 接著下一個步驟是形成電晶體閘極所需要的複晶矽 層於整個晶圓上，為了要避免所要製造的電晶體閘極下的 閘極氧化層之厚度增加，所以本發明的一較佳實施例提供 的用於形成電晶體閘極氧化層的方法如下所述。首先形成 未摻雜複晶矽層403於整晶圓（包含場氧化層區域401以 及第一介電層402)表面上，其方法是用矽甲烷（SiH4)沉積 而成。然後參考第九 B圖，形成一個經摻雜晶.矽層 404 適用中國囷家標準（CNS ) Μ規格（210Χ297公釐） β〇948 ^濟部中央標準局员工消费合作社印製 A7 B7 五、發明説明（) 於未摻雜複晶矽層403上。 根據本發明的一較佳實施例，上述的經摻雜晶矽層 4〇4是在形成未摻雜複晶矽層403的同一個氣室中形成 的。而且經#雜複晶發層4Ό 4係用PH3(phosphine)氣流 以及矽甲烷（silane)氣流以一流量比沉積所形成，此pH3 氣流對矽曱烷氣流之流量比大約為百分之十五以上。並且 使其摻雜劑量大約是每平方公分5 X 1 01 5個原子以上。下 一個步驟是在經摻雜晶矽層404上形成一導電層406，參 考第十圖，依據本發明的較佳實施例中的未摻雜複晶矽層 403與經摻雜晶矽層4 04的總厚度範圍大約為800至2000 埃，而經掺雜晶矽層4 0 4的厚度大約為8 0 0埃，此外，導 電層406的厚度大約為1 250埃，本發明的較佳實施例中 的導電層406是由矽化鎢所組成。 然後’使用標準的微影（photo lithography)以及钱刻 製程’以形成電晶體的閘極結構，並定義電晶體的主動區 域（active area)。參考第十一圖，為了要定義電晶體的主 動區'域’使用上述標準的微影（photo lithography)以及姓.刻 製程，用光阻圖案層413為遮罩進行蝕刻，以形成閘極導 電層41 0以及閘極複晶矽層4彳1。閘極導電層4 1 0是由蝕 刻導電層406(第十圖）而得來，而閘極複晶矽層4 1 1是由 對未摻雜複晶矽層403(第十圖）以及經摻雜晶矽層404(第 十圖）所獲得，並且閘極複晶矽層41 1包含閘極未摻雜複 晶矽層4 1 1 a以及閘極經摻雜複晶矽層4 1 1 b。其中的閘極 未摻雜複晶矽層4 1 1 a是由蝕刻未摻雜複晶矽層403所獲 本紙張尺度適用中國國家標率（CNS ) Α4規格（210Χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) k. 、·ιτ 之 w # 一-46094b 經濟部中央標率局—工消费合作社印製 A7 B7 五、發明説明（） 得’而閘極經摻雜複晶矽層411 b是由姓刻經摻雜複晶矽 層404所獲得。前述的蝕刻步驟可以使用下列其中之一作 為姓刻劑：CF4 + O2、CHF3、c2F6、以及SFe + He。在閘極 導電層410以及閘極複晶矽層411形成之後，可以將光阻 圖案層4 1 3剝除’並且使用離子植入法，以形成電晶體的 汲極以及源極。 參考第十二圖’下一個步驟是進行第一離子植入 420’其中是以閘極導電層41〇以及閘極複晶石夕層411為 離子植入時的罩幕（mask)。以第一離子植入420在基底 4〇〇中形成了形成第一摻雜區422，形成第一摻雜區422 時’其換雜可以使用填離子捧雜（ph〇Sphorous rT dose) 或是硼離子換雜（boro η ρ· dose)而形成濃度較低的摻雜 區。在本實施例當中，是以磷為離子源，其濃度大約為每 平方公分1013個的離子摻雜所形成。然後進行一回火步 驟’以恢復在第一離子植入420步驟中，被損壞的部分晶 片表面之石夕晶格結構、 然後，如第十三囷所示，形成第二介電層430於整 個晶圓表面上’並利用微影法及蝕刻法，定義出後續製程 步驟所要形成的側間隙壁（sidewall spacer)。其中第二介 電層430所用的材質是氧化石夕（sj|jco.n dioxide)，然後用 一個非等向性蝕刻對第二介電層4 3 0進行蝕刻，以形成一 間隙壁440，蝕刻之後的結果可參考第十四圖，其中用來 蝕刻以形成間隙壁440的飯刻劑是使用下列其中一： CHF3、C3F8、CF4 + 〇2 以及 C2F6。 11 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29*7公漦） (請先閱讀背面之注意事項再填寫本頁) ---- _ 、1Tm I In , 460948 A7 B7 五、發明説明（ 參考第十五圖，接著進行第二離子植入46〇，以形 成第二摻雜區461。在此第二離子植入460中，是以閉極 導電層410、閘極複晶梦層411以及間隙壁44〇作為姓刻 罩幕（mad)。第二摻雜區461可以使用砷離子摻雜 (Arsenicn d〇se)或是蝴離子摻雜（B〇「〇n p+d〇se)而形成 濃度較高的摻雜區，在此是以神離子濃度大約為每平方公 分5x1 015個離子的摻雜所形成。 參考第十六圖所示，下一個步驟是形成硼磷矽玻璃 (BPSG)@ 465於整個晶圓表面，然後以傳統蚀刻方式， 對蝴填破玻璃（BPS0)層465進行餘刻，以形成接觸窗 467’使第二換雜區461裸露出來。上述的傳統蝕刻方式 可以是先形成光阻圖案層，並且以光阻圖案層為罩幕’對 硼磷矽玻璃（BPSG〉層465進行蝕刻》接著參考第十七圖， 形成金屬圖案層470，使其接觸第二摻雜區461，並接著 形成保護層475,其中的保護層475 —般是由氬化矽（SiNx) 或是鱗矽玻璃（PSG)所形成，於是電晶體的閘極、汲極以 及源極皆已形成。 經濟部中央標準局貝工消费合作社印製 (請先閱讀背面之注意事項再填炜本頁) 在上述製程中’因為依據本發明的較佳實施例所形 成的閉極複晶石夕層411包含了閘極未摻雜複晶矽错411a 與問極經換雜複晶梦層41 1 b，所以所形成的電晶體閘極 中，鄰接於閘極複晶矽層41 1下的閘極氧化層4〇2的厚 .度’不會因為後續的退火步驟而變厚。所以依據本發明 的較佳實施例所形成的電晶體，其臨限電壓（thresh〇|d voltage)可以獲得控制。除此之外，依據本發明.的較佳實 12 本紙張尺度適用中國國家標準（CNS > Μ規格（21〇><297公釐） .攀460948 kl B7 五、發明説明（) 施例中的閘極内，其用來對閘極導電層4 1 0進行金屬矽 化（silicidiation)步驟之後，因為閘極經掺雜複晶矽層 4 1 1 b，所以閘極複晶石夕層4 1 1的厚度不會增加。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之申請專利範圍；凡其它未脫離本發明所揭 示之精神下所完成之等效改變或修飾’均應包含在下述 之申請專利範圍内。 (請先鬩讀背面之注意事項再填寫本頁) 訂 經濟部中央操準局員工消费合作社印製 13 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）This paper size applies to China National Standard (CNS) A4 (210X 297 mm). Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 4 6 0 948 Α7 Β7. 5. Description of the invention () Dielectric layer on the gate and exposed The second part is on the substrate. The second dielectric layer is then patterned to expose the second portion of the substrate, and a conductive layer is formed on the second dielectric layer and the exposed second portion of the substrate. Finally, the conductive layer is patterned to form a transistor. Source and drain, wherein the source and drain are electrically coupled to the second doped region. 5-4 Ring Type Brief Description The first figure shows a cross-sectional view of a crystal circle after a silicon oxide layer, a first polycrystalline silicon layer, and a tungsten silicide layer are formed on a substrate in a conventional method for making a transistor. The second figure shows a cross-sectional view of a conventional method for fabricating a transistor by etching a tungsten silicide layer and a polycrystalline silicon layer using a standard lithography and etching step to form a pattern to form a gate structure on a wafer. The third figure shows a cross-sectional view of a wafer after a first doped region is formed in a substrate in a conventional method for fabricating a transistor. The fourth figure shows a cross-sectional view of a wafer after a silicon dioxide layer is formed on the entire wafer surface in a conventional method for making a transistor. The fifth figure shows a cross-sectional view of a wafer after a silicon dioxide layer is etched to form a gate structure of a gate structure to form a semiconductor element gate according to a conventional method for fabricating a transistor. FIG. 6 is a cross-sectional view of a conventional method for fabricating a transistor in which a second ion implantation step is used and a gate electrode of a semiconductor device is used to mask the second doped region behind the substrate. '' The seventh figure shows the traditional method of making transistors, which has the paper size applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) (please read the precautions on the back before filling this page) Order 4 60948 Economy The Central Standards Bureau of the People's Republic of China only prints A7 B7 from the Consumer Cooperative. V. Description of the invention () The cross-sectional view of the wafer after the contact glass is formed on the substrate. The eighth figure shows a circular cross-sectional view of the conventional method for forming a transistor, after etching the formed conductive layer on the wafer, and forming a protective layer on the entire wafer surface to form the transistor. Fig. 9A shows a cross-sectional view of a circle after the formation of a silicon oxide layer and an undoped polycrystalline silicon layer on a substrate in a method according to a preferred embodiment of the present invention. FIG. 9B shows a cross-sectional view of a wafer after forming a doped polycrystalline silicon layer on an undoped polycrystalline silicon layer in a method according to a preferred embodiment of the present invention. The tenth figure shows a cross-sectional view of a wafer after forming a silicided ballast layer after doped with a polycrystalline silicon layer in a preferred embodiment according to the present invention. The eleventh figure shows a carrier surface after the tungsten silicide layer and the polycrystalline silicon layer are processed by standard lithography and etching steps to form a gate structure after the wafer. The twelfth figure shows a cross-sectional view of the wafer after the first doped region is formed in the substrate according to the preferred embodiment of the present invention. The thirteenth figure shows a wafer cross section 之后 after a silicon oxide layer is formed on the entire wafer surface in a preferred embodiment of the present invention. Fig. 14 shows a cross-sectional view of a crystal circle after a silicon oxide spacer is formed on a side wall of the gate structure to form a transistor gate in a preferred embodiment of the present invention. The fifteenth figure shows a preferred embodiment of the present invention. In the second ion implantation step, the gate electrode of the transistor is used to form a second doped region. The paper size is applicable to the Chinese national sample rate ((Ns ) μ specifications (ho〆297gongchu (please read the precautions on the back and fill in {? $ this page) Order M Β7 460948 V. Description of the invention () Wafer cross section after the substrate 囷. Figure 16 shows In a preferred embodiment of the present invention, a cross-sectional view of a wafer after a phosphosilicate glass (PSG) with a contact window is formed on a substrate. FIG. 17 shows a method of forming a conductive layer in a conventional method for fabricating a transistor. After the conductive layer is etched on the wafer to form a transistor source glow drain and a protective layer is formed on the entire wafer surface, a circular cross-sectional view is made. 5-5 Detailed description of the invention because it is adjacent to the defined pattern ( After the patterned) part of the first oxide layer 102 of the closed polycrystalline silicon layer 111, the thickness of the first oxide layer 102 will increase after the above annealing step. Therefore, the threshold voltage of the transistor manufactured according to the traditional method should be controlled. )is very It is easy, so the method provided by the present invention can be used to form transistor idler without increasing the thickness of the gate oxide layer under the transistor gate. In addition, the question of the transistor formed according to the traditional method The thickness of the interfacial polycrystalline silicon layer is reduced after the power input used to form the gate tungsten silicide layer ... the siliconidation step is performed. Provide a method for forming a transistor and a pole to avoid silicification of the tungsten silicide layer of the gate. The Central Standards Bureau of the Ministry of Economic Affairs, the Ministry of Economic Affairs ’s Standards and Consumer Cooperatives will print the dragon ’s step scale after the gate ’s complex crystal. The thickness of the dream layer is thus reduced. When the method provided in the embodiment of the present invention is used in the four steps of the shape of the transistor, the steps are as follows. Referring to the ninth window A, providing a Ίε with a crystal direction < 100 > Single-crystal silicon substrate 400, Zogan + Shiqi surface formation-This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 4 60 94 8 A7 B7 V. Description of the invention () Field oxide layer (Field Ox ide: FOX) region 401 to provide electrical isolation between components on the substrate 400. The field oxide layer region 401 can be produced by first forming a silicon nitride layer, and then etching the nitride by exposure development and dry etching. A silicon layer is formed to form the field oxide region 401. After the photoresist is removed and the wafer is wet-etched, an oxide layer region 401 is formed in high temperature oxygen by a thermal oxidation method, and the silicon nitride layer is removed. The field oxide region 401 therein may also use other isolation methods, such as trench isolation. Next, a first dielectric layer 402 is formed on the surface of the substrate 400 as a gold-oxygen half field-effect transistor to be formed subsequently. (Metal Oxide Semiconductor Field Effect Transistor: MOSFET) for gate oxide. When the first dielectric layer 402 is formed, the wafer is placed therein with oxygen at about 800-1100 degrees Celsius to form the first dielectric layer 402. Another method of forming the first dielectric layer 402 is to perform a suitable oxide formation step on the wafer to form the first dielectric layer 402. The thickness of the field oxide layer region 401 is about 3000-8000 angstroms (angstroms) and the thickness of the first dielectric layer is about 45-250 angstroms. Printed by the Central Government Bureau of the Ministry of Economic Affairs of the Consumer Cooperative (please read the notes on the back before filling this page). The next step is to form the polycrystalline silicon layer required for the transistor gate on the entire wafer. The thickness of the gate oxide layer under the transistor gate to be manufactured is prevented from increasing, so a method for forming a transistor gate oxide layer provided by a preferred embodiment of the present invention is as follows. First, an undoped polycrystalline silicon layer 403 is formed on the surface of the entire wafer (including the field oxide layer region 401 and the first dielectric layer 402), and the method is deposited by using silicon methane (SiH4). Then refer to the ninth figure B to form a doped crystal. The silicon layer 404 applies the Chinese Standard (CNS) M specification (210 × 297 mm) β〇948 ^ Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 5. DESCRIPTION OF THE INVENTION () On the undoped polycrystalline silicon layer 403. According to a preferred embodiment of the present invention, the above-mentioned doped crystalline silicon layer 40 is formed in the same gas chamber in which the undoped polycrystalline silicon layer 403 is formed. And the #heterocomposite hair layer 4Ό4 is formed by PH3 (phosphine) gas flow and silane gas flow deposition at a flow ratio. The flow ratio of this pH3 gas flow to the silane gas flow is about 15%. the above. And its doping dose is about 5 X 1 01 5 atoms per square centimeter or more. The next step is to form a conductive layer 406 on the doped crystalline silicon layer 404. Referring to the tenth figure, the undoped polycrystalline silicon layer 403 and the doped crystalline silicon layer 4 according to the preferred embodiment of the present invention 4 The total thickness of 04 is in the range of about 800 to 2000 angstroms, and the thickness of the doped crystalline silicon layer 404 is about 800 angstroms. In addition, the thickness of the conductive layer 406 is about 1 250 angstroms, which is a preferred implementation of the present invention. The conductive layer 406 in the example is composed of tungsten silicide. Then 'use standard photo lithography and money lithography processes' to form the gate structure of the transistor and define the active area of the transistor. Referring to the eleventh figure, in order to define the active area 'domain' of the transistor, the above-mentioned standard photo lithography and surname. Engraving process are used, and the photoresist pattern layer 413 is used as a mask to etch to form gate conduction. Layer 41 0 and gate polycrystalline silicon layer 4 彳 1. The gate conductive layer 4 1 0 is obtained by etching the conductive layer 406 (tenth picture), and the gate polycrystalline silicon layer 4 1 1 is formed by pairing an undoped polycrystalline silicon layer 403 (tenth picture) and Obtained from the doped crystalline silicon layer 404 (tenth figure), and the gate polycrystalline silicon layer 41 1 includes a gate undoped polycrystalline silicon layer 4 1 1 a and a gate doped polycrystalline silicon layer 4 1 1 b. The gate undoped polycrystalline silicon layer 4 1 1 a is obtained by etching the undoped polycrystalline silicon layer 403. The paper size is applicable to China National Standard (CNS) A4 specification (210 × 297 mm) (please first Read the notes on the back and fill in this page) k. 、 · Ιτ 的 w # 一 -46094b Printed by the Central Bureau of Standards of the Ministry of Economy—Industrial and Consumer Cooperatives Co., Ltd. A7 B7 5. The description of the invention () is obtained, and the gate is doped The crystalline silicon layer 411 b is obtained by engraving a doped polycrystalline silicon layer 404. The foregoing etching step may use one of the following as the last name etchants: CF4 + O2, CHF3, c2F6, and SFe + He. After the gate conductive layer 410 and the gate polycrystalline silicon layer 411 are formed, the photoresist pattern layer 4 1 3 can be stripped 'and an ion implantation method can be used to form the drain and source of the transistor. Referring to the twelfth figure, the next step is to perform the first ion implantation 420 ', in which the gate conductive layer 41 and the gate polycrystalline stone layer 411 are used as the ion implantation mask. A first ion implantation 420 is used to form a first doped region 422 in the substrate 400. When the first doped region 422 is formed, the doping can be performed by using a phOSphorous rT dose or The boron ion is doped (boro η ρ · dose) to form a doped region with a lower concentration. In this embodiment, phosphorus is used as the ion source, and its concentration is about 1013 ions per square centimeter. Then a tempering step is performed to restore the stone lattice structure on the surface of the damaged part in the first ion implantation step 420. Then, as shown in the thirteenth step, a second dielectric layer 430 is formed. On the entire wafer surface, the lithography and etching methods are used to define the side wall spacers to be formed in the subsequent process steps. The material of the second dielectric layer 430 is sj | jco.n dioxide, and then the second dielectric layer 430 is etched with an anisotropic etching to form a spacer 440. The result after the etching can be referred to the fourteenth figure, wherein one of the following etching agents used to etch to form the partition wall 440 is: CHF3, C3F8, CF4 + 〇2, and C2F6. 11 This paper size applies Chinese National Standard (CNS) A4 specification (210X29 * 7mm) (Please read the notes on the back before filling this page) ---- _ 、 1Tm I In, 460948 A7 B7 V. Description of the invention (Refer to the fifteenth figure, and then perform a second ion implantation 46 to form a second doped region 461. In this second ion implantation 460, a closed-electrode conductive layer 410 and a gate complex crystal dream layer are formed 411 and the spacer 44 are used as the engraved mask (mad). The second doped region 461 may be doped with arsenic ion (Arsenicn dosse) or butterfly ion doped (Bo "〇n p + dose ) To form a higher-concentration doped region, which is formed by doping a god ion with a concentration of about 5 × 1015 ions per square centimeter. Referring to the sixteenth figure, the next step is to form borophosphosilicate glass (BPSG) @ 465 on the entire wafer surface, and then perform conventional etching on the butterfly filled glass (BPS0) layer 465 to form a contact window 467 'to expose the second impurity region 461. The above-mentioned tradition The etching method may be to first form a photoresist pattern layer, and use the photoresist pattern layer as a mask. Glass (BPSG> layer 465 is etched), then referring to the seventeenth figure, a metal pattern layer 470 is formed so that it contacts the second doped region 461, and then a protective layer 475 is formed, wherein the protective layer 475 is generally argonized Silicon (SiNx) or scale silicon glass (PSG) is formed, so the gate, drain, and source of the transistor have been formed. Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back first) (Fill on this page again) In the above process, 'because the closed polycrystalline silicon layer 411 formed according to the preferred embodiment of the present invention includes the gate undoped polycrystalline silicon wafer 411a and the intermetallic compound The crystal dream layer 41 1 b, so in the transistor gate formed, the thickness of the gate oxide layer 4 2 adjacent to the gate polycrystalline silicon layer 41 1 is not changed by the subsequent annealing step. Thick. Therefore, the threshold voltage (thresh || d voltage) of the transistor formed according to the preferred embodiment of the present invention can be controlled. In addition, according to the present invention. Chinese National Standards (CNS > M specifications (21〇 > < 297 mm). 460948 kl B7 V. Description of the invention () In the gate electrode in the embodiment, it is used to perform a metal silicidation step on the gate conductive layer 4 1 0 because the gate is doped with a polycrystalline silicon layer 4 1 1 b, so the thickness of the gate polycrystalite layer 4 1 1 will not increase. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention; All equivalent changes or modifications' under the disclosed spirit should be included in the scope of patent application described below. (Please read the notes on the back before filling out this page) Order Printed by the Consumer Cooperatives of the Central Office of the Ministry of Economic Affairs 13 This paper size applies to China National Standard (CNS) A4 (210X297 mm)