476137 6614twf.doc/006 B7 五、發明說明（/ ) 本發明是有關於一種半導體積體電路的製造方法，且 特別是有關於一種閘氧化層之製造方法。 在積體電路蓬勃發展的今日’元件縮小化與積集化是 必然之趨勢，也是各界積極發展的重要課題。當元件尺寸 逐漸縮小，積集度（integration)逐漸提高，元件間的隔離結 構也必須縮小，因此元件隔離技術困難度也逐漸增高。元 件隔離有利用區域氧化法(local oxidation，LOCOS)來形成 的場氧化層(field oxide)，由於場氧化層受限於其外型之鳥 嘴(bird’s beak)區的形成，而容易造成遺漏電流（leakage current)，以至於造成影像出現壳點（white spot)的現象， 要縮小其尺寸實有困難。 有鑒於此，已有其他元件隔離方法持續被發展出來， 其中以淺溝渠隔離(Shallow Trench Isolation，STI)最被廣泛 應用，尤其應用於次半微米(sub-half micron)的積體電路製 程中。 習知的淺溝渠隔離的製造流程爲在基底上依序形成墊 氧化層和氮化矽罩幕層。然後進行微影步驟，定義出欲形 成溝渠的區域，再依序以乾蝕刻法來蝕刻氮化矽層、墊氧 化層和基底，在基底中形成溝渠。而溝渠所圍繞著的區域 爲主動區，供後續製程在此形成各種主動元件之用。 接著在溝渠的表面以熱氧化法形成墊氧化層，再以化 學氣相沈積法沈積氧化矽於溝渠之中以及氮化矽罩幕層之 上。然後進行化學機械硏磨法，將高於氮化矽罩幕層之氧 化矽層去除掉，以形成溝渠中之淺溝渠隔離結構。最後再 請 先 閱 讀 背 意 事 項476137 6614twf.doc / 006 B7 V. Description of the Invention (/) The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular, to a method for manufacturing a gate oxide layer. Today's booming development of integrated circuits is the inevitable trend of component shrinkage and accumulation, and it is also an important issue for the active development of various circles. When the component size is gradually reduced and the integration is gradually increased, the isolation structure between the components must also be reduced, so the difficulty of component isolation technology is gradually increased. Element isolation uses a field oxide (LOCOS) method to form a field oxide. Because the field oxide is limited by the formation of its bird's beak area, it can easily cause leakage current. (Leakage current), so that white spots appear in the image, it is difficult to reduce its size. In view of this, other component isolation methods have been continuously developed. Among them, Shallow Trench Isolation (STI) is most widely used, especially in sub-half micron integrated circuit manufacturing processes. . The conventional manufacturing process of shallow trench isolation is to sequentially form a pad oxide layer and a silicon nitride mask layer on the substrate. Then, a lithography step is performed to define the area where the trench is to be formed, and then the silicon nitride layer, the pad oxide layer, and the substrate are sequentially etched by a dry etching method to form a trench in the substrate. The area surrounded by the trench is the active area for subsequent processes to form various active components. A pad oxide layer is then formed on the surface of the trench by thermal oxidation, and then silicon oxide is deposited in the trench and on the silicon nitride mask layer by chemical vapor deposition. Then chemical mechanical honing is performed to remove the silicon oxide layer higher than the silicon nitride mask layer to form a shallow trench isolation structure in the trench. Finally, please read the memorandum first
再··! ^ 頁I 訂 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476137 6614twf.doc/006 A7 B7 經濟邹智慧財產局員工消費合作社印製 五、發明說明（z) 使用熱磷酸溶液來蝕刻氮化矽罩幕層，以及使用氫氟酸溶 液來触刻墊氧化層。 但是在製作淺溝渠隔離結構之製程中，以等向性蝕刻 移除墊氧化層與罩幕層時，會在淺溝渠隔離頂角（Top Edge Corner)周圍部分形成凹陷。因此形成閘氧化層時，在淺溝 渠隔離頂角周圍部分所形成之閘氧化層較薄於主動區所形 成之閘氧化層，而導致寄生元件傳導，即產生駝峰效應 (Hump effect)。之後塡充作爲閘極的複晶矽時，所形成之 閘極將包覆此淺溝渠隔離頂角，而造成較大的局部電場 (Local Intensified Field)，而使閘極具有較低的啓始電壓， 進而增加電晶體之次啓始漏電流（Sub-threshold Leakage)。 當積體電路的線寬愈來愈小，局部強化電場對整體電晶體 之啓始電壓下降的影響也將愈形嚴重。所以環繞淺溝渠隔 離頂角之聞氧化層形狀爲閘氧化層崩潰之主要原因。 本發明提供一種閘氧化層之製造方法，係在淺溝渠隔 離頂角部分形成較其他部分厚之閘氧化層，可防止因淺溝 渠隔離頂角（Top Edge Corner)部分導致之寄生元件傳導， 即產生駝峰效應(Hump effect)。 本發明提供一種聞氧化層之製造方法，不會造成主動 區域變小。 t 本發明提供一種閘氧化層之製造方法，此方法係在基 底上形成一層罩幕層’定我罩幕層並蝕刻基底，以在基底 中形成一溝渠。接者移除部分罩幕層，暴露溝渠以及溝渠 頂角周圍之區域。之後，以絕緣層塡滿溝渠及其頂角周圍 4 (請先閱讀背面之注音？事項再填寫本頁) 裝 · -I線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 476137 6614twf.doc/006 A7 B7 五、發明說明（彡） 之區域，再移除罩幕層而暴露部份基底表面。接著再對暴 露之部份基底表面植入摻質，使其氧化速率較未暴露出之 該基底表面慢。其後移除部分絕緣層，暴露溝渠頂角周圍 部分，接著在溝渠頂角周圍部分形成較其他部分厚之閘氧 化層。 依照本發明實施例所述，本發明的重要特徵爲摻質植 入步驟’除淺溝渠feg離頂角周圍部分外之其他部分植入氮 離子，降低氧化成長速率。以形成除淺溝渠隔離頂角周圍 部分外之其他部分較淺溝渠隔離頂角部分薄之閘氧化層。 在淺溝渠隔離頂角部分成長較厚之氧化層，可防止因淺溝 渠隔離頂角部分導致之寄生元件傳導，即產生駝峰效應。 另外，摻質之植入步驟，係在製造淺溝渠隔離結構的 過程中，使塡充於溝渠之中的絕緣層可以延伸覆蓋溝渠頂 角周圍之區域，然後再以其作爲自對準植入幕罩，僅在除 淺溝渠隔離頂角部分外的其他部分植入氮而降低氧化成長 速率’使後續所形成之閘氧化層在淺溝渠隔離頂角部分厚 度較其他部分厚。而不需額外之微影蝕刻步驟，可減少生 產花費，並且不會造成主動區域變小。 圖式之簡單說明 讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂’並進一步提供發明專利範圍之解釋，下文特舉一較 佳實施例，並配合所附圖式，作詳細說明如下： 第1A圖至第1G圖爲根據本發明較佳實施例之閘氧 化層製造流程剖面圖。 5 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂_ · ··線· 476137 6614twf.doc/006 五、發明說明（f ) 圖式標號之簡單說明 100 :基底 110 :墊氧化層 120 :罩幕層 130 :溝渠 140 :溝渠頂角周圍部分 140a :溝渠頂角周圍部分寬度 150 絕緣層 160 摻雜區 170 閘氧化層 (請先閱讀背面之注意事項再填寫本頁) 經齊邹A曰慧財¾¾員工消費合泎汪印製 實施例 本發明實施例之一種閘氧化層之製造流程分別以第1A 圖至第1G圖來說明。 請參照第1A圖，提供一基底100，例如是砂基底。 在基底100上形成一層墊氧化層110。塾氧化層11〇材質 例如是氧化砂，形成方法包括熱氧化法（Thermal Oxidation)。接著在墊氧化層110上形成一層罩幕層12〇。 罩幕層120材質例如是氮化矽層，形成方法包括化學氣相 沈積法（Chemical Vapor Deposition，CVD)，厚度例如是 2000 埃。之後叫微影與飽刻技術使罩幕層120與墊氧化層11〇 圖案化，並在基底100中形成一溝渠130，鈾刻方法例如 是電發蝕刻法（Plasma Etching)。 接著請參照第1B圖，進行所謂之後退(pullback)製程， 除去部分罩幕層120,以暴露溝渠130其頂角周圍部分140。 6 »- --線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476137 / 經濟部智慧財產局員工消費合作社印製 巧絛』 五、發明說明（f 所以此罩幕層120部分覆蓋溝渠13〇所圍之一主動區，並 使溝渠130頂部周圍之區域裸露出來。去除部分罩幕層12〇 的方法例如是等向性蝕刻，包括溼式蝕刻，係利用熱磷酸 洛液進行罩幕層120之蝕刻。暴露之溝渠頂角周圍部分14〇 的寬度140a例如200埃。 .接者請參照第1C圖，在基底1〇Q上形成一層絕緣層 150，此絕緣層150塡滿溝渠130並且覆蓋溝渠13〇其頂角 周圍部分140與罩幕層120之表面。絕緣層150之材質例 如是氧化矽，形成絕緣層]^方法例如是以四_乙基_鄰_矽 酸酯(Tetra Ethyl Ortho Silicate，TE0S)/臭氧（03)爲反應氣體 源利用化學氣相沈積法以形成之，之後進行密實化製程以 使絕緣層之結構更爲緻密。 接著請參照第1D圖，移除部分絕緣層150，以暴露 罩幕層120之表面。移除方法包括化學機械硏磨法(Chemical Mechanical Polishing，CMP)等。此製程係利用罩幕層120 當作硏磨終止層進行硏磨，直至暴露罩幕層120之表面。 接著請參照第1E圖，移除罩幕層120，暴露部分墊 氧化層110之表面。移除方法例如是等向性蝕刻包括溼式 蝕刻等。例如是利用墊氧化層110當作飩刻終止層，以熱 憐酸溶液進彳了触刻，直至暴露墊氧化層11 〇之表面。接著 進行摻質植入製程，以絕緣層150當作自對準植入罩幕， 將摻質經由所暴露之墊氧化層110表面植入基底100的表 面，形成摻雜區160。植入之摻質係用來降低基底100之 氧化速率，因此摻雜區160較其他未摻雜之部分氧化速率 jl. doc/009 $J7473號專利說明書修正頁Then ...! ^ Page I Alignment The paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 476137 6614twf.doc / 006 A7 B7 Economy Zou Intellectual Property Bureau Employees' Cooperative Printed by V. Invention Description (Z) Use a hot phosphoric acid solution to etch the silicon nitride mask layer, and use a hydrofluoric acid solution to etch the pad oxide layer. However, in the process of making the shallow trench isolation structure, when the pad oxide layer and the mask layer are removed by isotropic etching, a depression is formed around the top edge corner of the shallow trench isolation. Therefore, when the gate oxide layer is formed, the gate oxide layer formed around the apex corner of the shallow trench is thinner than the gate oxide layer formed in the active region, which leads to the conduction of parasitic elements, that is, the Hump effect. Later, when filling the polycrystalline silicon as the gate, the formed gate will cover the shallow trench isolation apex angle, resulting in a larger local electric field (Local Intensified Field), and the gate has a lower start Voltage, which in turn increases the Sub-threshold Leakage of the transistor. As the line width of integrated circuits becomes smaller and smaller, the effect of the locally enhanced electric field on the initial voltage drop of the overall transistor will also become more serious. Therefore, the shape of the oxide layer surrounding the top corner of the shallow trench is the main reason for the collapse of the gate oxide layer. The invention provides a method for manufacturing a gate oxide layer. A gate oxide layer thicker than other parts is formed at a shallow trench isolation apex portion, which can prevent the parasitic element conduction caused by the shallow trench isolation top corner portion. Hump effect is produced. The invention provides a method for manufacturing an oxide layer without causing the active area to be smaller. t The present invention provides a method for manufacturing a gate oxide layer. This method is to form a mask layer on a substrate, and then etch the substrate to form a trench in the substrate. The receiver removes part of the masking layer to expose the trench and the area around the top corner of the trench. After that, fill the trench and its surrounding corners with an insulating layer 4 (Please read the phonetic on the back? Matters before filling out this page) Installation · -I line · This paper size applies to China National Standard (CNS) A4 (210 X 297) (Mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476137 6614twf.doc / 006 A7 B7 5. In the area of the invention description (彡), remove the cover layer to expose part of the substrate surface. Then, dopants are implanted on the exposed part of the substrate surface, so that the oxidation rate is slower than that of the exposed substrate surface. After that, part of the insulation layer was removed to expose the part around the top corner of the trench, and then a gate oxide layer thicker than the other part was formed around the top corner of the trench. According to the embodiment of the present invention, an important feature of the present invention is that the implantation step of implantation is to implant nitrogen ions in a portion other than the part surrounding the shallow trench feg from the apex angle to reduce the oxidative growth rate. In order to form a gate oxide thinner than the shallow trench isolation apex, the gate oxide layer is thinner. Growing a thicker oxide layer at the top corner of the shallow trench isolation can prevent conduction of parasitic elements caused by the top corner of the shallow trench isolation, resulting in a hump effect. In addition, the implantation step of the dopant is in the process of manufacturing the shallow trench isolation structure, so that the insulating layer filled in the trench can extend to cover the area around the top corner of the trench, and then use it as a self-aligned implant For the curtain, nitrogen is implanted only in the portions other than the shallow trench isolation apex corner to reduce the oxidative growth rate, so that the subsequently formed gate oxide layer in the shallow trench isolation apex corner is thicker than other parts. Eliminating the need for an additional lithographic etching step reduces production costs and does not cause the active area to become smaller. A brief description of the drawings makes the above and other objects, features, and advantages of the present invention more obvious and understandable, and further provides an explanation of the scope of the invention patent. A preferred embodiment is given below in conjunction with the attached drawings to make The detailed description is as follows: FIGS. 1A to 1G are cross-sectional views of a manufacturing process of a gate oxide layer according to a preferred embodiment of the present invention. 5 This paper size applies the Chinese National Standard (CNS) A4 specification (21〇χ 297 mm) (Please read the precautions on the back before filling this page) Order _ · · · Line · 476137 6614twf.doc / 006 V. Invention Explanation (f) Brief description of the drawing number 100: substrate 110: pad oxide layer 120: cover layer 130: trench 140: portion around the top corner of the trench 140a: width around the top corner of the trench 150 Insulation layer 160 Doped region 170 Gate Oxide layer (please read the precautions on the back before filling this page) Figure 1G to illustrate. Referring to FIG. 1A, a substrate 100 is provided, such as a sand substrate. A pad oxide layer 110 is formed on the substrate 100. The material of the hafnium oxide layer 11 is, for example, oxidized sand, and a formation method includes a thermal oxidation method. Then, a mask layer 120 is formed on the pad oxide layer 110. The material of the mask layer 120 is, for example, a silicon nitride layer, and the formation method includes a chemical vapor deposition method (Chemical Vapor Deposition, CVD), and the thickness is, for example, 2000 angstroms. It is then called lithography and saturation technology to pattern the mask layer 120 and the pad oxide layer 110 and form a trench 130 in the substrate 100. The uranium etching method is, for example, Plasma Etching. Next, referring to FIG. 1B, a so-called pullback process is performed to remove a part of the mask layer 120 to expose the trench 140 and its surrounding corner portion 140. 6 »---- line · This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 476137 / Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (f So this cover The curtain layer 120 partially covers one of the active areas surrounded by the trench 13 and exposes the area around the top of the trench 130. The method of removing part of the mask layer 12 is, for example, isotropic etching, including wet etching, which uses heat. Phosphoric acid solution is used to etch the mask layer 120. The width 140a, such as 200 angstroms, of the portion 14 around the top corner of the exposed trench is connected. Referring to FIG. 1C, an insulating layer 150 is formed on the substrate 10Q. This insulation The layer 150 covers the trench 130 and covers the surface of the trench 130 and its surroundings at the top corners 140 and the surface of the mask layer 120. The material of the insulating layer 150 is, for example, silicon oxide to form an insulating layer. _Tetra Ethyl Ortho Silicate (TE0S) / ozone (03) is formed using a chemical vapor deposition method as a reaction gas source, and then a densification process is performed to make the structure of the insulating layer more compact. 1D drawing, removed Part of the insulating layer 150 is to expose the surface of the cover curtain layer 120. The removal method includes chemical mechanical polishing (CMP), etc. This process uses the cover curtain layer 120 as a honing stop layer for honing. Until the surface of the mask layer 120 is exposed. Referring to FIG. 1E, the mask layer 120 is removed to expose a portion of the surface of the pad oxide layer 110. The removal method is, for example, isotropic etching, including wet etching. The pad oxide layer 110 is used as an etch stop layer, and the etching is performed with a hot phosphoric acid solution until the surface of the pad oxide layer 110 is exposed. Then, a dopant implantation process is performed, and the insulating layer 150 is used as a self-aligned implant. The dopant is implanted into the surface of the substrate 100 through the exposed surface of the pad oxide layer 110 to form a doped region 160. The implanted dopant is used to reduce the oxidation rate of the substrate 100. Other undoped partial oxidation rates jl. Doc / 009 $ J7473 Patent Specification Revised Page
請 先 閱 讀 背 意 事 項 再 填 寫 本 頁 裝 I 應 I I I 訂 参 本紙張尺度適用中國國家標準（CNS)A4規格（210^ 297公釐） 476137 6614twf.doc/006 A7 B7 五、發明說明（6) 低。摻質例如是氮’植入之方法包括離子植入法’能量爲 5至10仟電子伏特，植入劑量約5x 1014/平方公分至lx 1015/ (請先閱讀背面之注意事項再填寫本頁) 平方公分。 接著請參照第1F圖，移除部分絕緣層150以及墊氧 化層110，以暴露基底100之表面。所裸露之基底100的 表面包括溝渠頂角周圍部分140的表面以及摻雜區160的 表面。移除部分絕緣層150以及墊氧化層110之方法包括 等向性蝕刻例如是溼式蝕刻等。係利用基底100當作蝕刻 終止層，以氫氟酸溶液作爲溼式蝕刻之蝕刻液進行蝕刻， 直至暴露基底100之表面。 --線- 參照第1G圖，在上述包括溝渠頂角周圍部分140的 表面以及摻雜區160的表面之基底1〇〇上成長氧化矽，因 爲溝渠頂角周圍部分140未植入摻質，而摻雜區160植入 使氧化速率變慢之摻質，所以在溝渠頂角周圍部分140的 表面氧化成長氧化矽之速率較摻雜區160的表面快。因此 形成一層溝渠頂角周圍部分140較厚而摻雜區160部分較 薄之閘氧化層170。其中閘氧化層170的形成方法包括熱 氧化法。 本發明提供一種閘氧化層之製造方法，係在製造淺溝 渠隔離結停的過程中，使塡充於溝渠之中的絕緣層可以延 伸覆蓋溝渠頂角周圍之區域，然後再以其作爲自對準植入 罩幕，僅在除淺溝渠隔離頂角部分外的其他部分植入氮， 以降低其氧化成長速率，使後續所形成之閘氧化層在除淺 溝渠隔離頂角部分外的其他部分淺溝渠隔離頂角部分厚度 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476137 6614twf. doc/006 A7 B7 五、發明說明（ο ) 較其他部分薄。而不需額外之微影蝕刻步驟，可減少生產 花費，並且不會因傳統之淺溝渠隔離之罩幕層後退（pull back)製程’而造成主動區域變小，可利用在系統晶片（System on Chip，SOC)上。 另外，本發明係在淺溝渠隔離頂角部分形成較其他部 分厚之閘氧化層。在淺溝渠隔離頂角部分成長較厚之氧化 層，可防止因淺溝渠隔離頂角（Top Edge Corner)部分導致 之寄生元件傳導，即產生|它峰效應(Hump effect)。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 裝 -線· 硬齋grti犲查笱員1_消費^阼达卬製 9 本紙張尺度適用中國國家標準（CNS)A，1規格（210 X 297公釐）Please read the note before filling in this page. I should be III. The paper size is applicable to the Chinese National Standard (CNS) A4 (210 ^ 297 mm) 476137 6614twf.doc / 006 A7 B7 V. Description of the invention (6) low. The dopant is, for example, nitrogen. The method of implantation includes ion implantation. The energy is 5 to 10 仟 electron volts, and the implantation dose is about 5x 1014 / cm 2 to lx 1015 / (Please read the precautions on the back before filling this page. ) Square centimeters. Referring to FIG. 1F, a part of the insulating layer 150 and the pad oxidation layer 110 are removed to expose the surface of the substrate 100. The surface of the exposed substrate 100 includes the surface of the trench surrounding corner 140 and the surface of the doped region 160. Methods for removing a portion of the insulating layer 150 and the pad oxide layer 110 include isotropic etching such as wet etching. The substrate 100 is used as an etching stop layer, and the hydrofluoric acid solution is used as an etching solution for wet etching until the surface of the substrate 100 is exposed. --Line- Referring to FIG. 1G, silicon oxide is grown on the substrate 100 including the surface 140 around the trench apex angle and the surface of the doped region 160 because no dopants are implanted around the trench apex angle portion 140. The doped region 160 is implanted with a dopant that slows down the oxidation rate. Therefore, the surface of the portion 140 around the apex of the trench is oxidized to grow silicon oxide faster than the surface of the doped region 160. Therefore, a gate oxide layer 170 having a thicker portion 140 around the apex of the trench and a thinner portion of the doped region 160 is formed. The method for forming the gate oxide layer 170 includes a thermal oxidation method. The invention provides a method for manufacturing a gate oxide layer. In the process of manufacturing a shallow trench isolation junction, the insulating layer filled in the trench can extend to cover the area around the top corner of the trench, and then use it as a self-alignment. In the quasi-implantation mask, nitrogen is implanted only in the portion except the shallow trench isolation apex portion to reduce its oxidation growth rate, so that the subsequently formed gate oxide layer is in the other portions except the shallow trench isolation apex portion. Shallow trench isolation apex corner thickness 8 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 476137 6614twf. Doc / 006 A7 B7 5. Description of the invention (ο) Thinner than other parts. No additional lithography etching steps are required, which can reduce production costs, and will not cause the active area to be reduced due to the traditional pull back process of the shallow trench isolation. It can be used in the system on chip Chip, SOC). In addition, the present invention forms a gate oxide layer thicker at the top corner portion of the shallow trench isolation than at other portions. Growing a thicker oxide layer in the shallow trench isolation apex corner can prevent parasitic element conduction caused by the shallow trench isolation apex corner (Hump effect). Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling in this page.) Packing-line · Hard-tied grti 犲 Checker 1_Consumer ^ 阼 阼 9 9 This paper size applies to China National Standard (CNS) A, 1 specifications (210 X 297 mm)