WO1999007012A1 - Process for manufacturing integrated mos circuits - Google Patents

Process for manufacturing integrated mos circuits Download PDF

Info

Publication number
WO1999007012A1
WO1999007012A1 PCT/DE1998/002140 DE9802140W WO9907012A1 WO 1999007012 A1 WO1999007012 A1 WO 1999007012A1 DE 9802140 W DE9802140 W DE 9802140W WO 9907012 A1 WO9907012 A1 WO 9907012A1
Authority
WO
WIPO (PCT)
Prior art keywords
polysilicon
oxide
gate
layer
pbl
Prior art date
Application number
PCT/DE1998/002140
Other languages
German (de)
French (fr)
Inventor
Martin Kerber
Dietrich Widmann
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1999007012A1 publication Critical patent/WO1999007012A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects

Definitions

  • the invention relates to a method for producing integrated MOS circuits, in which a PBL process is used.
  • LOCOS technology Local Oxidation of Silicon
  • PB polysilicon-buffered-LOCOS
  • a layer sequence of pad oxide which consists of a thermal oxide, polysilicon and nitride, is applied to a substrate.
  • a resist mask for defining the active areas is applied to this triple layer, which is typical for the PBL process.
  • the nitride typically silicon nitride (SiN 4 )
  • SiN 4 silicon nitride
  • the LOCOS oxidation to generate the field oxide then takes place outside the active areas marked with the mask. Then the nitride layer is stripped in the area of the active areas. Then be stripped the polysilicon layer and the pad oxide, which have been applied as auxiliary layers for the PBL process.
  • the field oxide is also thinned. This is followed by thermal oxidation to oxidize the nitride-like layer (Kooi layer). When this oxide layer is removed, the field oxide is further thinned. Subsequently, a scattering oxide is usually thermally grown, through which the implantation of boron for U th adaptation takes place. The scatter oxide is also stripped again. After these steps, the gate oxide is then cleaned and oxidized, and a polysilicon layer is deposited and doped. A resist mask for defining the gate polysilicon structures is applied thereon and anisotropic etching of the polysilicon is carried out. The field implantations that may be required in this process have not been taken into account.
  • the invention addresses the problem of creating a method for producing an integrated MOS circuit, in which a PBL process is used and a field oxide and a gate oxide are generated, with which particularly simple process control is possible.
  • the object is achieved in that an oxide layer produced in the PBL process is used as the gate oxide.
  • the gate oxidation is carried out before the field oxidation.
  • the field oxidation takes place within the LOCOS process.
  • the gate oxide can be almost perfect surface of the entire surface can be carried out, which is not yet exposed to mechanical stresses due to the thick field oxide layer that is created during the field oxidation.
  • the numerous oxidation processes cause an increasingly rough surface, which deteriorates the quality of the gate oxide.
  • a first thermal oxide of the manufacturing process is particularly preferably used as the gate oxide. This means that a high-quality oxide is used, which is produced particularly early in the process.
  • a polysilicon layer deposited in the PBL process at least partially as gate polysilicon. It is particularly advantageous if the polysilicon layer deposited in the PBL process can be used overall as gate polysilicon, since a particularly extensive process simplification can be achieved in this way, since it would otherwise only be used as an auxiliary layer in a standard PBL process applied polysilicon layer can be fully integrated into the process according to the invention and thus a removal and a later re-application of
  • Polysilicon can at least partially be omitted.
  • a further polysilicon layer is deposited on the polysilicon layer deposited in the PBL process in order to form the gate polysilicon.
  • the further polysilicon layer is also possible for the further polysilicon layer to produce a gate polysilicon with a flat, planar surface over the entire wafer. Further structures can be applied particularly simply to such a planar surface in the following process steps. This is achieved by means of the overall process according to the invention, in which the oxide and polysilicon layers which are otherwise used as auxiliary layers in standard PBL processes are integrated into the process and thereby already enable a largely flat substructure, to which the further one is then Polysilicon layer is applied to form a flat surface.
  • the method according to the invention is advantageously used in a CMOS process.
  • the polysilicon deposited in the PBL process is used as a floating gate, in particular in an EEPROM memory cell.
  • nitrided oxide or an oxide-nitride layer is preferably used as the nitride layer in the PBL process.
  • This nitrided oxide layer used as the nitride layer or the oxide nitride layer serves as an insulation layer between the floating gate and a control gate.
  • the area of the storage cells is covered by a resist mask during nitride stripping. The resulting completely insulated polysilicon, which was deposited during the PBL process, can then be used as a floating gate in addition to its function in the LOCOS process.
  • Figures 1 to 5 are a plan view and various cross sections of a MOS transistor according to the invention with its surroundings in an earlier process stage;
  • Figure 1 is a plan view of an active area
  • Figure 2 is a section along A-A 'in Figure 1;
  • FIG. 3 shows a section along the line BB 'in Figure 1 after the LOCOS oxidation
  • FIG. 4 shows a section along line BB ′ in FIG. 1 after nitride stripping
  • Figures 6 to 9 are a plan view and various cross sections of a MOS transistor according to the invention with its surroundings after the structuring of the gate polysilicon;
  • Figure 6 is a top view of the active area
  • Figure 7 is a section along the line B-B 'of Figure 6;
  • FIG. 1 shows a top view of an active region 1 after the LOCOS oxidation.
  • FIG. 2 shows a cross section along the line AA ′ of FIG. 1 through the active region 1.
  • the substrate 2 which consists of monocrystalline silicon, lies at the bottom in the cross section.
  • a photoresist mask, which masks the active area 1, is then applied in the area of the active area 1. Outside the resist mask, ie outside the active region 1, an anisotropic nitride etching takes place, in which the nitride layer is removed, so that the underlying polysilicon layer 4 is exposed.
  • Fig. 3 is a section along the line BB 'in Fig. 1.
  • LOCOS oxidation an oxide nitride is formed on the top of the nitride layer, which is etched isotropically.
  • the field oxide regions 5 are thinned during this and during the subsequent complete nitride stripping. This process status is shown in FIG. 4.
  • FIG. 6 shows a plan view of an active region 1 of a MOS transistor produced using the method according to the invention, with its surroundings in the further course of the method.
  • FIG. 9 shows this polysilicon layer 7, FIG. 9 representing a cross section along the line AA ′ in FIG. 6.
  • This further polysilicon layer 7 has a flat surface, on which further structures can optionally be produced particularly cheaply.
  • Structure is made possible by including the polysilicon layer 4 deposited during the PBL process in the gate polysilicon.
  • a further resist mask 8 for defining the gate polysilicon structures is then applied, which is shown in broken lines in FIG. 6.
  • An anisotropic etching of the polysilicon then takes place, with both the polysilicon from the further polysilicon layer 7 and the polysilicon from the first deposited polysilicon layer 4 being removed unless they are covered by the resist mask 8.
  • 8 is a cross section 6 along line CC from FIG.
  • FIG. 7 shows a section along the line BB ′ in FIG. 6, in which the gate polysilicon structure is particularly clear.
  • the pad oxide 3, which consists of SiO 2 is continuously present on the substrate 2 in the active region 1, and a polysilicon structure is formed thereon in the area that has in the meantime been covered by the resist mask 8 the polysilicon 4 initially deposited as part of the PBL process and in the upper two thirds of the later deposited polysilicon of the further polysilicon layer 7.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Non-Volatile Memory (AREA)

Abstract

In a process for manufacturing MOS circuits, a PBL (polysilicon-buffered-LOCOS) process is simplified in that the pad oxide (3) precipitated during the PBL process is used as gate oxide. In addition, the polysilicon layer (4) precipitated during the PBL process is used as part of the gate polysilicon.

Description

Beschreibungdescription
Verfahren zur Herstellung von integrierten MOS-SchaltungenProcess for the production of integrated MOS circuits
Die Erfindung betrifft ein Verfahren zur Herstellung von integrierten MOS-Schaltungen, bei dem ein PBL-Prozeß angewendet wird.The invention relates to a method for producing integrated MOS circuits, in which a PBL process is used.
Eine bei der Herstellung von integrierten MOS-Schaltungen, insbesondere CMOS-Schaltungen, in großem Umfang genutzteOne widely used in the manufacture of integrated MOS circuits, particularly CMOS circuits
Technologie ist die LOCOS-Technik (Local Oxidation of Silicon) . Mit einer solchen lokalen Oxidation von Silizium ist es möglich, dicke Feldoxidbereiche mit einer selbstjustierten erhöhten Felddotierung zu erzeugen, mit denen in integrierten MOS-Schaltungen die aktiven Bereiche abgegrenzt werden. Ein bei der LOCOS-Technik entstehender Obergangsbereich zwischen dem Feldoxid und dem aktiven Gebiet weist eine Stufe auf, die aufgrund ihres typischen Profils auch als Vogelschnabel (Bird's beak) bezeichnet wird. Zur Verkürzung dieses Vogel- Schnabels, der wertvolle aktive Fläche belegt, ist die Poly- silizium gepufferte LOCOS-Technik eingeführt worden, die im folgenden als PB (Polysilicon-Buffered-LOCOS) -Prozeß bezeichnet wird.Technology is LOCOS technology (Local Oxidation of Silicon). With such a local oxidation of silicon, it is possible to produce thick field oxide regions with a self-aligned increased field doping, with which the active regions are delimited in integrated MOS circuits. A transition area between the field oxide and the active area that occurs in the LOCOS technology has a step that is also referred to as a bird's beak due to its typical profile. To shorten this bird's beak, which occupies valuable active area, the polysilicon-buffered LOCOS technology has been introduced, which is referred to below as the PB (polysilicon-buffered-LOCOS) process.
Beim PBL-Prozeß wird auf ein Substrat eine Schichtfolge aus Padoxid, welches aus einem thermischen Oxid besteht, Polysi- lizium und Nitrid aufgebracht. Auf diese für den PBL-Prozeß typische Dreifach-Schicht wird eine Resistmaske zur Definition der aktiven Gebiete aufgebracht. Außerhalb der aktiven Ge- biete, die nicht durch die Resistmaske abgedeckt sind, wird das Nitrid, wobei typischerweise Siliziumnitrid (SiN4) eingesetzt wird, anisotrop geätzt. Danach erfolgt außerhalb der mit der Maske markierten aktiven Gebiete die LOCOS-Oxidation zur Erzeugung des Feldoxids. Danach wird im Bereich der akti- ven Gebiete die Nitridschicht gestrippt. Anschließend werden die Polysiliziumschicht und das Padoxid gestrippt, die als Hilfsschichten für den PBL-Prozeß aufgebracht worden sind. Beim Strippen des Padoxids wird auch das Feldoxid gedünnt . Danach erfolgt eine thermische Oxidation zur Aufoxidation der nitridartigen Schicht (Kooi-Schicht) . Beim Entfernen dieser Oxidschicht wird das Feldoxid weiter gedünnt. Anschließend wird üblicherweise ein Streuoxid thermisch gewachsen, durch das die Implantierung von Bor zur Uth-Anpassung erfolgt. Das Streuoxid wird ebenfalls wieder gestrippt. Nach diesen Schritten folgt dann die Reinigung und Oxidation des Gateoxids sowie eine Abscheidung und Dotierung einer Polysiliziumschicht. Darauf wird eine Resistmaske zur Definition der Gate-Polysiliziu strukturen aufgebracht und eine anisotrope Ätzung des Polysiliziums durchgeführt. Die bei diesem Prozeß eventuell erforderlichen Feldimplantationen sind nicht berücksichtigt worden.In the PBL process, a layer sequence of pad oxide, which consists of a thermal oxide, polysilicon and nitride, is applied to a substrate. A resist mask for defining the active areas is applied to this triple layer, which is typical for the PBL process. Outside the active areas, which are not covered by the resist mask, the nitride, typically silicon nitride (SiN 4 ), is anisotropically etched. The LOCOS oxidation to generate the field oxide then takes place outside the active areas marked with the mask. Then the nitride layer is stripped in the area of the active areas. Then be stripped the polysilicon layer and the pad oxide, which have been applied as auxiliary layers for the PBL process. When the pad oxide is stripped, the field oxide is also thinned. This is followed by thermal oxidation to oxidize the nitride-like layer (Kooi layer). When this oxide layer is removed, the field oxide is further thinned. Subsequently, a scattering oxide is usually thermally grown, through which the implantation of boron for U th adaptation takes place. The scatter oxide is also stripped again. After these steps, the gate oxide is then cleaned and oxidized, and a polysilicon layer is deposited and doped. A resist mask for defining the gate polysilicon structures is applied thereon and anisotropic etching of the polysilicon is carried out. The field implantations that may be required in this process have not been taken into account.
Der Erfindung stellt sich die A u f g a b e, ein Verfahren zur Herstellung einer integrierten MOS-Schaltung, bei dem ein PBL-Prozeß angewendet und ein Feldoxid und ein Gateoxid erzeugt werden, zu schaffen, mit dem eine besonders einfache Prozeßführung möglich ist.The invention addresses the problem of creating a method for producing an integrated MOS circuit, in which a PBL process is used and a field oxide and a gate oxide are generated, with which particularly simple process control is possible.
Erfindungsgemäß wird die Aufgabe dadurch gelöst, daß eine im PBL-Prozeß erzeugte Oxidschicht als Gateoxid verwendet wird. Dadurch wird der PBL-Prozeß wesentlich vereinfacht, weil die sonst nur als Hilfsschicht aufgebrachte Padoxidschicht direkt als Gateoxid genutzt wird und dadurch ein Strippen des Padoxids und eine neue Erzeugung des Gateoxids und die damit verbundenen zusätzlichen Verfahrensschritte entfallen können.According to the invention, the object is achieved in that an oxide layer produced in the PBL process is used as the gate oxide. This greatly simplifies the PBL process, because the pad oxide layer, which is otherwise only applied as an auxiliary layer, is used directly as gate oxide, so that stripping of the pad oxide and new generation of the gate oxide and the associated additional process steps can be dispensed with.
Dabei ist es insbesondere günstig, daß die Gateoxidation vor der Feldoxidation durchgeführt wird. Die Feldoxidation erfolgt innerhalb des LOCOS-Prozesses . Durch die frühe Durch- führung der Gateoxidation kann das Gateoxid auf einer nahezu perfekten Oberfläche des gesamten afers durchgeführt werden, die noch nicht durch die dicke Feldoxidschicht, die bei der Feldoxidation entsteht, mechanischen Spannungen ausgesetzt ist. Weiterhin verursachen die zahlreichen Oxidationsprozesse eine zunehmend rauhe Oberfläche, die die Qualität des Gateoxids verschlechtert. Besonders bevorzugt wird als Gateoxid ein erstes thermisches Oxid des Herstellungsprozesses verwendet. Dadurch wird ein qualitativ hochwertiges Oxid verwendet, das besonders früh im Prozeß hergestellt wird.It is particularly advantageous that the gate oxidation is carried out before the field oxidation. The field oxidation takes place within the LOCOS process. By performing the gate oxidation early, the gate oxide can be almost perfect surface of the entire surface can be carried out, which is not yet exposed to mechanical stresses due to the thick field oxide layer that is created during the field oxidation. Furthermore, the numerous oxidation processes cause an increasingly rough surface, which deteriorates the quality of the gate oxide. A first thermal oxide of the manufacturing process is particularly preferably used as the gate oxide. This means that a high-quality oxide is used, which is produced particularly early in the process.
Weiterhin ist es bevorzugt, eine beim PBL-Prozeß abgeschiedene Polysiliziumschicht zumindest teilweise als Gate-Poly- silizium zu verwenden. Besonders günstig ist es dabei, wenn die beim PBL-Prozeß abgeschiedene Polysiliziumschicht insge- samt als Gate-Polysilizium verwendet werden kann, da auf diese Weise eine besonders weitgehende Prozeßvereinfachung erreicht werden kann, da die sonst in einem Standard-PBL-Prozeß lediglich als Hilfsschicht aufgebrachte Polysiliziumschicht vollständig in den erfindungsgemäßen Prozeß integriert werden kann und so ein Entfernen und ein späteres Neuaufbringen vonFurthermore, it is preferred to use a polysilicon layer deposited in the PBL process at least partially as gate polysilicon. It is particularly advantageous if the polysilicon layer deposited in the PBL process can be used overall as gate polysilicon, since a particularly extensive process simplification can be achieved in this way, since it would otherwise only be used as an auxiliary layer in a standard PBL process applied polysilicon layer can be fully integrated into the process according to the invention and thus a removal and a later re-application of
Polysilizium zumindest teilweise entfallen kann. In einer Weiterbildung dieses Verfahrensschrittes wird zur Bildung des Gate-Polysiliziums auf die beim PBL-Prozeß abgeschiedene Polysiliziumschicht eine weitere Polysiliziumschicht abgeschie- den. Dabei ist es auch möglich, daß durch die weitere Polysiliziumschicht über den gesamten Wafer ein Gate-Polysilizium mit einer ebenen, planaren Oberfläche erzeugt wird. Auf eine derartige planare Oberfläche können in folgenden Prozeßschritten weitere Strukturen besonders einfach aufgebracht werden. Erreicht wird dies durch den erfindungsgemäßen Gesamtprozeß, in dem die sonst in Standard-PBL-Prozessen als Hilfsschichten verwendeten Oxid- und Polysiliziumschichten in den Prozeß integriert werden und dadurch schon einen weitgehend ebenen Unterbau ermöglichen, auf den dann die weitere Polysiliziumschicht zur Bildung einer ebenen Oberfläche aufgebracht wird.Polysilicon can at least partially be omitted. In a development of this method step, a further polysilicon layer is deposited on the polysilicon layer deposited in the PBL process in order to form the gate polysilicon. It is also possible for the further polysilicon layer to produce a gate polysilicon with a flat, planar surface over the entire wafer. Further structures can be applied particularly simply to such a planar surface in the following process steps. This is achieved by means of the overall process according to the invention, in which the oxide and polysilicon layers which are otherwise used as auxiliary layers in standard PBL processes are integrated into the process and thereby already enable a largely flat substructure, to which the further one is then Polysilicon layer is applied to form a flat surface.
Günstigerweise wird das erfindungsgemäße Verfahren in einem CMOS-Prozeß eingesetzt. In einer anderen bevorzugten Anwendungsvariante wird das beim PBL-Prozeß abgeschiedene Polysi- lizium als Floating-Gate, insbesondere in einer EEPROM- Speicherzelle, verwendet. In diesem Fall wird beim PBL-Prozeß als Nitridschicht bevorzugt nitridiertes Oxid oder eine Oxid- Nitridschicht verwendet. Diese als Nitridschicht eingesetzte nitridierte Oxidschicht oder die Oxid-Nitridschicht dient als Isolationsschicht zwischen dem Floating-Gate und einem Con- trol-Gate. Bei dieser Anwendung des erfindungsgemäßen Verfahrens wird beim Nitrid-Strippen der Bereich der Speicherzellen durch eine Lackmaske abgedeckt. Das dabei entstehende ringsum vollständig isolierte Polysilizium, welches beim PBL-Prozeß abgeschieden worden ist, kann dann neben seiner Funktion im LOCOS-Verfahren gleichzeitig als Floating-Gate eingesetzt werden .The method according to the invention is advantageously used in a CMOS process. In another preferred application variant, the polysilicon deposited in the PBL process is used as a floating gate, in particular in an EEPROM memory cell. In this case, nitrided oxide or an oxide-nitride layer is preferably used as the nitride layer in the PBL process. This nitrided oxide layer used as the nitride layer or the oxide nitride layer serves as an insulation layer between the floating gate and a control gate. In this application of the method according to the invention, the area of the storage cells is covered by a resist mask during nitride stripping. The resulting completely insulated polysilicon, which was deposited during the PBL process, can then be used as a floating gate in addition to its function in the LOCOS process.
Nachfolgend wird die Erfindung anhand eines in der Zeichnung dargestellten bevorzugten Ausführungsbeispiels weiter erläutert. Im einzelnen zeigen die schematischen Darstellungen inThe invention is explained in more detail below on the basis of a preferred exemplary embodiment shown in the drawing. The schematic representations in detail in
Figuren 1 bis 5 eine Draufsicht und verschiedene Querschnitte eines erfindungsgemäßen MOS-Transistors mit seiner Umgebung in einem früheren Verfahrensstadium; mitFigures 1 to 5 are a plan view and various cross sections of a MOS transistor according to the invention with its surroundings in an earlier process stage; With
Figur 1 einer Draufsicht auf ein aktives Gebiet;Figure 1 is a plan view of an active area;
Figur 2 einen Schnitt entlang A-A' in Fig. 1;Figure 2 is a section along A-A 'in Figure 1;
Figur 3 einen Schnitt entlang der Linie B-B' in Figur 1 nach der LOCOS-Oxidation; Figur 4 einen Schnitt entlang der Linie B-B' in Figur 1 nach dem Nitrid-Strippen;3 shows a section along the line BB 'in Figure 1 after the LOCOS oxidation; FIG. 4 shows a section along line BB ′ in FIG. 1 after nitride stripping;
Figur 5 einen Schnitt entlang der Linie B-B1 in Figur 1 nach Si02-Rückätzung;5 shows a section along line BB 1 in FIG. 1 after Si0 2 etching back;
Figuren 6 bis 9 eine Draufsicht und verschiedene Querschnitte eines erfindungsgemäßen MOS-Transistors mit seiner Umgebung nach der Strukturierung des Gate-Polysiliziums; mitFigures 6 to 9 are a plan view and various cross sections of a MOS transistor according to the invention with its surroundings after the structuring of the gate polysilicon; With
Figur 6 einer Draufsicht auf das aktive Gebiet;Figure 6 is a top view of the active area;
Figur 7 einem Schnitt entlang der Linie B-B' der Figur 6;Figure 7 is a section along the line B-B 'of Figure 6;
Fig. 8 einem Schnitt entlang der Linie C-C ' der Figur 6; und8 shows a section along the line C-C 'of FIG. 6; and
Fig. 9 einem Schnitt entlang der Linie A-A' der Figur 6.9 shows a section along the line A-A 'of FIG. 6.
In Fig. 1 ist eine Draufsicht auf ein aktives Gebiet 1 nach der LOCOS-Oxidation dargestellt. In Fig. 2 ist ein Querschnitt entlang der Linie A-A' der Fig. 1 durch das aktive Gebiet 1 dargestellt. In dem Querschnitt liegt zuunterst das Substrat 2, das aus monokristallinem Silizium besteht. Auf das Substrat 2 wird die für den PBL-Prozeß typische Dreifach- Schichtfolge von Padoxid 3, Polysilizium 4 und Nitrid aufgebracht. Danach wird im Bereich des aktiven Gebietes 1 eine Fotoresistmaske aufgebracht, die das aktive Gebiet 1 maskiert. Außerhalb der Resistmaske, also außerhalb des aktiven Gebiets 1, erfolgt eine anisotrope Nitridätzung, bei der die Nitridschicht entfernt wird, so daß die darunterliegende Polysiliziumschicht 4 freiliegt. Die Resistmaske wird dann entfernt und eine LOCOS-Oxidation zur Erzeugung des Feldoxids (Si02) durchgeführt. Dieser Verfahrensstand mit den gedickten Feldoxidbereichen 5, die aus der oxidierten Polysilizium- Schicht 4 hervorgegangen sind, und dem verbliebenen Nitrid 6 im Bereich des aktiven Gebiets 1 ist in Fig. 3 dargestellt. Fig. 3 ist ein Schnitt entlang der Linie B-B' in Fig. 1. Bei der LOCOS-Oxidation entsteht an der Oberseite der Nitridschicht ein Oxidnitrid, welches isotrop geätzt wird. Dabei und beim anschließenden vollständigen Nitrid-Strippen werden die Feldoxidbereiche 5 gedünnt. Dieser Verfahrensstand ist in Fig. 4 dargestellt.1 shows a top view of an active region 1 after the LOCOS oxidation. FIG. 2 shows a cross section along the line AA ′ of FIG. 1 through the active region 1. The substrate 2, which consists of monocrystalline silicon, lies at the bottom in the cross section. The triple layer sequence of pad oxide 3, polysilicon 4 and nitride, which is typical for the PBL process, is applied to the substrate 2. A photoresist mask, which masks the active area 1, is then applied in the area of the active area 1. Outside the resist mask, ie outside the active region 1, an anisotropic nitride etching takes place, in which the nitride layer is removed, so that the underlying polysilicon layer 4 is exposed. The resist mask is then removed and LOCOS oxidation is carried out to produce the field oxide (Si0 2 ). This state of the art with the thickened field oxide regions 5, which have arisen from the oxidized polysilicon layer 4, and the remaining nitride 6 in the area of active area 1 is shown in FIG. 3. Fig. 3 is a section along the line BB 'in Fig. 1. In LOCOS oxidation, an oxide nitride is formed on the top of the nitride layer, which is etched isotropically. The field oxide regions 5 are thinned during this and during the subsequent complete nitride stripping. This process status is shown in FIG. 4.
Danach erfolgt eine weitere Rückätzung des Feldoxids 5, das aus Si02 besteht, bis herunter zu dem Polysilizium 4 in dem aktiven Gebiet 1. Dieser Verfahrensstand ist in Fig. 5 dargestellt.This is followed by a further etching back of the field oxide 5, which consists of SiO 2 , down to the polysilicon 4 in the active region 1. This process status is shown in FIG.
Der weitere Verfahrensablauf wird anhand der Fig. 6 bis 9 be- schrieben. In Fig. 6 ist eine Draufsicht auf ein aktives Gebiet 1 eines mit dem erfindungsgemäßen Verfahren hergestellten MOS-Transistors mit seiner Umgebung im weiteren Verfahrensablauf dargestellt.The further process sequence is described with reference to FIGS. 6 to 9. FIG. 6 shows a plan view of an active region 1 of a MOS transistor produced using the method according to the invention, with its surroundings in the further course of the method.
Zunächst wird eine weitere Polysiliziumschicht 7 abgeschieden und n+-dotiert. Fig. 9 zeigt diese Poly-Siliziumschicht 7, wobei die Fig. 9 einen Querschnitt entlang der Linie A-A' in Fig. 6 darstellt. Diese weitere Polysiliziumschicht 7 weist eine ebene Oberfläche auf, auf der gegebenenfalls besonders günstig weitere Strukturen erzeugt werden können. DieseFirst, a further polysilicon layer 7 is deposited and n + -doped. FIG. 9 shows this polysilicon layer 7, FIG. 9 representing a cross section along the line AA ′ in FIG. 6. This further polysilicon layer 7 has a flat surface, on which further structures can optionally be produced particularly cheaply. This
Struktur wird durch die Einbeziehung der während des PBL- Prozesses abgeschiedenen Polysiliziumschicht 4 in das Gate- Polysilizium möglich. Anschließend wird eine weitere Resistmaske 8 zur Definition der Gate-Polysilizumstrukturen aufgebracht, die in Fig. 6 gestrichelt dargestellt ist. Es erfolgt dann eine anisotrope Ätzung des Polysiliziu s, wobei sowohl das Polysilizium aus der weiteren Polysiliziumschicht 7 als auch das Polysilizium aus der zuerst abgeschiedenen Polysiliziumschicht 4 entfernt werden, sofern sie nicht von der Resistmaske 8 abgedeckt sind. In Fig. 8 ist ein Querschnitt entlang der Linie C-C von' Fig. 6 dargestellt, aus dem auch deutlich wird, daß das Polysilizium außerhalb der Resistmaske 8 entfernt worden ist, so daß dort lediglich außerhalb des aktiven Gebiets 1 die dickeren Feld- oxidbereiche (Si02) und innerhalb des aktiven Gebiets 1 das ursprünglich aufgebrachte Padoxid 3 verbleibt, welches ebenfalls aus Si02 besteht. In Fig. 7 ist ein Schnitt entlang der Linie B-B' in Fig. 6 dargestellt, in dem die Gate-Polysili- ziumstruktur besonders deutlich wird. Auf dem Substrat 2 be- findet sich im aktiven Gebiet 1 durchgängig das Padoxid 3, welches aus Si02 besteht, und darauf ist im Bereich, der zwischenzeitlich von der Resistmaske 8 abgedeckt war, eine Poly- siliziumstruktur entstanden, die in ihrem unteren Drittel aus dem zunächst im Rahmen des PBL-Prozesses abgeschiedenen Poly- silizium 4 und in den oberen zwei Dritteln aus dem später abgeschiedenen Polysilizium der weiteren Polysiliziumschicht 7 besteht . Structure is made possible by including the polysilicon layer 4 deposited during the PBL process in the gate polysilicon. A further resist mask 8 for defining the gate polysilicon structures is then applied, which is shown in broken lines in FIG. 6. An anisotropic etching of the polysilicon then takes place, with both the polysilicon from the further polysilicon layer 7 and the polysilicon from the first deposited polysilicon layer 4 being removed unless they are covered by the resist mask 8. 8 is a cross section 6 along line CC from FIG. 6, from which it is also clear that the polysilicon outside the resist mask 8 has been removed, so that the thicker field oxide regions (SiO 2 ) and inside the active region only exist outside the active region 1 Area 1, the originally applied pad oxide 3 remains, which also consists of Si0 2 . FIG. 7 shows a section along the line BB ′ in FIG. 6, in which the gate polysilicon structure is particularly clear. The pad oxide 3, which consists of SiO 2, is continuously present on the substrate 2 in the active region 1, and a polysilicon structure is formed thereon in the area that has in the meantime been covered by the resist mask 8 the polysilicon 4 initially deposited as part of the PBL process and in the upper two thirds of the later deposited polysilicon of the further polysilicon layer 7.

Claims

Patentansprüche claims
1. Verfahren zur Herstellung einer integrierten MOS-Schaltung bei dem ein PBL (Polysilicon-Buffered-LOCOS) -Prozeß angewendet wird, d a d u r c h g e k e n n z e i c h n e t , daß ein beim PBL-Prozeß abgeschiedenes Padoxid als Gateoxid verwendet wird.1. A method for producing an integrated MOS circuit in which a PBL (polysilicon-buffered-LOCOS) process is used, so that a pad oxide deposited in the PBL process is used as the gate oxide.
2. Verfahren nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß erst das Gateoxid und dann ein Feldoxid erzeugt wird.2. The method of claim 1, d a d u r c h g e k e n n z e i c h n e t that first the gate oxide and then a field oxide is generated.
3. Verfahren nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t , daß als Gateoxid ein erstes thermisches Oxid des Herstellungsprozesses verwendet wird.3. The method according to any one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that a first thermal oxide of the manufacturing process is used as gate oxide.
4. Verfahren nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t , daß eine beim PBL-Prozeß abgeschiedene Polysiliziumschicht zumindest teilweise als Gate-Polysilizium verwendet wird.4. The method according to any one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that a polysilicon layer deposited in the PBL process is at least partially used as gate polysilicon.
5. Verfahren nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t , daß zur Bildung des Gate-Polysilizium auf die beim PBL-Prozeß abgeschiedene Polysiliziumschicht eine weitere Polysiliziumschicht abgeschieden wird.5. The method according to any one of the preceding claims, that a further polysilicon layer is deposited on the polysilicon layer deposited during the PBL process in order to form the gate polysilicon.
6. Verfahren nach Anspruch 5, d a d u r c h g e k e n n z e i c h n e t , daß die weitere Polysiliziumschicht etwa mit der doppelten Dicke wie die beim PBL-Prozeß abgeschiedene Polysiliziumschicht erzeugt wird. 6. The method according to claim 5, characterized in that the further polysilicon layer is produced approximately twice as thick as the polysilicon layer deposited in the PBL process.
7. Verfahren nach einem der' Ansprüche 5 oder 6, d a d u r c h g e k e n n z e i c h n e t , daß durch die weitere Polysiliziumschicht über den gesamten Wafer ein Gate-Polysilizium mit ebener Oberfläche erzeugt wird.7. The method according to any one of ' claims 5 or 6, characterized in that a gate polysilicon with a flat surface is generated by the further polysilicon layer over the entire wafer.
8. Verfahren nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t , daß das Verfahren bei einem CMOS-Prozeß eingesetzt wird.8. The method according to any one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the method is used in a CMOS process.
9. Verfahren nach einem der Ansprüche 1 bis 5, d a d u r c h g e k e n n z e i c h n e t , daß die beim PBL-Prozeß abgeschiedene Polysiliziumschicht als Floating-Gate verwendet wird.9. The method according to any one of claims 1 to 5, that the polysilicon layer deposited in the PBL process is used as the floating gate.
10. Verfahren nach Anspruch 9, d a d u r c h g e k e n n z e i c h n e t , daß beim PBL-Prozeß als Nitridschicht nitridiertes Oxid oder eine Oxid-Nitridschicht verwendet wird.10. The method of claim 9, d a d u r c h g e k e n n z e i c h n e t that nitrided oxide or an oxide-nitride layer is used as the nitride layer in the PBL process.
11. Verfahren nach einem der Ansprüche 9 oder 10, d a d u r c h g e k e n n z e i c h n e t , daß die als Nitridschicht eingesetzte nitridierte Oxidschicht oder die Oxid-Nitridschicht als Iεolationsschicht zwischen dem Floating-Gate und einem Control-Gate verwendet wird. 11. The method according to any one of claims 9 or 10, so that the nitrided oxide layer used as the nitride layer or the oxide-nitride layer is used as the insulation layer between the floating gate and a control gate.
PCT/DE1998/002140 1997-08-01 1998-07-28 Process for manufacturing integrated mos circuits WO1999007012A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE1997133349 DE19733349A1 (en) 1997-08-01 1997-08-01 Process for the production of integrated MOS circuits
DE19733349.4 1997-08-01

Publications (1)

Publication Number Publication Date
WO1999007012A1 true WO1999007012A1 (en) 1999-02-11

Family

ID=7837726

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1998/002140 WO1999007012A1 (en) 1997-08-01 1998-07-28 Process for manufacturing integrated mos circuits

Country Status (3)

Country Link
DE (1) DE19733349A1 (en)
TW (1) TW415021B (en)
WO (1) WO1999007012A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4214993A1 (en) * 1991-05-07 1992-11-12 Micron Technology Inc Semiconductor disc prepn. - by forming layer of polycrystalline silicon on substrate, forming dielectric by oxidn. of substrate, and then doping
US5358892A (en) * 1993-02-11 1994-10-25 Micron Semiconductor, Inc. Etch stop useful in avoiding substrate pitting with poly buffered locos
US5393694A (en) * 1994-06-15 1995-02-28 Micron Semiconductor, Inc. Advanced process for recessed poly buffered locos
DE4336869A1 (en) * 1993-10-28 1995-05-04 Gold Star Electronics Method for producing an MOS transistor
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652177A (en) * 1996-08-22 1997-07-29 Chartered Semiconductor Manufacturing Pte Ltd Method for fabricating a planar field oxide region

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4214993A1 (en) * 1991-05-07 1992-11-12 Micron Technology Inc Semiconductor disc prepn. - by forming layer of polycrystalline silicon on substrate, forming dielectric by oxidn. of substrate, and then doping
US5358892A (en) * 1993-02-11 1994-10-25 Micron Semiconductor, Inc. Etch stop useful in avoiding substrate pitting with poly buffered locos
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate
DE4336869A1 (en) * 1993-10-28 1995-05-04 Gold Star Electronics Method for producing an MOS transistor
US5393694A (en) * 1994-06-15 1995-02-28 Micron Semiconductor, Inc. Advanced process for recessed poly buffered locos

Also Published As

Publication number Publication date
TW415021B (en) 2000-12-11
DE19733349A1 (en) 1999-02-18

Similar Documents

Publication Publication Date Title
DE69031849T2 (en) Method for leveling topologies for integrated circuits
DE4310954C2 (en) Semiconductor processing method for producing an isolation trench in a substrate
DE69623679T2 (en) Process for producing a trench structure for isolation in an integrated circuit
DE2923995C2 (en) Process for the production of integrated MOS circuits with MOS transistors and MNOS memory transistors in silicon gate technology
DE69231655T2 (en) Method for producing a grab structure in a semiconductor substrate
DE69226987T2 (en) Local connections for integrated circuits
DE4142469B4 (en) Process for the production and removal of temporary silicon dioxide structures
EP0645808A1 (en) Process for manufacturing an isolation trench in a SOI substrate
DE69634675T2 (en) Method for isolating a semiconductor device
DE3841588A1 (en) DYNAMIC VERTICAL SEMICONDUCTOR STORAGE WITH OPTIONAL ACCESS AND METHOD FOR THE PRODUCTION THEREOF
DE10127622A1 (en) Production of HDPCVD oxide-filled insulation trench used in production of integrated circuits comprises forming insulation trench in semiconductor substrate, and forming silicon oxide layers on side walls and on base of trench
DE68916120T2 (en) Method for manufacturing an integrated memory cell.
DE60025991T2 (en) A method of forming a device isolation region
DE10011642C2 (en) Method for producing a shallow trench isolation of a semiconductor device
DE3402825A1 (en) SEMICONDUCTOR ARRANGEMENT WITH INSULATION GROOVE AND PRODUCTION METHOD
EP1019958B1 (en) Method for making a groove structure in a silicon substrate
DE10229346B4 (en) Process for producing a semiconductor element
DE19840385C2 (en) Method for isolating areas of an integrated circuit and semiconductor device with an integrated circuit
DE19853432A1 (en) Semiconductor device and method of manufacturing the same
DE19823742B4 (en) A method of forming an isolation region in a semiconductor substrate
DE3411960A1 (en) METHOD FOR SELF-ALIGNING A DOUBLE LAYER OF POLYCRISTALLINE SILICON BY MEANS OF OXYDATION IN AN INTEGRATED CIRCUIT
WO1999007012A1 (en) Process for manufacturing integrated mos circuits
EP0914678B1 (en) Method of filling trenches in a substrate
DE19856805B4 (en) Trench isolation structure and method of making the same
DE19512148C2 (en) Method for producing a field oxide layer in a semiconductor device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: KR

122 Ep: pct application non-entry in european phase