TWI242647B - Probe for testing flat panel display and manufacturing method thereof - Google Patents

Probe for testing flat panel display and manufacturing method thereof

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Publication number
TWI242647B
TWI242647B TW92132733A TW92132733A TWI242647B TW I242647 B TWI242647 B TW I242647B TW 92132733 A TW92132733 A TW 92132733A TW 92132733 A TW92132733 A TW 92132733A TW I242647 B TWI242647 B TW I242647B
Authority
TW
Taiwan
Prior art keywords
probe
dielectric
sacrificial substrate
substrate
conductors
Prior art date
Application number
TW92132733A
Other languages
Chinese (zh)
Other versions
TW200419159A (en
Inventor
Oug-Ki Lee
Byung-Ho Jo
Chul-Hwan Goo
Yong-Hwi Jo
Sung-Young Oh
Original Assignee
Phicom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR10-2002-0072990A external-priority patent/KR100474420B1/en
Priority claimed from KR10-2002-0082273A external-priority patent/KR100450310B1/en
Priority claimed from KR10-2003-0007654A external-priority patent/KR100517729B1/en
Priority claimed from KR1020030065988A external-priority patent/KR100554180B1/en
Application filed by Phicom Corp filed Critical Phicom Corp
Publication of TW200419159A publication Critical patent/TW200419159A/en
Application granted granted Critical
Publication of TWI242647B publication Critical patent/TWI242647B/en

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/073Multiple probes
    • G01R1/07307Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measuring Leads Or Probes (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)

Abstract

The present invention relates to a probe for testing a flat panel display device, in which a plurality of conductors having a parallel arrangement are stacked between a plurality of other conductors, a probe assembly having the probe, and a method of manufacturing the probe and the probe assembly. The present invention provides a probe for testing a flat panel display device comprising: a plate-like dielectric; a plurality of conductors being provided in parallel; and first trenches being provided on at least one plane of upper and lower planes of the dielectric to fix the plurality of conductors in the dielectric in a predetermined arrangement.

Description

1242647 玫、發明說明: 【發明所屬之技術領域】 本發明係關於與用以測試平 製造方法有關。更特別ut1不4置之探針及其 示器之探針有關,其^行配=明舆用以測試平面板顯 個其它導體間,一探針组且,二複=個導體堆疊於複數 針及該探針組之方法有關:木針,本發明並與製造該探 盆之本1明與用以測試平面板顯示器之探針有 二生產製程期間,無需於—MEMS單元中利用接合 枝黏讀針導體之製程,藉以獲得精確對齊之導體,本發 明並與製造該探針之方法有關。 卜本么明舁用以測試平面板顯示器之探針有關,其 中利用在單-犧牲基板上之MEMS製程,於該單—犧牲基板 之兩平面上形成探針導體,本發明並與製造該探針之方法 有關。 【先前技術】 概言之,TFT-LCD(薄膜電晶體液晶顯示器)裝置係一平面 板顯示器,其包括具預定尺寸之下板,其中具有多個薄膜 私晶體(TFT)及各像素電極;一與該下板間具預定距離之用 以著色之彩色濾波器;一與該下板間具預定距離且依序具 有共用電極之下板;以及介於上下板間之液晶。 該TFT-LCD裝置包括複數個TFT,其係由上下板間之液晶 產生之切換構件、電容器區與輔助電容器區;用以驅動TFT 之ΟΝ/OFF之閘極驅動電極;以及用以施加外部影像信號之1242647 Description of the invention: [Technical field to which the invention belongs] The present invention relates to testing methods for flat manufacturing. More specifically, the ut1 probe is not related to the probe of the indicator, and its ^ line configuration = Mingyu is used to test the plane board between other conductors, a probe group, and two complexes = conductors are stacked in the plural The needle and the method of the probe set are related to: wooden needle, the present invention and the manufacturing method of the probe basin and the probe used for testing the flat panel display. During the production process, there is no need to use a bonding branch in the MEMS unit. The process of sticking a needle conductor to obtain a precisely aligned conductor is related to the method of manufacturing the probe. The prototype is used to test a flat-panel display probe, in which a MEMS process on a single-sacrificial substrate is used to form a probe conductor on two planes of the single-sacrificial substrate. The present invention is also related to manufacturing the probe. Needle-related. [Prior art] In summary, a TFT-LCD (thin film transistor liquid crystal display) device is a flat panel display, which includes a lower panel with a predetermined size, which has a plurality of thin film private crystals (TFT) and pixel electrodes; and A color filter with a predetermined distance between the lower plate for coloring; a lower plate with a predetermined distance from the lower plate and sequentially having a common electrode; and a liquid crystal interposed between the upper and lower plates. The TFT-LCD device includes a plurality of TFTs, which are switching members, capacitor regions and auxiliary capacitor regions generated by liquid crystal between upper and lower plates; gate drive electrodes for driving ON / OFF of the TFTs; and for applying external images Of Signal

O:\89\89662.DOC 1242647 影像信號電極,藉以顯示 此外^ , 、疋心像(包含移動影像)。 、.“木針組與平面板顯示器 衣罝歷 保平面板顯示 *、, 接觸之測試過程,以確 H式/、吊’亚預先剔除不良平面板顯示器。 種類型::用具探針組之探針儀器施行。前已發展出各 探針儀哭/ °探針儀器包含針形探針儀器、剃刀形 儀器。為、㈣形探針儀器,以及mems(微電機系統)探針 =:面板顯示器中之圖案線寬已隨平面板顯示器之高 度積體化而極度銳化。 因此,亟需發展具有優良再產率與高生產率,並且足敷 千面板顯示器之精細間距(piteh)需求之探針組。 【發明内容】 本發明之設計係為符合前階發展需求。本發明之一目的 在於提=、可簡化製程’ i因而縮減製程時間之用以測試平 面板顯不器之探針,及製造該探針之方法。 本發明,另_目的在於提供可在生產製程期間,去除在 -MEMS單元中利用接合機黏著探針導體之製程,並因而獲 得極精確對齊之探針導體之用以測試平面板顯示器之^ 針’及製造该探針之方法。 本|χ月之目的在於提供一種用以測試平面板顯示器之 奴針以及,、衣义方法,藉由針對一單一犧性基板使用 製程,該探針就能夠在—犧性基板上之兩個面板上形成探 針導體。O: \ 89 \ 89662.DOC 1242647 Image signal electrode to display ^,, heart image (including moving image). "." Wooden needle set and flat panel display, clothing, calendar, flat panel display * ,, contact test process to confirm the H-type, hanging, sub-removal of bad flat panel display in advance. Type :: Probe probe set Needle instrument implementation. Various probes have been developed before. The probe probes include needle probe instruments and razor-shaped instruments. Probe probes and mems (micro-motor system) probes =: panel display The line width of the pattern has been extremely sharpened with the high integration of the flat panel display. Therefore, it is urgent to develop a probe that has excellent re-productivity and high productivity, and meets the fine pitch requirements of the thousand-panel display. [Summary of the Invention] The design of the present invention is to meet the requirements of the previous stage of development. One of the objectives of the present invention is to provide a probe for testing the flat panel display device, which can simplify the process, and thus reduce the process time, and A method for manufacturing the probe. The present invention also aims to provide a process capable of removing the process of adhering a probe conductor with a bonding machine in a -MEMS unit during a manufacturing process, and thereby obtaining a probe with extremely precise alignment. Conductor for testing pin of flat-panel display and method for manufacturing the same. The purpose of this month is to provide a pin for testing flat-panel display and a method for fabricating a single pin. The sacrificial substrate uses a manufacturing process, and the probe can form a probe conductor on two panels on the sacrificial substrate.

O:\89\89662.DOC 1242647 /目的’本發明之—態樣提供-種用以測試平面 反’·’、員不态之振針’該顯示器包括一類板狀介電質、複數個 平料體,以及位於該介電質之上下平面中之至少—μ 渠溝’俾以縣配置固定該等複數個導體於該介 本發明之另—態樣提供—㈣以測試平面板顯示器之探 針,該顯示器包括以一預定間隔位於並固定於一薄膜之下 部上之複數個單元接觸組件’其中該薄膜具—預定尺寸 該等單元接觸组件均包括一具桿狀外型之光束構件,及复 中一檢測尖端係以整合方式位於該光束構件之一端上。” 本發明之另—態樣提供—種用以測試平面板顯示器之探 針’該顯示器包括一犧牲基板;利用一微影製程與一姓刻 製程形成之第—渠溝;利用一傳導膜形成製程而以一預定 ^隔位於該犧牲基板上之該等第一渠溝中之導體;一在該 等導體上形成之第一介電質;及利用一微影製程與一蝕;: 以 呈形成之第二渠溝,俾暴露該等導體於一該犧牲基板之 下千面上,一藉由將一介電質材料嵌入該等第二渠溝中而 形成之第二介電質。 另1、樣提供一種使用一單一犧牲基板形成之 、針,包括:-類板狀介電質;及複數個導體,其中的準 溝係由-微影製程與-㈣製程形成’其中一傳導材料嵌 於该等渠溝中,其中該等複數個導體係以_預定間隔位於 该介電質之該等上與下平面上’及其中在該上平面上形成 之该寻導體與在該下平面上形成之該等導體平行。O: \ 89 \ 89662.DOC 1242647 / Purpose 'Invention of the present invention-a kind of sample-a kind of vibration pin to test the plane anti-', 'the display includes a type of plate dielectric, a plurality of flat Material, and at least in the upper and lower planes of the dielectric material, μ trenches, and the plurality of conductors are arranged and fixed in the county to provide another aspect of the present invention, to test the flat panel display. A needle, the display comprising a plurality of unit contact assemblies located at a predetermined interval and fixed on a lower portion of a film, wherein the film has a predetermined size, the unit contact assemblies each include a beam-shaped beam member, and The Fuzhongyi detection tip is located on one end of the beam member in an integrated manner. Another aspect of the present invention provides a probe for testing a flat panel display. The display includes a sacrificial substrate; a first trench formed by a lithography process and a last name engraving process; and a conductive film is formed. A predetermined distance between the conductors in the first trenches on the sacrificial substrate; a first dielectric formed on the conductors; and a lithography process and an etch; and The formed second trenches expose the conductors on a thousand surfaces below the sacrificial substrate, and a second dielectric formed by embedding a dielectric material in the second trenches. 1. The sample provides a needle formed using a single sacrificial substrate, including:-a plate-like dielectric; and a plurality of conductors, wherein the quasi-ditch is formed by a -lithographic process and a ㈣ process-one of the conductive materials Embedded in the trenches, where the plurality of guide systems are located on the upper and lower planes of the dielectric at predetermined intervals, and the seeker conductor formed on the upper plane and the lower plane The conductors formed on them are parallel.

O:\89\89662.DOC 1242647 本叙明之另一態樣提供一種使用—單一犧牲美 探針,包括:一類板狀第一介電質;_ γ之 其在-該第-介電質之上部形成一步階;之:二:電質, 曰左,以一預定P弓H5 配置之複數個導體,以穿透該等第—與第二介電質· ^ 藉由-預定電鍍方法堆疊一傳導材料於各該等:二之―: 面上之傳導層。 平 探另—態樣提供—種使用I —犧牲基板形成之 .,十,匕括.-藉由堆疊-陶£板於—環氧化物之上 平面上而形成之介電質;以一預定間隔於該介電質之該 上與下平面上形成之複數個導體;一 、 检田田田认^ 精由一預定電鍍方法 宜;一 σ該等導體之平面上之傳導層;及堆疊於詨八㊉ ^寺上與下平面上之支撐組件,以固定該等導體之位 r ^發H另—祕提供-種使用—單—犧牲基板形成之 二等:::一類板狀介電質;以-預定間隔於該介電質 X下平面上形成之複數個導體;H預定恭 ::法堆疊於各該等導體之一平面上之傳導層;及堆疊: 體之位置。〃下千面上之支撐組件,以固定該等導 ^另-態樣提供-種製造一用以測試一平面板顯 之木針之方法,包括步驟:一於_介電質之上盜下平 t之至少Γ平面上形成第—渠溝之第一渠溝形成步驟,藉 4以預疋配置固定複數個導體於該介電質上;及一堆聶 一支撑組件於該介電質之—上平面或—下平面上之支^O: \ 89 \ 89662.DOC 1242647 Another aspect of this description provides a use—a single sacrificial beauty probe, including: a type of plate-like first dielectric; _ γ of its presence-the first-dielectric The upper part forms a step; of: two: electric substance, said left, a plurality of conductors arranged with a predetermined P bow H5 to penetrate the first and second dielectrics. ^ By- Conductive materials are in each of these two types: the conductive layer on the surface. Ordinary exploration—provide a kind—use I—form the sacrificial substrate to form it.—Ten, dagger.—A dielectric formed by stacking ceramic plates on an epoxide plane; a predetermined A plurality of conductors formed on the upper and lower planes of the dielectric; one, a field inspection, and a predetermined plating method; a conductive layer on the plane of the conductors; and詨 八 ㊉ ^ The supporting components on the upper and lower planes of the temple to fix the positions of these conductors r ^ H H Another-secret provide-a kind of use-single-sacrificial substrate formation second class ::: a type of plate-shaped dielectric ; A plurality of conductors formed on the lower plane of the dielectric X at a predetermined interval; H predetermined: a conductive layer stacked on one of the planes of each of these conductors; and stacked: the position of the body. The support assembly on the lower surface is used to fix the guides. Another method is to provide a method for manufacturing a wooden needle for testing a flat panel display. A first trench forming step forming a first trench on at least the Γ plane, and a plurality of conductors are fixed on the dielectric in a pre-arranged configuration; and a stack of Nie-support components is on the dielectric. Plane or—support on the lower plane ^

O:\89\89662.DOC 1242647 件形成步驟’藉此固定該等導體 渠溝中。 ’包貝上之該等第一 本發明之另一態樣提供—種 示器之探針之方法,包括.一: M測試一平面板|) 微影製程與一傳導膜"制—導體形成步驟,其係利用-1寻V胰形成製程於一呈一 牲基板之一上平面與_下平面之至,丨疋旱度之單-犧 案,藉以形成導體;_介電…:+面上形成光阻圖 形成光-索,啟一二利= 等導趙之開啟中央部上形成 =i於各邊 苴係剎爾一他π 电貝’一渠溝形成步驟, 肩用-心與一蝕刻製程形 體之該下平面;一 伴路出各忒寺導 , 9 、 支撐組件於該等渠溝中而幵j 成一支撐組件之支撐組件 y 之完結步驟。成”驟,及-移除該犧牲基板 本發明之另一態樣提供一 示器之探針之方法,包括測试一平面板顯 一 麦匕括·一利用一微影製程及第一盥第 二姓刻製程形成具有歷經一圓化製程之底部之第一渠溝之 第一渠溝形成步驟;一導體形成步驟’其係利用一微影製 程開啟具該等第-渠溝之中央部,接著將—傳導材料嵌入 開啟區中’藉以形成導體;一利用一微影製程與一介電膜 形成製程於一各該等導體之上部上形成一介電質之介電質 形成步驟;及一移除該犧牲基板之完結製程。 本發明之另一態樣提供一種製造一用以測試一平面板顯 不器之探針片之方法,包括步驟··於一犧牲基板上形成一 第一保護膜圖案,藉此界定形成複數個單元接觸組件之尖O: \ 89 \ 89662.DOC 1242647 piece forming step ’to fix the conductors in the trench. 'Another aspect of the first invention of the present invention is to provide a method of a probe of a display device, including: a: M test a flat plate |) lithography process and a conductive film " manufacturing-conductor formation The steps are to use the -1 seek V pancreatic formation process on the upper and lower planes of a substrate to form a single-sacrifice case to form a conductor; _dielectric ...: + surface The photoresist pattern is formed on the photo-cable, and the first and second benefits are equal to that of the guide. Zhao Zhi opens the central part to form = i on each side. An etching process of the lower plane of the body; a companion path leading to each temple, 9, the supporting components in the trenches and 幵 j into a supporting component of the supporting component y of the completion step. Into a step, and-removing the sacrificial substrate. Another aspect of the present invention provides a method for providing a probe for a display device, including testing a flat panel display, a microphone, a lithography process, and a first bath. The first surname engraving process forms a first ditch formation step having a first ditch that goes through the bottom of a rounding process; a conductor forming step 'which uses a lithographic process to open the central portion of the first -ditch, and then Embedding a conductive material in the opening region to form a conductor; a dielectric forming step of forming a dielectric on the upper portion of each of the conductors using a lithography process and a dielectric film forming process; and a shift In addition to the completion process of the sacrificial substrate, another aspect of the present invention provides a method for manufacturing a probe chip for testing a flat panel display, comprising the steps of: forming a first protective film pattern on a sacrificial substrate So as to define the tip forming a plurality of unit contact components

O:\89\89662.DOC -10- 1242647 端之區域’·利用該第一保護膜圖案為蝕刻罩,藉由施行一 蝕刻製程於該犧牲基板上形成渠溝;移除該第—保護=圖 案’·於移除該第一保護膜處之該犧牲基板上形成一第二保 護膜圖案,藉此界定形成複數個單元接觸組件之尖端之區 域;藉由在形成該第二保護膜圖案處之該犧牲基板上形成 々:金屬膜而形成該單元接觸組件之光束構件;藉由移除該 第二保護膜圖案而開啟該單元接觸組件之該等光束構件. 以一預定尺核開啟該單元接觸組件之料光束構件處之 該犧牲基板切π具—職尺寸之薄膜置於切方之犧 牲基板上’並附接與固定該單元接觸組件之該等光束構件 於該薄膜之該下部上;及藉由移除附接與固定該薄膜處之 該犧牲基板而開啟該單元接觸組件之該等尖端。 本务明之另—態樣提供—種製造—使用—單—犧牲基板 之探針之方法’包括:一利用-微影與-敍刻製程於該單 一犧牲基板之上與下平面上形成第一渠溝之第一渠溝形成 /驟其中3亥單-犧牲基板具-預定厚度;-藉由嵌入一 傳‘材料於忒等第一渠溝中而形成導體之導體形成步驟; 巧彳用一从〜與一蝕刻製程於該等導體之下部上形成第二 -第—木屢形成步·;一•由散入一·導材料於該等 u中而形成介電質之介電質形成步驟;一於形成該 电貝處之a犧牲基板之該等上與下平面之至少—平面上 ,成:支擇組件之支撐組件形成步驟;及一移除該犧牲基 板之完結步驟。 用一單一犧牲基板 本發明之另一能搂+日w 心樣棱供一種製造一使O: \ 89 \ 89662.DOC -10- 1242647 end area '· Using the first protective film pattern as an etching mask, a trench is formed on the sacrificial substrate by performing an etching process; removing the first—protection = Pattern ': A second protective film pattern is formed on the sacrificial substrate where the first protective film is removed, thereby defining an area where the tips of the plurality of cell contact components are formed; by forming the second protective film pattern A sacrificial substrate is formed on the sacrificial substrate: a metal film forms a beam member of the unit contact assembly; the beam member of the unit contact assembly is opened by removing the second protective film pattern. The unit is opened with a predetermined ruler The sacrificial substrate with the material beam member of the contact component is cut with a film of a size on the sacrificial substrate of the cut square 'and the beam members of the unit contact component are attached and fixed on the lower part of the film; And opening the tips of the unit contact assembly by removing the sacrificial substrate where the film is attached and fixed. What's more obvious—provide a variety of methods—manufacture—use—single-sacrificial substrate probe method 'includes: a first-use-lithography and-sculpting process to form a first on the single sacrificial substrate above and below the plane Formation of the first trench of the trenches / steps where the single-sacrifice substrate has a predetermined thickness;-a conductor forming step of forming a conductor by embedding a pass-through material in the first trench, etc .; A second-first-wood repeated formation step is formed from ~ and an etching process on the lower part of these conductors; a dielectric formation step of forming a dielectric by scattering a conductive material into the u ; On at least one of the upper and lower planes of the sacrificial substrate where the electric substrate is formed, forming: a supporting component forming step of a selective component; and a finishing step of removing the sacrificial substrate. Using a single sacrificial substrate

OA89\89662.DOC 1242647 之探針之方法,包括:一 保護膜之第一保護膜形成步:早::牲上形成-第-預定厚度,其中利用兮第 ’、5亥早—犧牲基板具- 導體形成步驟,·―㈣成,::取圖案中而形成上導體之上 —第1 V 體處之該犧牲基板上形成 護二—;:Γ第二保護膜形成步驟,其中利用該第二保 一=;ΓΓ支撐組件;—於該第二保護膜圖案中形成 料於該与^巨且、^上支撐形成步驟;一藉由嵌入一介電質材 寺木溝中而形成一介雷人年 移除該犧牲基板之步驟。、π $成步驟’及- =明之另一態樣提供一種製造一使用一單一犧牲基板 二:之方法,包括·· -於-該單-犧牲基板之預定部上 弟*溝之第一渠溝形成步驟,其中該單-犧牲基板 糸由一預定材料製A,並歷經一抛光製程以具一預定厚 度:其中利用該等渠溝形成一介電質;一藉由嵌入一介電 材料於,亥等第一渠溝中而形成該介電質之介電質形成步 驟 $體形成步驟’其係藉由在形成該介電處之該犧牲 基板之上與下平面上形成一保護膜圖案而形成導體,接著 甘欠入一傳導材料於該保護膜圖案;及一移除該犧牲基板之 完結步驟。 本發明之另一態樣提供一種製造一使用一單一犧牲基板 之探針之方法,包括:一於一單一犧牲基板之一上平面之 、Z上I成具預疋練度之渠、/冓之渠溝形成步驟;一於 心成尔溝處之该犧牲基板上形成一第一保護膜圖案之第一OA89 \ 89662.DOC 1242647 probe method, including: a protective film, the first protective film formation step: early :: formed on the animal-the first-a predetermined thickness, in which the first, 5th Hai-sacrificial substrate with -Conductor forming step, ...: forming a pattern: forming an upper conductor on a pattern—forming a protective layer on the sacrificial substrate at the first V body—; Γ a second protective film forming step, in which the first Two guarantees one; ΓΓ support component;-forming a step of supporting the upper and lower supports in the second protective film pattern; forming a dielectric thunder by embedding a dielectric material in the temple trench The step of removing the sacrificial substrate in human years. , Π $ 成 步骤 'and-= another aspect of the Ming provides a method of manufacturing a using a single sacrificial substrate II: a method, including-in-the first channel of the predetermined part of the single-sacrificial substrate * the first channel The trench formation step, wherein the single-sacrificial substrate 糸 is made of a predetermined material A, and undergoes a polishing process to have a predetermined thickness: wherein the trenches are used to form a dielectric; and a dielectric material is embedded in , The dielectric formation step of forming the dielectric in the first trench, etc. The body formation step is performed by forming a protective film pattern on the sacrificial substrate and the lower plane where the dielectric is formed. A conductor is formed, and then a conductive material is arbitrarily inserted into the protective film pattern; and a finishing step of removing the sacrificial substrate. Another aspect of the present invention provides a method for manufacturing a probe using a single sacrificial substrate, including: forming a channel on a plane of one of the single sacrificial substrates, forming a pre-trained channel on Z, / 冓A trench forming step; a first protective film pattern is formed on the sacrificial substrate at the Xinchenger trench;

O:\89\89662.DOC -12- l242647 保護膜形成步驟’藉此開啟該等渠溝 甘欠入一渠溝埋,、 材料於該第-保護膜圖案開啟之該等渠溝中之竿溝埋入步 驟,其中藉由-姓刻製程移除該等渠溝埋入材料;一利用 一被影製程於该犧牲基板之上鱼下承 只下千面上形成一第二保護 膜之弟一保遵膜圖案形成步驟,盆φ 士丨 ^ ^其中利用該第二保護膜圖 案形成導體;一於該第二保護滕安 示又肤圖案所界定之特定位置處 形成導體之導體形成步驟;一於, 於形成该寺導體處之該犧牲 基板之該等上與下平面上形成—箆一 4 取弟二保護膜圖案之第三保 護膜圖案形成步驟,其中利用哕筐一 J用11亥弟二保護膜圖案形成一支 撐組件;一於該第三保護膜圖 口木所界疋之特定位置處形成 -支擇組件之支樓組件形成步驟;及一移除部分為該渠溝 埋入材料分隔之犧牲基板並接著移除該渠溝埋入材料之完 結步驟。 【實施方式】 在本發明之說明書中,注意"探針,,在本發明中係指"探 針結構π。 首先,在詳述依本發明之用以測試平面板顯示器之探针 之具體實施㈣,先將描述探針之概念性構造。 如圖la至1C與圖仏至及中所示,類板狀介電質⑽由介 電材料如陶莞製成。介電質10厚240微米較佳。此外,介電 :1〇兩端具步階差外型或傾斜外型較佳。再者,由於介電 、、〃有、.#持&針外型與絕緣功能,故介電質係由硬質材 料製成較佳。 由鎳(Ni)或鎳合金製成之導體2如與2仙具桿狀外型,其兩O: \ 89 \ 89662.DOC -12-l242647 Protective film formation step 'This will open the trenches and bury them in a trench, and the material will be in the trenches where the -protective film pattern is opened. The trench embedding step, in which the trench embedding material is removed by a surname engraving process; a brother is formed on the sacrificial substrate by a shadow process to form a second protective film on the lower surface. One guarantees compliance with the film pattern forming step, where the conductor is formed using the second protective film pattern; one is a conductor forming step for forming a conductor at a specific position defined by the second protective Teng Anshi skin pattern; one is Forming on the upper and lower planes of the sacrificial substrate where the temple conductor is formed—the first and third protective film pattern forming steps of taking the second protective film pattern, in which the first and second protective film patterns are used. The protective film pattern forms a supporting component; a branch component forming step of forming-selecting a component at a specific position bounded by the third protective film figure; and a removed portion for the trench buried material separation Sacrificial substrate and then remove the trench and embed End knot material step. [Embodiment] In the description of the present invention, note that the "probe" refers to the "probe structure π" in the present invention. First, in detail the detailed implementation of the probe for testing a flat panel display according to the present invention, the conceptual structure of the probe will be described first. As shown in Figs. 1 to 1C and Figs. 1 to 1 and 1, plate-like dielectrics ⑽ are made of a dielectric material such as Tao Wan. Dielectric 10 is preferably 240 microns thick. In addition, the dielectric: 10 has a stepped or slanted shape at both ends. In addition, because of the dielectric, 〃 ,, ## & pin shape and insulation function, the dielectric is preferably made of a hard material. Conductors 2 made of nickel (Ni) or nickel alloys

O:\89\89662.DOC -13- 1242647 末端部具尖銳外型。 有不同的製造依本具體實施例之導體之方法。在第一具 體實施例中,導體插入處之渠溝係利用切方鑛齒製程开^ 成,具尖銳末端部之導體附接並固定於各渠溝中,藉以使 得導體位於介電質10上。 在第二具體實施例中,導體位置與大小係視微影製程而 定,並以預定間隔位於介電質之上下平面之至少一平面上。 導體20a與20b分別與介電質10之上下平面相接。雖缺兩 列導體係分別於介電質之上下平面上形成,但亦可使」列 導體位於介電質10内。 此外,在一列導體位於介電質内之情況下,形成單層探 針,示如圖2a至2c。 由於係自探針上部觀察探針,故置放導體2〇a與2〇b使得 在黾貝10之上平面上之導體2〇a位於介電質之下平面 之相鄰導體20b間。 此外,在介電質10之上平面上之各導體20a長度均與在介 電質10之下平面上之各導體2〇b相同,自介電質⑺向外突出 之導體20a與20b之左右突出部之長度均同。 如圖lc所示,在介電質1〇之上平面上之導體2〇a之末端部 較在介電質10之下平面上之導體2〇b之末端部突出。特別言 之,導體20a與20b之形成使得連結介電質1〇之上平面上之 導體20a之末端部與介電質1〇之下平面上之導體2仙之末端 部之線u相對於各導體表面具3〇。至6〇。夾角較佳。所採用之 導體20a與20b之製造厚度為6〇土5微米。O: \ 89 \ 89662.DOC -13- 1242647 The tip has a sharp shape. There are different methods of manufacturing a conductor according to this embodiment. In the first specific embodiment, the trenches at the conductor insertion points are formed using a tangent tine process. The conductors with sharp ends are attached and fixed in the trenches, so that the conductors are located on the dielectric 10 . In the second specific embodiment, the position and size of the conductor are determined according to the lithography process, and are located on at least one plane above and below the dielectric at predetermined intervals. The conductors 20a and 20b are in contact with the upper and lower planes of the dielectric 10, respectively. Although two rows of conducting systems are formed on the dielectric substrate above and below, respectively, it is also possible to arrange the conductors in the dielectric 10. In addition, a single-layer probe is formed when a row of conductors are located within the dielectric, as shown in Figures 2a to 2c. Since the probe is viewed from the top of the probe, the conductors 20a and 20b are placed so that the conductor 20a on the plane above the shell 10 is located between adjacent conductors 20b on the plane below the dielectric. In addition, the lengths of the conductors 20a on the plane above the dielectric 10 are the same as the lengths of the conductors 20b on the plane below the dielectric 10. The conductors 20a and 20b protrude outward from the dielectric ⑺. The protrusions have the same length. As shown in FIG. 1c, the end portion of the conductor 20a on the plane above the dielectric 10 is more prominent than the end portion of the conductor 20b on the plane below the dielectric 10. In particular, the conductors 20a and 20b are formed such that a line u connecting the end portion of the conductor 20a on the plane above the dielectric 10 and the end portion of the conductor 2 cents on the plane below the dielectric 10 is relative to each The conductor surface has 30. To 60. The included angle is better. The thickness of the conductors 20a and 20b used is 60 to 5 microns.

O:\89\89662.DOC -14- 1242647 如後述,在製造具有在介電fl〇上之導體加與鳥之用 以測财面板顯示器之探針之方法之主要具體實施例有 -。弟-具體實施例係利用切方鋸齒製程製造探針之方 法’第二具體實施利澤係利職刪製程製造探針之方法。 在採用_s製程之情況下,可於導體心舆鳥表面上形 成導電率較導體佳之薄導體材料術與杨。傳導材料係以 鑛金層形成較佳。形成傳導材料他與杨以改盖各導體之 傳導率。 口守版心 此外:並具有以環氧化物、陶瓷板’或環氧化物與陶瓷 成开7成之支撐組件3〇a與3〇b。支撐組件與導體⑽與 2〇b之上部相接,俾強化導體2〇a與20b支撐。 再者:本發明另揭示單層探針與雙層探針。如圖2^2c 所不’早層探針包括具預定尺寸之類板狀介電質8㈧以特 定間隔平行穿透介電質之複數個導體5〇;以及與介電質8〇 之上下平面之一相接之類板狀支撐組件6 〇。 結用MEMS製程之情況下,可於單層探針中之各導體 5〇之-平面上形成具優良導電率之傳導材料。該傳導材料 為金,藉以形成鍍金層7〇較佳。 單層探針與雙層探針之料㈣,且部件之功能相同。 因此,茲不贅述。 (第一具體實施例) 。依第:具體實施例,利用切方㈣製程在由硬質材料製 矩形強化板上形成渠溝(縫)並將導體插入與固定於該 等木溝中而製造用以測試平面板顯示器之探針,藉以使得O: \ 89 \ 89662.DOC -14-1242647 As will be described later, the main specific embodiment of the method for manufacturing a probe having a conductor on a dielectric fl0 and a bird for measuring a panel display is-. Brother-specific embodiment is a method for manufacturing a probe using a tangential sawtooth process. The second specific implementation is a method for manufacturing a probe using a profitable process. In the case of the _s process, a thin conductive material with better conductivity than the conductor can be formed on the surface of the conductor and the bird. The conductive material is preferably formed with a layer of mineral gold. Forming conductive materials, he and Yang changed the conductivity of each conductor. Mouth guard version In addition: It also has support components 30a and 30b that are 70% apart from epoxide, ceramic plate 'or epoxide and ceramic. The supporting component is connected to the upper part of the conductor ⑽ and 20b, and 俾 strengthens the support of the conductors 20a and 20b. Furthermore: The present invention also discloses single-layer probes and double-layer probes. As shown in Figure 2 ^ 2c, the early probe includes a plate-like dielectric 8 having a predetermined size, and a plurality of conductors 50 which penetrate the dielectric in parallel at a specific interval; and a plane above and below the dielectric 80. One of them is a plate-like supporting assembly 60. In the case of a MEMS process, a conductive material with excellent conductivity can be formed on the-plane of each conductor 50 in a single-layer probe. The conductive material is gold, so that the gold plating layer 70 is preferably formed. Single-layer probes and double-layer probes are the same, and the functions of the components are the same. Therefore, I will not repeat them here. (First specific embodiment). According to a specific embodiment, a trench is formed on a rectangular reinforced plate made of hard material by using a tangent square process, and a conductor is inserted and fixed in these wooden grooves to manufacture a probe for testing a flat panel display. So that

O:\89\89662.DOC -15- 1242647 導體充作用以測試平面板顯示器之針。 現將參閱圖3至5描述第—具體實施例。 圖3a至3e係闡釋依本 平面板顯示器之探針之^/具體只施例之用以測試 之方法之流程圖。4視圖’以及用以闡釋製造該探針 法中,2 3月ί用以測試平面板顯示器之探針及其製造方 撐板係二:所製傷之支撐板9〇為矩形板狀。該支 9牙〇之上、石貝材枓如陶究製成。由於中央槽93係在支樓板 川之上千面之一側至其相 以於支擇板9。之上平…成= 向方向中形成,因此得 第二突出區95。 屯成彼此相對之第一突出區91與 所=成之中央槽93可具切方鑛齒或類似形狀。 接著如圖3 b所示,利用切古施| 方鋸回氣程分別於支撐板90上 與95之上表面上形成複數個針狀渠 溝9l97b。該等複數個渠溝97a與97b均連結於中央㈣。 此外,分別於第一與第二突出區Mi%上二 娜均具相驟…車使彼此相對,如圖3c所二: :形成之渠溝可能係在第一突出區91上形成之渠溝⑽ 精細間隔,而在第二突出區95上形成之渠溝⑽則具粗操間 隔,或反之。 特別言之,就渠溝97a與97峰度而言,較佳係所形成之 渠溝舆中央槽93水平相同’或所形成之渠溝較中央槽93 深’俾得以視中央槽93之平坦度決定在渠溝%盥⑽中之 導體之平坦度。O: \ 89 \ 89662.DOC -15- 1242647 The conductor acts as a pin for testing flat panel displays. A first embodiment will now be described with reference to FIGS. 3 to 5. Figures 3a to 3e are flowcharts illustrating the method for testing the flat panel display probes. 4 views' and the method used to explain the method of manufacturing the probe, 2 March, the probe used to test the flat panel display and its manufacturing method. This branch is made of stone materials such as ceramics. Since the central groove 93 is located on one side of the thousands of planes above the branch floor slab to the side corresponding to the support slab 9. The upper flat surface is formed in the direction, so that the second protruding region 95 is obtained. The first protruding areas 91 and the central grooves 93 formed opposite each other may have tangent teeth or similar shapes. Next, as shown in Fig. 3b, a plurality of needle-shaped trenches 9l97b are formed on the support plate 90 and the upper surface of the support plate 95, respectively, by using the backing airflow of the clegusch | square saw. The plurality of trenches 97a and 97b are connected to the central ridge. In addition, on the first and second protruding areas Mi%, the second na has a phase difference ... the car is opposite to each other, as shown in Figure 3c. 2: The formed trench may be the trench formed on the first protruding area 91.间隔 Finely spaced, while the trenches formed on the second protruding area 95 are coarsely spaced, or vice versa. In particular, in terms of the trenches 97a and 97 kurtosis, it is preferred that the trenches formed are at the same level as the central trenches 93 or the trenches formed are deeper than the central trenches 93, so that the central trenches 93 are flat. The degree determines the flatness of the conductor in the channel.

O:\89\89662.DOC -16- 1242647 ,而後如圖3d所不,具預定長度與預定直徑之導體%均具 大銳狀末端部,並分別位於在支撐板9〇之第一突出區W 與第二突出區95上形成之渠溝97a與97b中。 省各導體98均具自支撐板90向外突出之預定長度,使得各 導體之一末端部可充作接觸組件,以直接與平面板顯示器 之測試處相接,另一末端部則可充作連結組件。導體%係 由鎢或鎢合金製成。 2圖36所示’於支撐板90上方用以插入針或導體(針)98 於弟—與第二突出區91與95上形成之渠溝97a與97b中處施 加黏㈣’接著施加黏著劑如環氧化物並固化以附接於支 揮板上之導體上,藉以製造探針。 現將參閱圖4舆5描述參閱圖3所述探針之製造方法之具 體貫施例。 圖4a與4b係闡釋依本發明之另一且, 、, w ~力具體貫施例之用以測智 平面板顯示器之探針及其製造方法之透視圖。 在依本發明之具體實施例之用以測試平面板顯示器之探 針及其製造方法中,如圖4a所示,上方形成次級探針之另 -支撐板到系在第一具體實施例中之支撐板9〇上方。此處 之支撐板100與支撐板90之製造方法相同。 位於上部處之探針稱之為上探 、 ^針其與弟一具體實施例 中稱之為下振針之探針製造方法 乃沄相冋。亦即在第一突出區 101上形成之渠溝107a連結於中 、 y夹槽103,且位於渠溝107a 中之導體1 〇 8係以黏著劑如環气 J衣虱化物1〇9附接與固定。此 外,另一渠溝係於第二突出區 上形成,但圖4a中並未顯O: \ 89 \ 89662.DOC -16-1242647, and then as shown in Figure 3d, the conductors with a predetermined length and a predetermined diameter have large sharp ends and are located in the first protruding areas of the support plate 90 respectively. W and trenches 97a and 97b formed in the second protruding region 95. Each of the conductors 98 has a predetermined length protruding outward from the support plate 90, so that one end of each conductor can be used as a contact component to directly connect to the test place of the flat panel display, and the other end can be used as Link components. The conductor% is made of tungsten or a tungsten alloy. 2 As shown in FIG. 36, 'A needle or a conductor (needle) 98 is inserted above the support plate 90. The adhesive is applied in the middle of the trenches 97a and 97b formed on the second protruding areas 91 and 95', and then an adhesive is applied. Such as epoxide and curing to attach to the conductor on the support board to make the probe. Specific embodiments of the method for manufacturing the probe described in FIG. 3 will now be described with reference to FIGS. 4a and 4b are perspective views illustrating a probe for measuring a smart flat panel display and a manufacturing method thereof according to another embodiment of the present invention. In a probe for testing a flat panel display and a method for manufacturing the same according to a specific embodiment of the present invention, as shown in FIG. 4a, another secondary support plate forming a secondary probe is attached to the first specific embodiment. Above the support plate 90. The manufacturing method of the support plate 100 and the support plate 90 here is the same. The probe located at the upper part is called the upper probe, and the manufacturing method of the probe which is called the lower vibrating needle in a specific embodiment is the same. That is, the trench 107a formed on the first protruding area 101 is connected to the middle and y clamp grooves 103, and the conductor 10a located in the trench 107a is attached with an adhesive such as an air-loop J lice compound 109. With fixed. In addition, another channel was formed on the second protruding area, but it is not shown in Figure 4a.

O:\89\89662.DOC -17- 1242647 不 ο 接著如圖4b所示,利用黏著劑如環氧化物(未圖示)附接上 下探針使之相互重疊。 ”所形成之上探針之導體i 〇 8 (而後有時稱之為上導體)舆下 板針之導體98(而後有時稱之為下導體戌替配置。各上探針 之導體U)8之-末端部較對應之各導體叩之末端部向外突 出較多。上下導體之向外突出部總長相同,使得上下導體 具相同物理條件。各導體⑽與98之—末端部係充作直接盘 平面板顯示器之測試處相接之接觸組件,另—末端部則充 作連結組件。 雖然在具體實施例中所述係雙層探針,應知可依製造商 意向製造三或更多層探針。 此外,亦可依製造商意向選擇決定上下探針之附接處。 口此可直接附接與固定上探針之支樓板1〇〇於下探針之支 撐板90上。 圖5 a係闡釋依本發明之另 板顯示器之探針及其製造方 剖面圖。 一具體實施例之用以測試平面 法之透視圖;圖5b則係圖5a之 具體實施例之用以測試平面板顯示器 中,如圖5a與5b所示,於支樓板9〇之 在依本發明之另一 之探針及其製造方法 下平面上施行下列製成。亦即與第一具體實施例類似,形 成中央槽112、第-突出區11〇與第二突出區之製程;形 成第-渠溝116a與第二渠溝(未示於圖叫之製程;以及形成 穿透第-渠溝ma、第二渠溝(未圖示)與中央槽112之下導O: \ 89 \ 89662.DOC -17- 1242647 No ο Then, as shown in Figure 4b, the upper and lower probes are attached to each other with an adhesive such as an epoxide (not shown). The conductor i 〇8 of the upper probe (hereinafter sometimes referred to as the upper conductor) and the conductor 98 of the lower board pin (later sometimes referred to as the lower conductor are alternately arranged. The conductor U of each upper probe) The 8-ends protrude outwards more than the corresponding end of each conductor 总. The total length of the outward protrusions of the upper and lower conductors is the same, so that the upper and lower conductors have the same physical conditions. Each of the conductors 之 and 98-the end is sufficient The direct contact flat panel display is connected to the contact assembly at the test point, and the other end is used as the connection assembly. Although the double-layer probe is described in the specific embodiment, it should be understood that three or more can be manufactured according to the manufacturer's intention. Layer probe. In addition, you can also choose the attachment point of the upper and lower probes according to the manufacturer's intention. You can directly attach and fix the upper floor 100 of the upper probe on the support plate 90 of the lower probe. 5 a is a cross-sectional view illustrating a probe of another display according to the present invention and a manufacturing method thereof. A perspective view of a specific embodiment for testing a plane method; FIG. 5 b is a specific embodiment of FIG. 5 a for testing a flat panel. Panel display, as shown in Figures 5a and 5b, in the branch building 90 ° performs the following fabrication on the lower plane of another probe and its manufacturing method according to the present invention. That is, similar to the first embodiment, a central groove 112, a first protruding region 11 and a second projection are formed. Process of the area; formation of the first canal 116a and the second canal (not shown in the drawing; and formation of a guide through the first canal ma, the second canal (not shown) and the central groove 112

O:\89\89662.DOC -18 - 1242647 體118(具預定長度)之製程,藉以使得兩末端部向外突出, 二、 乂於支撐板之下平面上施行利用黏著劑如環氧化物 而為之附接與固定下導體118於支撐板90之下平面之製程。 所形成之在支撐板90之上平面上之導體98與在支撐板90 、下平面上之導體118呈鉛直交替。在支撐板之上平面上之 導體98之一末端部較在支撐板之下平面上之各導體118之 對應末鳊部更為向外突出。上導體⑽與下導體US之向外突 出部總長相同。 (第二具體實施例) 弟二具體實施例係利用MEMS製程製造探針之方法。在 七田述製以木針方法之特殊範例前,將先描述製造探針方法 中之共通步驟。 在犧牲基板製備步驟中,所製備之犧牲基板具有矽(si) 晶圓或由_料製成之基板。概言之,犧牲基板較佳厚 度為400至5〇〇微米。 接著在;丨包貝形成步驟中,利用蝕刻製程於犧牲基板之 ^下平面之敎區上形成渠溝。並接著將介電質插入或禱 模於渠溝中’藉以於犧牲基板上形成介電質。介電質包含 陶瓷、環氧化物等。換言之’於渠溝中施加環氧化物,並 在環氧化物固化前,將與各渠溝大小相同之預製陶£板插 入與附接於渠溝中,藉以形成介電質。或者,可將與各渠 溝大小相同之預製m插人,接著施加環氧化物於渠溝 與陶兗板之間隙中,因而附接渠溝與陶究板,#以形成介 電質。O: \ 89 \ 89662.DOC -18-1242647 The process of body 118 (with a predetermined length), so that the two ends protrude outward. Second, carry out the use of an adhesive such as epoxide on the plane below the support plate. A process for attaching and fixing the lower conductor 118 below the support plate 90. The conductors 98 formed on the plane above the support plate 90 and the conductors 118 on the support plate 90 and the lower plane are vertically alternated. One end portion of the conductor 98 on the plane above the support plate protrudes more outwardly than the corresponding end portion of each conductor 118 on the plane below the support plate. The total length of the upper protrusion of the upper conductor ⑽ and the lower conductor US is the same. (Second Specific Embodiment) The second specific embodiment is a method for manufacturing a probe using a MEMS process. Before describing a special example of the wooden needle method made by Nanada, common steps in the method of manufacturing a probe will be described. In the sacrificial substrate preparation step, the prepared sacrificial substrate has a silicon (Si) wafer or a substrate made of silicon. In summary, the preferred thickness of the sacrificial substrate is 400 to 500 microns. Then, in the step of forming a shell, a trench is formed on a region of the lower plane of the sacrificial substrate by an etching process. And then insert or pray the dielectric into the trench 'to form the dielectric on the sacrificial substrate. Dielectrics include ceramics, epoxides, and so on. In other words, an epoxide is applied to the trench, and a prefabricated ceramic plate of the same size as each trench is inserted and attached to the trench before the epoxy is cured, thereby forming a dielectric. Alternatively, a prefabricated m of the same size as each trench can be inserted, and then an epoxide is applied in the gap between the trench and the pottery board, so the trench and the pottery board are attached to form a dielectric.

O:\S9\89662.DOC -19- 1242647 、雖然陶瓷板為矩形平行六面體,但其亦可為平行四邊形 或步階形,如圖21a與21b所示。 / 韻刻犧牲基板之上τ平面之預定部之製程包含切方製程 -乾飿刻製程’其中㈣光阻形成之保護膜圖案韻刻犧牲 基板。 此處在以㈣作為犧牲基板之情況τ,由於犧牲基板本 即係介電質’故於犧牲基板之上部上形成介電質之製 可略之。 接著在導體形成步驟中,於犧牲基板之上下平面上形成 與導體外型相同之圖案,接著精確利用這些圖案於各處形 成導體。導體係由鎳(Ni)或鎳合金製成較佳。 首先,利用光阻於犧牲基板上之精確位置處(形成導體處) ==導體形狀相同之圖案。接著利用這些圖案,以電解 貝讀法形成導體。結果使得依本發明之探針在介電質之 亡下平面上之上下導體之配置間隔、位置與間距上具有優 !精確性與再造性,故與人卫施行接合製程之情況相較, 仔以降低產生故障率。 由於導體係以電鑛製程形成,故在電鑛製程前,需於犧 牲基板表面形成種層’以利施行電鑛製程。此處之種声可 ^用減鑛法形成。此外,種層係以欽㈤與銅(Cu)製成較 :。欽層具!提昇犧牲基板與銅層間黏著性之功能,銅層 、J可充作後績電鍍製程中之電鍍種層用。 曰 此外,體係由鎳(Ni)或鎳合金製成。 在支撐組件形成步驟中,將支撐組件附接與鑄模於犧牲O: \ S9 \ 89662.DOC -19- 1242647. Although the ceramic plate is a rectangular parallelepiped, it can also be a parallelogram or step shape, as shown in Figures 21a and 21b. / The manufacturing process of the predetermined portion of the τ plane on the sacrificial substrate includes a tangent process-a dry-etching process, wherein the protective film pattern formed by the photoresist is formed on the sacrificial substrate. Here, in the case where ㈣ is used as the sacrificial substrate τ, since the sacrificial substrate is a dielectric material ', a system for forming a dielectric on the upper portion of the sacrificial substrate can be omitted. Next, in the conductor forming step, the same pattern as the shape of the conductor is formed on the upper and lower planes of the sacrificial substrate, and then these patterns are accurately used to form the conductor everywhere. The guide system is preferably made of nickel (Ni) or a nickel alloy. First, use a photoresist at a precise position on the sacrificial substrate (where the conductor is formed) == a pattern with the same conductor shape. These patterns are then used to form conductors by electrolytic reading. As a result, the probe according to the present invention is superior in the arrangement interval, position, and spacing of the upper and lower conductors on the lower plane of the dielectric material! Accuracy and reproducibility, so it is compared with the case where the joint process is performed by human health. To reduce the failure rate. Since the guide system is formed by an electric mining process, a seed layer is required to be formed on the surface of the sacrificial substrate before the electric mining process to facilitate the electric mining process. The kind of sound here can be formed by ore reduction. In addition, the seed layer is made of Chin-Yin and copper (Cu). Qin layer has the function of improving the adhesion between the sacrificial substrate and the copper layer. The copper layer and J can be used as the plating seed layer in the post-plating process. In addition, the system is made of nickel (Ni) or a nickel alloy. At the support assembly forming step, attach and mold the support assembly to the sacrifice

O:\89\89662.DOC -20. 1242647 基板上欲形成導體處。 成。特別言之,…由…物或陶莞製 於並μ 在衣乳物固化前,預先施加環氧化物並 於,、上附接陶变板即可獲得較佳支樓組件。 " 換言之’利用光㈣成支撐組件圖案 件圖案中施加支擇材料,藉以形成支撐㈣。妾者於支撐組 完結步驟中,利製程移除犧牲基板之 夕欠餘邛,稭以得出探針。 之二二方:而言’在利用硬質材料如陶瓷作為犧牲基板 ^ 製造探針之方法包括槽形成㈣,其係於介電 質材料製之單-犧牲基板之上下平面之預定部且= :度之槽,所形成之預定厚度係利用抱光製程為 貝形成補充工具形成步驟,其 ,„ „ ^ ,、係猎由形成用以於犧牲基板 ^開啟才曰之保護膜圖案並將金屬材料嵌入槽中而形成介電 貝形成補充工具’其中金屬材料係可利用濕银刻製程選擇 性移除之材料;導體形成步驟,其係於犧牲基板上形成盘 導體外型相同之保護膜圖案並接著利用這些圖案於精心立 置處形成導體而為之;支撐組件形成步驟’其係於犧牲基 板之上下平面上欲形成導體處形成支撐組件;以及將介電 質形成補充工具自犧牲基板移出之步驟。 此處之硬質材料包含陶瓷、破璃等。 現將參閱隨附圖式描述用以測試平面板顯示器之探針構 造及其製造方法。 (具體實施例2 -1) 圖6a至6Ρ係闡釋依另一具體實施例製造用以測試平面板 O:\89\89662.DOC -21 - 1242647 顯示器之探針之方法之剖面圖。 在依茶閱圖6a至6p所述之具體實施例中之製造探針之方 法中,導體及對齊鍵係位於犧牲基板之上平面上,以利於 利用對齊鍵在其下平面上施行製程。如圖6a所示,在利用 沉積製程如濺鍍製程於矽等材料製之犧牲基板12〇上形成 之種層126具預定厚度,接著於種層126上塗佈充作保護膜 之具預定厚度之第一光阻128。 所建構之種層126具有厚500埃之鈦層122與厚5,〇〇〇埃之 銅層124。銅層124實質上係充作後續電鍍製程中之種層 126。鈦層122則係用以改善犧牲基板12〇與銅層124之黏著 性。 接著如圖6b所示,形成第一光阻圖案129以界定用以形成 導體之預定區,以及在後續製程中之對齊鍵。各導體均係 與所測試之平面板顯示器直接相接之接觸組件。 可利用其上設計有預定電路圖案之罩,藉由在犧牲基板 0上开^成之第一光阻128之曝光形成第一光阻圖案Μ),俾 形成導體舆對齊鍵,接著顯影之。 而後如圖&所示,利用電鑛製程沉積傳導材料如鎖(Ni 或録合金(Ni-Co、Nl_w_c。)於犧牲基板12吐有第一光阻圖 案129形成處而形成僂導膜〗μ 风得V膜13 1。接者利用平坦化製程使犧 牲基板120之上平面平坦化。 利用化學機械抱光(CMP)法及研磨法等施行平坦化製 之電_程期間,在種層126中之銅 層124係充作電鍍材料之來源。O: \ 89 \ 89662.DOC -20. 1242647 Where a conductor is to be formed on the substrate. to make. In particular,… made by… or Tao Wan before the milk solidified, pre-apply epoxide and then attach the ceramic transformer board to obtain better branch components. " In other words, 'the support pattern is formed by using light to form a support pattern. In the end of the support group, the operator removes the surplus of the sacrificial substrate in the manufacturing process to obtain the probe. The second and second party: In terms of 'using a hard material such as ceramic as a sacrificial substrate ^ The method of manufacturing a probe includes a groove formation ㈣, which is a predetermined portion of the upper and lower planes of a single-sacrificial substrate made of a dielectric material and =: Degree groove, the predetermined thickness formed is a step of forming a supplementary tool for the shell using a light-holding process, which is formed by forming a protective film pattern for opening the sacrificial substrate and opening the metal material. Embedded in the trench to form a dielectric shell forming supplementary tool 'where the metal material is a material that can be selectively removed using a wet silver engraving process; the conductor forming step is to form a protective film pattern with the same shape as the disk conductor on a sacrificial substrate and These patterns are then used to form conductors at carefully erected places; the supporting component forming step is to form supporting components at the conductors to be formed on the upper and lower planes of the sacrificial substrate; and remove the dielectric formation supplementary tool from the sacrificial substrate. step. The hard materials here include ceramics, broken glass, and the like. The structure of a probe for testing a flat panel display and a method of manufacturing the same will now be described with reference to the accompanying drawings. (Specific Example 2 -1) Figures 6a to 6P are cross-sectional views illustrating a method of manufacturing a probe for testing a flat panel O: \ 89 \ 89662.DOC -21-1242647 display according to another embodiment. In the method for manufacturing a probe according to the specific embodiment described in Figs. 6a to 6p, the conductor and the alignment key are located on the plane above the sacrificial substrate, so as to facilitate the use of the alignment key to perform the process on its lower plane. As shown in FIG. 6a, a seed layer 126 formed on a sacrificial substrate 12 made of silicon and other materials by a deposition process such as a sputtering process is formed with a predetermined thickness, and then the seed layer 126 is coated with a predetermined thickness as a protective film. The first photoresist 128. The seed layer 126 is constructed to have a titanium layer 122 having a thickness of 500 angstroms and a copper layer 124 having a thickness of 5,000 angstroms. The copper layer 124 is substantially used as a seed layer 126 in a subsequent electroplating process. The titanium layer 122 is used to improve the adhesion between the sacrificial substrate 120 and the copper layer 124. Next, as shown in FIG. 6b, a first photoresist pattern 129 is formed to define a predetermined area for forming a conductor, and an alignment key in a subsequent process. Each conductor is a contact component that is in direct contact with the flat panel display being tested. The first photoresist pattern (M) can be formed by exposing a first photoresist 128 formed on the sacrificial substrate 0 by using a cover having a predetermined circuit pattern thereon, and then forming a conductor alignment key, and then developing it. Then, as shown in FIG. &Amp;, a conductive material such as a lock (Ni or alloy (Ni-Co, Nl_w_c.)) Is deposited using a power mining process on the sacrificial substrate 12 where the first photoresist pattern 129 is formed to form a hafnium conductive film. μ Wind obtains the V film 13 1. Then, the planarization process is used to planarize the plane above the sacrificial substrate 120. During the electrical process of performing the planarization process using the chemical mechanical polishing (CMP) method and the polishing method, the seed layer is used. The copper layer 124 in 126 serves as a source of the electroplating material.

O:\89\89662.DOC -22- 1242647 特另丨"之’在用以形成傳導膜13 1之理想電鍍製程之進程 中’僅於第一光阻圖案129之開啟部内形成傳導膜131之情 況下,平坦化製程可略之。 此外,在利用除電鍍製程外之方法如物理汽相沉積(PVD) 與化學汽相沉積(CVD)形成傳導膜131之情況下,先前形成 種層126之製程可略之。 接著如圖6d所不,藉由移除第一光阻圖案129使得部分銅 層124曝光,藉以形成導體及對齊鍵132a與132b。可以方法 如使用化學物之濕蝕刻製程或乾蝕刻製程移除第一光阻圖 案 129。 接著如圖6e所示,在使用化學物之濕蝕刻製程中,利用 導體13G及對齊鍵132a#132b為罩,藉由移除第—光阻圖案 129使得由鈦層122與銅層124構成之種層126曝光而移除 之,藉以使得導體!30及對齊鍵132&與13几完全暴露在外。 接著如圖6f所示’塗佈一定數量之第二光阻134於犧牲基 板120上導體130及對齊鍵1323與1321)完全暴露在外處。 雖然在此係塗佈固接於旋轉吸盤上之犧牲基板12〇,但第 二光阻U4係經一噴嘴喷灑於犧牲基板12〇上,故得以塗佈 一定數量之第二光阻134。 接著如圖6g所示,將具有預定電路圖案之罩置於犧牲基 板⑽上塗佈第二光阻134處,接著將之曝光與顯影,藉二 形成完全開啟之導體130之中央部與對齊鍵132&與13几之 第二光阻圖案136。 接著如圖6h所示,以介電材料如環氧化物封閉導體13〇 O:\89\89662.DOC -23- 1242647 之中央^ (隨第二光阻圖案136而完全開啟)而形成支撐板 138 〇 在此可利用印刷法等形成充作支撐板138之環氧化物。 接著如圖61所示,以研磨製程將犧牲基板之上平面中完 王為’丨私負材料如環氧化物製之支撐板138封閉之導體之 中央部平坦化。 在此施行研磨製程以利後續在犧牲基板120背平面上施 行之研磨製程。 接著如圖6j所不,犧牲基板12〇面朝下,並研磨犧牲基板 120之背平面至預定厚度,藉以調整在後續渠溝形成製程 中,犧牲基板12〇之蝕刻深度於低高度。 接著如圖6k所示,塗佈預定厚度之第三光阻140於被研磨 至預定厚度之犧牲基板12〇之背平面上。 此處之第三光阻14〇塗佈法與第一及第二光阻128及134 相同。 接著如圖61所示,以上具特定電路圖案之罩將第三光阻 140曝光並接著顯影,藉此形成用以開啟犧牲基板丨2〇之背 平面之中央部之第三光阻圖案142。 接著如圖6m所示,利用第三光阻圖案142為罩,施行蝕刻 製耘,俾完全蝕刻種層126,藉以形成用以開啟犧牲基板12〇 之渠溝144。 此處之蝕刻製程係使用具特定比例之讣6、(^匕與匕之混 合氣體之乾蝕刻製程。 更特別言之,係利用所謂的波許⑺仍…製程施行蝕刻製O: \ 89 \ 89662.DOC -22- 1242647 In particular, "in the course of an ideal plating process for forming the conductive film 13 1", the conductive film 131 is formed only in the opening portion of the first photoresist pattern 129 In this case, the planarization process can be omitted. In addition, in the case where the conductive film 131 is formed using a method other than the plating process such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), the previous process of forming the seed layer 126 can be omitted. Next, as shown in FIG. 6d, a portion of the copper layer 124 is exposed by removing the first photoresist pattern 129, thereby forming conductors and alignment keys 132a and 132b. The first photoresist pattern 129 may be removed by a method such as a wet etching process using a chemical or a dry etching process. Next, as shown in FIG. 6e, in the wet etching process using chemicals, the conductor 13G and the alignment keys 132a # 132b are used as a cover, and the first photoresist pattern 129 is removed so that the titanium layer 122 and the copper layer 124 are formed. The seed layer 126 is exposed and removed to make the conductor! 30 and alignment keys 132 & 13 are completely exposed. Next, as shown in FIG. 6f, a certain amount of the second photoresist 134 is coated on the conductor 130 and the alignment keys 1323 and 1321 on the sacrificial substrate 120) to be completely exposed. Although the sacrificial substrate 12o fixed on the rotary chuck is coated here, the second photoresist U4 is sprayed on the sacrificial substrate 120 through a nozzle, so a certain number of second photoresists 134 can be coated. Next, as shown in FIG. 6g, a cover having a predetermined circuit pattern is placed on a sacrificial substrate 涂布 and coated with a second photoresist 134, and then exposed and developed to form a fully opened central portion of the conductor 130 and an alignment key. 132 & and the second photoresist pattern 136. Next, as shown in FIG. 6h, a support plate is formed with a dielectric material such as an epoxide closed conductor 1300: \ 89 \ 89662.DOC -23-1242647 ^ (fully opened with the second photoresist pattern 136) to form a support plate 138 〇 Here, an epoxide used as a support plate 138 can be formed by a printing method or the like. Then, as shown in FIG. 61, the central portion of the conductor enclosed by the private material such as the support plate 138 made of an epoxy material is flattened in the plane above the sacrificial substrate by a grinding process. A polishing process is performed here to facilitate subsequent polishing processes performed on the back plane of the sacrificial substrate 120. Next, as shown in FIG. 6j, the sacrificial substrate 12 is face down, and the back plane of the sacrificial substrate 120 is polished to a predetermined thickness, so as to adjust the etching depth of the sacrificial substrate 12 to a low height in the subsequent trench formation process. Next, as shown in FIG. 6k, a third photoresist 140 with a predetermined thickness is coated on the back plane of the sacrificial substrate 12 which has been ground to a predetermined thickness. The third photoresist 14 coating method is the same as the first and second photoresist 128 and 134. Then, as shown in FIG. 61, the third photoresist 140 is exposed by the mask with a specific circuit pattern and then developed, thereby forming a third photoresist pattern 142 for opening the central portion of the back plane of the sacrificial substrate 20. Next, as shown in FIG. 6m, the third photoresist pattern 142 is used as a cover to perform an etching process, and the seed layer 126 is completely etched to form a trench 144 for opening the sacrificial substrate 120. Here, the etching process is a dry etching process using a specific ratio of 讣 6, (^ 与 and 匕 mixed gas. More specifically, the so-called Bosch ⑺ is still used ...

O:\89\89662.DOC -24- 1242647 耘其係一源自深渠溝蝕刻法之反應離子蝕刻(RIE)。 接著如圖6n所示,在犧牲基板12〇之背平面上形成之渠溝 144中轭加一定數量之環氧化物黏著劑146,接著對以預定 尺寸之陶瓷板製成之支撐板丨48加壓並將之插入渠溝1 A# 中,藉以將支撐板148嵌入並附接於渠溝144中。 接著如圖6〇所示,藉由移除圖6n之第二光阻圖案136與第 一光阻圖案142使得支撐板148、介電質板13〇與導體138暴 露在外。 & 此處之第二光阻圖案136與第三光阻圖案142之移除,係 以使用化學物之乾蝕刻製程或濕蝕刻製程為之。 最終如圖6p所示,藉由在犧牲基板12〇上施行使用化學物 之濕蝕刻製程,使得各導體138之末端部暴露在外。各導體 138之下平面之中央部與介電質板13()絕緣,且各導體138之 上平面之中央部為支撐板148所支撐,藉以得出探針。 在此移除圖6〇中所示對齊鍵132&與1321)及殘餘種層126。 (具體實施例2-2) 圖7a至7ι係闡釋依另一具體實施例製造用以測試平面板 顯示為之板針之方法之剖面圖。 在依本具體實施例之探針製造方法中,如圖7a所示,利 用沉積製程如濺鍍製程,於矽等材料製之犧牲基板2〇〇上形 成具預定厚度之種層206,接著於種層上塗佈具預定厚度之 充作保護膜之第一光阻2〇8。 種層206係由鈦層202與銅層2〇4構成。銅層2〇4實質充作 後續電鍍製程中之來源。所具鈦層2〇2係用以改善犧牲基板O: \ 89 \ 89662.DOC -24-1242647 It is a reactive ion etching (RIE) derived from the deep trench etching method. Next, as shown in FIG. 6n, a certain amount of epoxide adhesive 146 is added to the trench 144 formed on the back plane of the sacrificial substrate 120, and then a support plate made of a ceramic plate of a predetermined size is added. Press and insert it into the trench 1 A #, thereby embedding and attaching the support plate 148 in the trench 144. Then, as shown in FIG. 60, the support plate 148, the dielectric plate 13 and the conductor 138 are exposed by removing the second photoresist pattern 136 and the first photoresist pattern 142 of FIG. 6n. & The second photoresist pattern 136 and the third photoresist pattern 142 are removed here by a dry etching process or a wet etching process using a chemical. Finally, as shown in FIG. 6P, a wet etching process using a chemical is performed on the sacrificial substrate 120, so that the end portion of each conductor 138 is exposed. The central portion of the lower plane of each conductor 138 is insulated from the dielectric plate 13 (), and the central portion of the upper plane of each conductor 138 is supported by the support plate 148, thereby obtaining a probe. The alignment keys 132 & 1321) and the residual seed layer 126 shown in FIG. 60 are removed here. (Embodiment 2-2) Figs. 7a to 7m are cross-sectional views illustrating a method of manufacturing a plate pin shown as a plate pin according to another embodiment. In the probe manufacturing method according to this embodiment, as shown in FIG. 7a, a seed layer 206 having a predetermined thickness is formed on a sacrificial substrate 200 made of silicon or the like by a deposition process such as a sputtering process, and then on The seed layer is coated with a first photoresist 208 having a predetermined thickness as a protective film. The seed layer 206 is composed of a titanium layer 202 and a copper layer 204. The copper layer 204 is substantially used as a source in the subsequent electroplating process. The titanium layer 20 is used to improve the sacrificial substrate

O:\89\89662.DOC -25- 1242647 200與銅層204之黏著性。 光阻圖案21 〇以界定用以於後 接著如圖7b所示,形成第一 續製程中形成導體之預定區。 可將,又相形成導體之預定電路圖案之罩置於圖之犧 牲基板上形成之第—光阻則上,並接著將其曝光與顯 影,藉以形成第一光阻圖案2 1 〇。 而後如圖九所不,利用電鍍製程沉積傳導材料如鎳(Ni) 或鎳合金於犧牲基板上㈣—光阻圖 木2 10形成處而形成充作接觸組件用之傳導膜2 12。接著利 用平坦化製程使犧牲基板2〇〇之上平面平坦化。 利用化學機械拋光(CMP)法及研磨法等施行平坦化製 紅在形成傳導膜212之電鍍製程期間,銅層2〇4係充作電 鍍材料之來源。特別言之,在用以形成傳導膜212之理想電 鍍製釭之進耘中,僅於第一光阻圖案2丨〇之開啟部内形成傳 導膜212之情況下,平坦化製程可略之。此外,在利用除電 鍍製程外之方法如物理汽相沉積(pVD)與化學汽相沉積 (CVD)形成傳導膜212之情況下,先前形成種層2〇6之製程可 略之。 接著如圖7d所示,在移除第二光阻圖案21〇後,利用在圖 7c之第二光阻圖案21〇之開啟部中形成之傳導膜212作為自 行對背罩而施行蝕刻製程,移除殘餘在圖7c之第二光阻圖 案210之下部上之由鈦層2〇2與銅層2〇4構成之種層2〇6。 此處係利用濕蝕刻或乾蝕刻移除第二光阻圖案2丨〇,亦可 利用濕蝕刻或乾蝕刻移除種層2〇6。 O:\89\89662.DOC -26- 1242647 而後如圖7e所示 板200上之圖7C之第 塗佈一疋數ϊ之第三光阻214於犧牲基 二光阻圖案被移除處。 二J用 4的光阻旋轉塗佈法等塗佈第三光阻214。 接著如圖7f所7^,置放上具特定電路圖案之罩於犧牲基 ⑽0上塗佈有第三光阻214處,並接著將其曝光與顯影, 猎以形成用以開啟充作接觸組件之傳導膜212之中央部之 光阻圖案222。 而後如圖7g所示,施加一定數量之黏著劑216如環氧化物 於利用第三光阻圖案222開啟之開啟部中,接著將具預定尺 寸之介電質材料如陶瓷製之支撐板218插入與附接於 光阻圖案222之開啟部中。 ' — 接著如圖7h所示’藉由移除圖%之第三光阻圖案222使得 由支撐板218與傳導膜212構成之導體暴露在外。 最終如圖7i所示’利用難刻製程等移除圖几之犧牲基 板200中之支撐板218與傳導膜212暴露在外處,以及在傳導 膜2 12之下部上之種層206,藉以完成具傳導膜之探針。 在此以一系列使用不同化學物之濕蝕刻製程依序移除犧 牲基板200以及由銅層202與鈦層204構成之種層2〇6較佳。 此外,並額外施行附接介電質材料如環氧化物於完成之 探針之傳導膜212之背平面上之製程。 (具體實施例2-3) 圖8a至8t係闡釋依另一具體實施例製造用以測試平面板 顯示器之探針之方法之剖面圖。 在依所述具體實施例之探針製造方法中,如圖8a所示, O:\89\89662.DOC -27- 1242647 塗佈第一光阻252於矽等材料製之犧牲基板252上。 此處係利用熟知之光阻旋轉塗佈法等塗佈第一光阻252。 接著如圖8b所示,於犧牲基板25〇施行後續製程,藉此形 成第一光阻圖案254以界定對齊鍵與塑造接觸組件。 在此藉由對齊一預定罩而於犧牲基板25〇上形成第一光 阻圖案254,接著將其曝光與顯影。 而後如圖8c所示’以犧牲基板250上之第一光阻圖案254 為罩,施行蝕刻製程,藉以形成第一渠溝25以與25讣及第 一渠溝258 ’俾用以形成犧牲基板25〇中之對齊鍵與接觸組 件。 在此係以使用反應性氣體之乾蝕刻製程施行形成第一渠 溝256a與256b及第二渠溝258之製程。 接著在移除在犧牲基板25〇上形成第一渠溝25以與25讣 及第二渠溝258處之第一光阻圖案254後,利用製程如濺鍍 製程形成具預定厚度之種層26〇。 種層260係由厚500埃之鈦層261與厚5,〇〇〇埃之銅層262 構成。銅層262實質上係充作後續電鍍製程中之種層26〇。 鈦層261則係用以改善犧牲基板25〇與銅層262之黏著性。 接著如圖心所示,塗佈一定數量之第二光阻264於犧牲基 板250上形成種層260處。 在此可利用熟知之光阻旋轉塗佈法等塗佈第二光阻⑽。 而後如圖輯示,將形成犧牲基板250處之第二光阻⑽ 曝光與顯影,藉以形成第二光阻圖案265,俾界定形成第一 渠溝256a與256b及第二渠溝258之區域。O: \ 89 \ 89662.DOC -25- 1242647 200 Adhesion to copper layer 204. The photoresist pattern 21 is used to define a predetermined area for forming a conductor in the first subsequent process as shown in FIG. 7b. The first photoresist pattern 2 1 can be formed by placing a cover of a predetermined circuit pattern that forms a conductor on the first photoresist formed on the sacrificial substrate of the figure, and then exposing and developing it. Then, as shown in FIG. 9, a conductive material such as nickel (Ni) or a nickel alloy is deposited on the sacrificial substrate by an electroplating process. A photoresist pattern 2 10 is formed to form a conductive film 2 12 for contact components. Then, a planarization process is used to planarize the plane above the sacrificial substrate 2000. The chemical mechanical polishing (CMP) method and the polishing method are used for planarization. During the electroplating process for forming the conductive film 212, the copper layer 204 is used as a source of electroplating materials. In particular, in the progress of the ideal electroplating process for forming the conductive film 212, only in the case where the conductive film 212 is formed in the opening portion of the first photoresist pattern 20, the planarization process can be omitted. In addition, in the case where the conductive film 212 is formed by a method other than the electroplating process, such as physical vapor deposition (pVD) and chemical vapor deposition (CVD), the previous process of forming the seed layer 206 can be omitted. Next, as shown in FIG. 7d, after removing the second photoresist pattern 21o, an etching process is performed by using the conductive film 212 formed in the opening portion of the second photoresist pattern 210 of FIG. 7c as a self-backing mask. A seed layer 206 composed of a titanium layer 202 and a copper layer 204 that is left on the lower portion of the second photoresist pattern 210 in FIG. 7C is removed. Here, the second photoresist pattern 2 is removed by wet etching or dry etching, and the seed layer 206 may also be removed by wet etching or dry etching. O: \ 89 \ 89662.DOC -26- 1242647, and then as shown in FIG. 7e, the third photoresist 214 coated with a plurality of layers of the first photoresist 214 in FIG. The second photoresist 214 is coated with a photoresist spin coating method of 4 or the like. Next, as shown in FIG. 7f, a mask with a specific circuit pattern is placed on the sacrificial substrate, and a third photoresist 214 is coated. Then, it is exposed and developed, and hunted to form a contact component for opening. A photoresist pattern 222 at a central portion of the conductive film 212. Then, as shown in FIG. 7g, a certain amount of an adhesive 216 such as an epoxide is applied to the opening portion opened with the third photoresist pattern 222, and then a dielectric material having a predetermined size such as a support plate 218 made of ceramic is inserted And attached to the opening of the photoresist pattern 222. '— Next, as shown in FIG. 7h', by removing the third photoresist pattern 222 of FIG.%, The conductor composed of the support plate 218 and the conductive film 212 is exposed. Finally, as shown in FIG. 7i, the support plate 218 and the conductive film 212 in the sacrificial substrate 200 of FIG. 2 are removed by using a difficult-to-etch process, etc., and the seed layer 206 on the lower part of the conductive film 21 is completed to complete the tooling. Probe for conductive film. It is preferable to sequentially remove the sacrificial substrate 200 and the seed layer 206 composed of the copper layer 202 and the titanium layer 204 in a series of wet etching processes using different chemicals. In addition, a process of attaching a dielectric material such as an epoxy on the back plane of the conductive film 212 of the completed probe is additionally performed. (Embodiment 2-3) FIGS. 8a to 8t are cross-sectional views illustrating a method of manufacturing a probe for testing a flat panel display according to another embodiment. In the probe manufacturing method according to the specific embodiment, as shown in FIG. 8a, O: \ 89 \ 89662.DOC -27-1242647 coats the first photoresist 252 on a sacrificial substrate 252 made of silicon and other materials. Here, the first photoresist 252 is coated by a well-known photoresist spin coating method or the like. Then, as shown in FIG. 8b, a subsequent process is performed on the sacrificial substrate 25, thereby forming a first photoresist pattern 254 to define the alignment key and the shape of the contact component. Here, a first photoresist pattern 254 is formed on the sacrificial substrate 25 by aligning a predetermined mask, and then it is exposed and developed. Then, as shown in FIG. 8c, the first photoresist pattern 254 on the sacrificial substrate 250 is used as a cover, and an etching process is performed to form the first trench 25 and 25 讣 and the first trench 258 'to form a sacrificial substrate. Align the keys in 25 ° with the contact assembly. This is a process of forming the first trenches 256a and 256b and the second trench 258 by a dry etching process using a reactive gas. After removing the first trench 25 formed on the sacrificial substrate 25 to form the first photoresist pattern 254 at 25 处 and the second trench 258, a seed layer 26 having a predetermined thickness is formed using a process such as a sputtering process. 〇. The seed layer 260 is composed of a titanium layer 261 with a thickness of 500 angstroms and a copper layer 262 with a thickness of 5,000 angstroms. The copper layer 262 is substantially used as a seed layer 26 in the subsequent electroplating process. The titanium layer 261 is used to improve the adhesion between the sacrificial substrate 25 and the copper layer 262. Then, as shown in the figure, a certain amount of second photoresist 264 is applied on the sacrificial substrate 250 to form a seed layer 260. Here, a second photoresist can be applied by a well-known photoresist spin coating method or the like. Then, as shown in the photo, a second photoresist at the sacrificial substrate 250 is exposed and developed to form a second photoresist pattern 265, and the areas where the first trenches 256a and 256b and the second trench 258 are formed are defined.

O:\89\89662.DOC -28- 1242647 而後如圖8g所示,利用電鍍製程沉積傳導材料如鎳 或鎳合金(Ni-Co、Ni-W-Co)於犧牲基板250上有第二光阻圖 案265形成處而形成傳導膜266。 此處在用以形成傳導膜266之電鍍製程期間,在種層26〇 中之銅層262係充作電鍍材料之來源。 接著如圖8h所示,將犧牲基板250之上平面上形成傳導膜 266處平坦化。犧牲基板250之上平面之平坦化製程係利用 化學機械拋光(CMP)法及研磨法等為之。 此外,在用以形成傳導膜266之理想電鍍製程之進程中, 僅於第二光阻圖案265之開啟部内形成傳導膜266之情況 下,平坦化製程可略之。 接著如圖8i所示,塗佈一定數量之第三光阻268於犧牲基 板250上完成平坦化製程處。 在此可利用熟知之光阻旋轉塗佈法等塗佈第三光阻268。 接著如圖8j所示,形成用以開啟在犧牲基板25〇上形成之 傳導膜266之中央部之第三光阻圖案270。 此處可藉由採用一罩之曝光製程與顯影製程形成第三光 阻圖案270。 接著如圖8k所示,藉由嵌入介電質材料如環氧化物於第 三光阻圖案270所開啟之開啟部中而形成介電質板272。 而後如圖81所示,將犧牲基板250之上平面上形成介電質 板272處平坦化。該平坦化係利用化學機械拋光(CMp)法及 研磨法等為之。 接著如圖8m所示,犧牲基板250面朝下,並研磨犧牲基板 O:\89\89662.DOC -29- 1242647 250之背平面至狀厚度’施行該研磨製程,以調整在後續 渠溝:成製程中’犧牲基板25()之#刻深度於低高度。 接著如圖8η所示,塗佈預定厚度之第四光阻274於被施行 研磨衣耘之犧牲基板25〇之背平面上。可利用熟知之光阻塗 佈法形成第四光阻274。 接者如圖8〇所示,將在犧牲基板25〇上形成之第四光阻 274曝光並接著顯影,藉此形成用以開啟犧牲基板Μ。之背 平面之中央邛(犧牲基板25〇之中央部)之第四光阻圖案276。 而後如圖8ρ所示,以第四光阻圖案276為罩施行蝕刻製 程。藉此於犧牲基板250之背平面上形成用以開啟傳導膜 266之第三渠溝278。此處之蝕刻製程係使用具特定比例之 SF0、(:4匕與〇2之混合氣體之乾蝕刻製程。 更特別言之,係利用所謂的波許製程施行蝕刻製程,其 係一源自深渠溝餘刻法之反應離子钱刻(RIE)。 接著如圖8q所示,在犧牲基板25〇之背平面上形成之第三 渠溝278中施加一定數量之環氧化物黏著劑28〇,接著對以 預定尺寸之陶瓷板製成之支撐板282加壓並將之插入渠溝 278中’藉以將支撐板282埋入並附接於第三渠溝278中。 接著如圖8r所示,以平坦化製程將犧牲基板25〇之背平面 上支撐板282埋入第三渠溝278處平坦化。 利用化學機械拋光(CMP)法或研磨法施行平坦化製程。 而後如圖8s所示,移除第三光阻圖案270、第四光阻圖案 276舆種層260。 最終如圖8t所示,利用蝕刻製程移除犧牲基板250,藉此 O:\89\89662.DOC -30- 1242647 完成之探針具有附接於具黏著劑280之導體284之上部上之 支撐組件282以及位於導體284之下部上之介電質板π〕。 圖9係闡釋依另一具體實施例製造用以測試 器之探針之方法之透視圖。 板不 在依本具體實施例之探針製造方法中,製備圖6〇之導體 130完全暴露在外之第一犧牲基板28〇與第二犧牲基板 282,或是製備圖8t之導體284完全暴露在外之第一犧牲基 板280與第二犧牲基板282。 此處之對齊鍵288、介電質板284及導體286向外暴露於第 一犧牲基板280與第二犧牲基板282上。 接著藉由相對於對齊鍵288或操作者眼睛之第一犧牲基 板280之導體284與第二犧牲基板282之導體284之匹配,將 第一犧牲基板280與第二犧牲基板282附接在一起,並接著 以黏著劑使之相互附接。 在第二犧牲基板282上形成之複數個導體286垂直配置於 在第一犧牲基板280上形成之複數個相鄰導體286間之間隙 空間中,藉以使得第二犧牲基板282之各導體286垂直配置 於第一犧牲基板280之相鄰導體286間,並 加之各導體施之末端部較第—犧牲基板之 之末端部水平突出為多(其中導體為多層結構)。 而後,以與丽揭具體實施例相同之濕蝕刻製程移除第一 與第二犧牲基板280與282,藉以製造堆疊探針處之多層探 針。 雖然在本具體實施例中所述係雙層探針,應知可依製造 O:\89\89662.DOC -31 - 1242647 者意向製造三或多層探針。 圖1 〇a係闡釋依另一具體實施例之探針之透視圖;圖⑽ 係其剖面圖。 如圖H)a與10b所示,依本發明之具體實施例之探針係由 雙層結構構成,其中利用黏著工具如黏著劑將在第一探針 3〇〇與第二探針310上形成之介電質板3〇6與316附接在一 起,藉此堆疊第一探針300與第二探針31q。 在第一採針300與第二探針3 1〇中,在陶瓷等製之支撐板 308與318之下部上以預定間隔分別附接複數個導體3〇2與 312,亚將介電質材料如環氧化物3〇4與3 μ製之介電質板 306與316分別附接於導體3〇2與312之下中央部上。 更特別言之,第二探針31〇之各導體垂直配置於第一探針 300之相鄰導體302間之間隙空間中,藉此得以將多層探針 之導體302與導體312之間隔調整至極短。 在該堆疊結構中,第二探針31〇之各導體312較第一探針 300之各導體3〇2之末端部在水平方向突出。 此外,在另一具體實施例中,分別在第一探針3〇〇與第二 探針310上形成之支撐板3〇8與3 18為黏著工具如黏著劑附 接在一起,藉此得以製出堆疊有第一探針300與第二探針 310之雙層結構。 再者,在又一具體實施例中,第一探針3〇〇或第二探針 之’丨私貝板306與3 16和第一探針3〇〇或第二探針31〇之支撐 板3 08與〇 1 8間為黏著工具如黏著劑附接在一起,藉此得以 製出堆疊有第一探針300與第二探針3 10之雙層結構。O: \ 89 \ 89662.DOC -28- 1242647 Then as shown in FIG. 8g, a conductive material such as nickel or a nickel alloy (Ni-Co, Ni-W-Co) is deposited on the sacrificial substrate 250 by a plating process, and there is a second light Where the resist pattern 265 is formed, a conductive film 266 is formed. Here, during the electroplating process used to form the conductive film 266, the copper layer 262 in the seed layer 26 is used as a source of electroplating material. Next, as shown in FIG. 8h, the conductive film 266 is formed on a plane above the sacrificial substrate 250 to be planarized. The planarization process of the plane above the sacrificial substrate 250 is performed by a chemical mechanical polishing (CMP) method, a polishing method, or the like. In addition, in the course of an ideal plating process for forming the conductive film 266, only when the conductive film 266 is formed in the opening portion of the second photoresist pattern 265, the planarization process can be omitted. Next, as shown in FIG. 8i, a certain number of third photoresists 268 are coated on the sacrificial substrate 250 to complete the planarization process. Here, the third photoresist 268 can be coated by a well-known photoresist spin coating method or the like. Next, as shown in FIG. 8j, a third photoresist pattern 270 is formed to turn on the central portion of the conductive film 266 formed on the sacrificial substrate 25o. Here, the third photoresist pattern 270 can be formed by using a mask exposure process and a development process. Next, as shown in FIG. 8k, a dielectric plate 272 is formed by embedding a dielectric material such as an epoxide in the opening portion opened by the third photoresist pattern 270. Then, as shown in FIG. 81, a dielectric plate 272 is planarized on a plane above the sacrificial substrate 250. This planarization is performed by a chemical mechanical polishing (CMp) method, a polishing method, or the like. Next, as shown in FIG. 8m, the sacrificial substrate 250 faces downward, and the back surface of the sacrificial substrate O: \ 89 \ 89662.DOC -29- 1242647 250 is polished to a thickness of '100, and the polishing process is performed to adjust the subsequent trenches: In the manufacturing process, the #etching depth of the sacrificial substrate 25 () is deeper than the low height. Next, as shown in FIG. 8n, a fourth photoresist 274 with a predetermined thickness is applied on the back plane of the sacrificial substrate 25 which has been subjected to a polishing coat. The fourth photoresist 274 can be formed by a well-known photoresist coating method. As shown in FIG. 80, the fourth photoresist 274 formed on the sacrificial substrate 25 is exposed and then developed, thereby forming a sacrificial substrate M for opening. A fourth photoresist pattern 276 in the center of the back plane (the center of the sacrificial substrate 25). Then, as shown in FIG. 8ρ, an etching process is performed using the fourth photoresist pattern 276 as a mask. Thereby, a third trench 278 for opening the conductive film 266 is formed on the back plane of the sacrificial substrate 250. Here, the etching process is a dry etching process using a mixture of SF0, (: 4k and 02) with a specific ratio. More specifically, the so-called Bosch process is used to perform the etching process. Reactive ion money engraving (RIE) of the trench trench method. Next, as shown in FIG. 8q, a certain amount of epoxy adhesive 28 is applied to the third trench 278 formed on the back plane of the sacrificial substrate 25. Then, the support plate 282 made of a ceramic plate of a predetermined size is pressurized and inserted into the trench 278 ', thereby burying and attaching the support plate 282 in the third trench 278. Then, as shown in FIG. 8r, The planarization process is used to planarize the support plate 282 on the back plane of the sacrificial substrate 25 to the third trench 278. The planarization process is performed by a chemical mechanical polishing (CMP) method or a polishing method. Then, as shown in FIG. 8s, The third photoresist pattern 270 and the fourth photoresist pattern 276 are removed from the seed layer 260. Finally, as shown in FIG. 8t, the sacrificial substrate 250 is removed by an etching process, thereby O: \ 89 \ 89662.DOC -30-1242647 The completed probe has an attachment on top of a conductor 284 with an adhesive 280 The supporting member 282 and the dielectric plate π on the lower part of the conductor 284]. FIG. 9 is a perspective view illustrating a method of manufacturing a probe for a tester according to another embodiment. The board is not in accordance with this embodiment. In the probe manufacturing method, the first sacrificial substrate 28 and the second sacrificial substrate 280 where the conductor 130 of FIG. 60 is completely exposed, or the first sacrificial substrate 280 and the second sacrificial substrate 280 where the conductor 284 of FIG. 8t is completely exposed are prepared. The sacrificial substrate 282. Here, the alignment key 288, the dielectric plate 284, and the conductor 286 are exposed to the first sacrificial substrate 280 and the second sacrificial substrate 282. Then, the alignment key 288 or the first Matching the conductor 284 of a sacrificial substrate 280 with the conductor 284 of the second sacrificial substrate 282 attaches the first sacrificial substrate 280 and the second sacrificial substrate 282 together, and then attaches them to each other with an adhesive. The plurality of conductors 286 formed on the sacrificial substrate 282 are vertically disposed in a gap space between a plurality of adjacent conductors 286 formed on the first sacrificial substrate 280, so that the conductors 286 of the second sacrificial substrate 282 are vertically disposed. Between adjacent conductors 286 of the first sacrificial substrate 280, and the ends of each conductor are more horizontally protruded than the ends of the first-sacrificial substrate (where the conductor is a multilayer structure). The same wet etching process removes the first and second sacrificial substrates 280 and 282 to manufacture a multilayer probe at the stacked probe. Although the double-layer probe is described in this embodiment, it should be understood that : \ 89 \ 89662.DOC -31-1242647 The intention is to make three or more layers of probes. Figure 10a is a perspective view illustrating a probe according to another embodiment; Figure ⑽ is a sectional view thereof. As shown in FIGS. H) a and 10b, the probe according to a specific embodiment of the present invention is composed of a double-layer structure, wherein an adhesive tool such as an adhesive will be used on the first probe 300 and the second probe 310. The formed dielectric plates 306 and 316 are attached together, thereby stacking the first probe 300 and the second probe 31q. In the first needle 300 and the second probe 3 10, a plurality of conductors 302 and 312 are attached to the lower portions of the support plates 308 and 318 made of ceramics or the like at predetermined intervals, respectively. For example, dielectric plates 306 and 316 made of epoxides 304 and 3 μ are attached to the central portions below the conductors 302 and 312, respectively. More specifically, each conductor of the second probe 31 is vertically disposed in a gap space between adjacent conductors 302 of the first probe 300, so that the distance between the conductors 302 and 312 of the multilayer probe can be adjusted to the extreme. short. In this stacked structure, each of the conductors 312 of the second probe 31 and the tip of each of the conductors 302 of the first probe 300 protrude in a horizontal direction. In addition, in another specific embodiment, the supporting plates 308 and 318 formed on the first probe 300 and the second probe 310, respectively, are attached together by an adhesive tool such as an adhesive, thereby obtaining A double-layered structure is formed in which the first probe 300 and the second probe 310 are stacked. Furthermore, in another specific embodiment, the first probe 300 or the second probe is supported by the private boards 306 and 316 and the first probe 300 or the second probe 31 The plates 3 08 and 08 are attached together by an adhesive tool such as an adhesive, so as to obtain a double-layer structure in which the first probe 300 and the second probe 3 10 are stacked.

O:\89\89662.DOC -32- 1242647 因此,第一探針300與第二探針3 1〇係位於堆疊結構中之 雙層探針併入探針組(未圖示)中,以確認經由一系列生產制 程所得之平面板顯示裝置之正常性。 衣 探針之各導體302與312之一末端部與平面板顯示器之一 測試處相#,亦即與墊電極相接,其另一末端部則連結至 與驅動晶片相連之捲帶式封裝(TCP),藉此確認平面板顯八 器之正常性。 纟、、、不 (具體實施例2-4) 圖11係闡釋依另體實施例之心測試平面板顯示器 之探針之透視圖。如圖U所示,探針具有各具桿狀光束^ 件322之複數個單元導體32〇,而光束構件322之一端具有與 之整合之檢測尖端324a,光束構件322之另一端則具^與^ 整合之檢測尖端324b。複數個單元導體32〇均以預定間隔配 置。 网一 此處之光束構件322及尖端3243與324b係由具優良傳導 率及延展性之金屬材料如(Ni)或鎳合金(Ni_c〇、 製成,各尖端324a與324b之末端部歷經圓化(r〇unding)製 程,以抑制微粒之產生。 此外’利用加壓製程與加熱製程將具預定大小並由可透 光材料如環氧化物或聚對二甲笨萝 〜卜4 T枣表成之可透光薄膜342附 接於複數個單元導體320上。 因此,將複數個單元導體 併入探針組中,以確認經由 顯示器之正常性。 320與薄膜342附接處之探針片 一系列生產製成所得之平面板O: \ 89 \ 89662.DOC -32- 1242647 Therefore, the first probe 300 and the second probe 3 10 are double-layer probes located in a stacked structure and merged into a probe set (not shown) to Confirm the normality of the flat panel display device obtained through a series of production processes. One end of each of the conductors 302 and 312 of the clothing probe is connected to one of the test positions of the flat panel display, that is, connected to the pad electrode, and the other end is connected to a tape and reel package connected to the driving chip ( TCP) to confirm the normality of the flat panel display.纟 ,,, and No (Embodiment 2-4) Fig. 11 is a perspective view illustrating a probe for testing a flat-panel display according to the heart of another embodiment. As shown in FIG. U, the probe has a plurality of unit conductors 32 each having a rod-shaped beam member 322, and one end of the beam member 322 has a detection tip 324a integrated therewith, and the other end of the beam member 322 has ^ and ^ Integrated detection tip 324b. The plurality of unit conductors 32 are arranged at predetermined intervals. The beam member 322 and the tips 3243 and 324b here are made of a metal material with excellent conductivity and ductility such as (Ni) or nickel alloy (Ni_co), and the ends of the tips 324a and 324b are rounded. (R〇unding) process to suppress the generation of particles. In addition, 'pressurization process and heating process will be a predetermined size and made of light-transmissive materials such as epoxide or poly-para-dimethy tallow ~ 4 T date The light-transmissive film 342 is attached to the plurality of unit conductors 320. Therefore, the plurality of unit conductors are incorporated into the probe set to confirm the normality of the display via the probe. Serial production of flat plates

O:\89\89662.DOC -33- 1242647 楝針片之連結尖端32仆連結至與驅動晶片相連之捲帶 封裝(TCP)’探針片之檢測尖端324a重複與平面板顯示= 測試處接觸’亦即與塾電極接觸,藉此確認平面板顯:器 此外,在另-具體實施例中,可不具各單元接觸組件之 光束構件322之連結尖端324b。不具連結尖端324b之各單元 導體320可經由非等向性傳導膜(ACF)連結至捲帶 (TCP) 〇 衣 圖12a至12i係、闡釋圖u所示之用以測試平面板顯示器之 探針之製造方法之剖面圖。 現爹閱圖12描述依本發明之用以測試平面板顯示器之势 造方法。首先’於具特定方向性如(1,〇,〇)之矽製之:牲: 板330上,形成在後續製程中用以形成第一渠溝33鈍與第2 渠溝334b之光阻圖案332。 、— 第-光阻圖案332係由具高感光性之光阻構成。第一光阻 圖案332之形成,係利用旋轉塗佈厚約2微米之光阻於基板 330之前平面上之旋轉塗佈製程,接著施行以製程與= 接著如圖12b所示,利用在犧牲基板33〇上形成之第—光 阻圖案332為㈣罩,施行第一㈣製程,藉此分別形成第 一朱溝334a與第二渠溝334b(檢測尖端32牦與連結尖产 324b係於其中形成)。 大而 形成渠溝334a與334b之第一蝕刻製程可為採用以預定比 例混合之氫氧化鉀(K0H)與去離子水之化學物之濕蝕刻製O: \ 89 \ 89662.DOC -33- 1242647 连结 The connection tip 32 of the needle piece is connected to the tape package (TCP) 'probe chip connected to the driver chip. The detection tip 324a of the probe piece is repeatedly in contact with the flat panel display = test place That is, contact with the rhenium electrode, thereby confirming the flat panel display: In addition, in another embodiment, the connection tip 324b of the beam member 322 of each unit contacting component may not be provided. Each unit conductor 320 without the connection tip 324b can be connected to the tape (TCP) via an anisotropic conductive film (ACF). Figure 12a to 12i are diagrams illustrating probes for testing flat panel displays shown in Figure u. Sectional view of the manufacturing method. Referring now to Fig. 12, a method for testing a flat panel display according to the present invention will be described. First, a photoresist pattern made of silicon with a specific directivity such as (1, 0, 0): a plate: 330 is formed in a subsequent process to form a first trench 33 and a second trench 334b. 332. -The first photoresist pattern 332 is composed of a photoresist with high sensitivity. The formation of the first photoresist pattern 332 is a spin coating process that spin-coats a photoresist with a thickness of about 2 micrometers on the plane before the substrate 330, and then performs the process and = then, as shown in FIG. 12b, using the sacrificial substrate The first photoresist pattern 332 formed on 33 ° is a mask, and the first process is performed to form the first Zhugou 334a and the second canal 334b (the detection tip 32 牦 and the connection tip 324b are formed therein). ). The first etching process for forming the trenches 334a and 334b may be a wet etching process using a chemical compound of potassium hydroxide (K0H) and deionized water mixed at a predetermined ratio.

O:\89\89662.DOC -34- 1242647 耘以使用化學物之濕蚀刻製程非等向蚀刻具特定方向性 之犧牲基板,藉此形成截面角錐狀或截面圓錐狀之第一渠 溝334a與第二渠溝334b。 /後如圖12e所示’以第-光阻圖案332為㈣罩,施行 第-姓刻製私,藉此形成之截面角錐狀或截面圓錐狀之第 一渠溝加與第:渠溝334喊度深,並使渠溝加與渠溝 3 3 4b歷經圓化製程。 此處之_製程係使用具特定比例之阳、C4m 〇2之混 合氣體之乾蝕刻製程。 更特別a之’係利用所謂的波許製程施行第二钱刻製 私其係源、自沐渠溝钱刻法之反應離子钱刻⑻幻。 接著先使截面角錐狀或截面圓錐狀之第一渠溝334&與第 、,木溝334bH帛名虫刻製程,使其深度為%微#至綱微 米,並使渠溝334a與334b底部歷經圓化製程。 而後如圖12d所示,在利用濕蝕刻製程移除圖丨之第一 光阻圖案332後,於前已歷經第二㈣製程之犧牲基板33〇 上形成在後績製程中充作種層336用之厚2,⑻〇埃至3,⑼〇埃 之銅層。 此處可利用物理沉積法如濺鍍製程形成銅層。 接著如圖12e所示,形成第二光阻圖案338,俾開啟在後 續製程中欲形成光束構件332之區域。 利用旋轉塗布製程、曝光製程及顯影製程,形成具有與 第光阻圖案332類似之高感光性之光阻所構成之第二光 阻圖案338。O: \ 89 \ 89662.DOC -34- 1242647 Using a chemical wet etching process to anisotropically etch a sacrificial substrate with a specific direction, thereby forming the first channel trench 334a and the cone-shaped first trench 334a and第二 沟沟 334b. / Later, as shown in FIG. 12e, with the first photoresist pattern 332 as a mask, the first-name engraving is performed to form a first channel trench with a cross-sectional pyramidal shape or a cross-sectional cone shape. Shout deep, and make the trenches and trenches 3 3 4b go through the rounding process. Here, the _ process is a dry etching process using a specific ratio of yang and C4m 0 2 mixed gas. The more special a ’is the use of the so-called Bosch process to carry out the second money engraving. The private ion source, the self-reaction ion money engraving method, is used to engraving magic. Next, the first trench 334 & and the first and second cone trenches with a cross-sectional pyramidal shape and the first and second trenches are engraved by the ditch 334b. Rounding process. Then, as shown in FIG. 12D, after the first photoresist pattern 332 in the figure is removed by a wet etching process, a seed layer 336 is formed on the sacrificial substrate 33 which has previously undergone the second process, and is used as a seed layer 336 in the subsequent process. Use a copper layer with a thickness of 2, Angstroms to 3, Angstroms. Here, a copper layer can be formed by a physical deposition method such as a sputtering process. Next, as shown in FIG. 12e, a second photoresist pattern 338 is formed, and the region where the beam member 332 is to be formed in a subsequent process is opened. A second photoresist pattern 338 composed of a photoresist having a high photosensitivity similar to the first photoresist pattern 332 is formed by a spin coating process, an exposure process, and a development process.

O:\89\89662.DOC -35- 1242647 而後如圖12f所示,利用電鏡製程形成由具有優良傳導率 與延展性之金屬材料如鎳(Ni)或鎳合金(Ni_c〇、Ni_w_c〇) 之具預定厚度之金屬膜,接著藉由化學機械拋光(CMp)法、 回蝕(etchback)法、研磨法等將犧牲基板33〇之上平面平坦 化而形成光束構件340。 但在先前施行製程中之電鍍製程中使用之種層336之形 成製程可略之,利用化學汽相沉積(CVD)法、物理汽相沉積 (PVD)法等形成由Ni、Ni_c〇、Ni_W-C〇等製之具預定厚度 之金屬膜’藉以形成光束構件34〇。 此外,在%行平坦化製程後,施行附加清洗製程以移除 犧牲基板330上之有機材料與微粒較佳。 接著如圖12g所示,在以濕蝕刻製程移除圖12f之第二光 阻圖案338後,將犧牲基板330上移除第二光阻圖案338處切 方。 而後如圖12h所示,將由可透光材料如環氧化物或聚對二 甲苯製之薄膜342至於切方之犧牲基板33〇上,接著利用加 壓製程與加熱製程,將薄膜342附接於在犧牲基板33〇上形 成之光束構件340之上平面上。 在此將藉由對薄膜342之加壓與加熱,在犧牲基板33〇上 形成由金屬膜構成之光束構件34〇之上部插入並附接於薄 膜342中。 最終如圖121所示,以使用化學物之濕蝕刻製程移除犧牲 基板330,藉此完成具類桿狀光束構件34〇之探針片,而光 束構件340之兩端分具接處尖端324a與連結尖端324b。 O:\89\89662.DOC -36- 1242647 (具體實施例2 - 5 ) 在依本么月之用以測试平面板顯示器之探針製造方法之 第-具體實施例中,如圖13a所示,以兩面均經拋光之具預 疋厚度之邦υ作為犧牲基板_。研磨製程或拋光製程後 之犧牲基板400厚約4〇〇至5〇〇微米。 接著如圖13a(b)所示,利用微影製程在犧牲基板4〇〇之兩 平面上形成與探針外型對應之第一光阻圖案她與侧。 在此由於係利用微影製程形成圖案4〇2&與4〇几,故可於所 要4置精確幵/成之。因此,與人工操作相較,得以進一步 改善錯誤。亦即’可以相同間隔於犧牲基板傷上形成相同 大J之複數個導體,特別言之,可於精確位置處交替形成 犧牲基板400之上平面八上之導體仙及犧牲基板楊之下 平面B上之導體412b。 因此,如圖13a(b)所示,在犧牲基板4〇〇之上下平面入與8 上形成之第一光阻圖案4〇2&與4〇2b係於稍後呈交替形式之 探針形成處之非對稱結構中形成。 而後如圖13a(c)所示,犧牲基板4〇〇之上平面a上之區域 係利用第一光阻圖案402a開啟,並利用非等向性乾蝕刻製 私蝕刻之,藉以於犧牲基板4〇〇之上平面A上形成具探針外 型之槽404。 接著如圖13a(d)所示,亦利用與上平面相同之製程蝕刻犧 牲基板400之下平面B,藉以形成具探針外型之槽4〇6。此處 在犧牲基板400之上下平面人舆]3上形成之槽4〇4與4〇6,具 有槽404與406相互交替之非對稱結構。O: \ 89 \ 89662.DOC -35- 1242647 and then as shown in Figure 12f, the electron microscopy process is used to form a metal material with excellent conductivity and ductility such as nickel (Ni) or nickel alloy (Ni_c0, Ni_w_c〇). A metal film having a predetermined thickness is then planarized on a plane above the sacrificial substrate 33 by a chemical mechanical polishing (CMp) method, an etchback method, a polishing method, or the like to form a beam member 340. However, the formation process of the seed layer 336 used in the electroplating process in the previous implementation process can be omitted. The chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method, etc. are used to form Ni, Ni_co, Ni_W- A metal film with a predetermined thickness, such as C0, is used to form the beam member 34o. In addition, after the% flattening process, an additional cleaning process is performed to remove organic materials and particles on the sacrificial substrate 330. Next, as shown in FIG. 12g, after the second photoresist pattern 338 of FIG. 12f is removed by a wet etching process, the second photoresist pattern 338 is removed from the sacrificial substrate 330 and cut in a square. Then, as shown in FIG. 12h, a thin film 342 made of a light-transmitting material such as an epoxide or parylene is placed on the sacrificial sacrificial substrate 33. Then, the thin film 342 is attached to the sacrificial substrate 33 using a pressure process and a heating process. The light beam member 340 formed on the sacrificial substrate 33 is on a plane. Here, the upper portion of the beam member 34o formed of a metal film on the sacrificial substrate 33o is inserted and attached to the thin film 342 by pressing and heating the thin film 342. Finally, as shown in FIG. 121, the sacrificial substrate 330 is removed by a wet etching process using a chemical, thereby completing a probe sheet having a rod-like beam member 340, and two ends of the beam member 340 are divided at the junction tips 324a. With link tip 324b. O: \ 89 \ 89662.DOC -36- 1242647 (specific embodiments 2-5) In the first-specific embodiment of the method for manufacturing a probe for testing a flat panel display according to this month, as shown in Figure 13a It is shown that a state with a pre-thickness thickness polished on both sides is used as the sacrificial substrate. The sacrificial substrate 400 after the grinding process or the polishing process has a thickness of about 400 to 5000 microns. Next, as shown in FIG. 13a (b), a lithography process is used to form a first photoresist pattern corresponding to the shape of the probe on both planes of the sacrificial substrate 400 and the side. Here, the patterns 40 and 40 are formed by the lithography process, so that they can be accurately set at a desired level. Therefore, compared with manual operation, the error can be further improved. That is, 'a plurality of conductors of the same size J can be formed on the sacrificial substrate wound at the same interval. In particular, the conductor fairy on the plane eight above the sacrificial substrate 400 and the plane B below the sacrificial substrate Yang can be alternately formed at precise positions. On the conductor 412b. Therefore, as shown in FIG. 13a (b), the first photoresist patterns 4002 & and 4202 formed on the sacrificial substrate 400 above and below the surface are formed by alternating probes formed later. Formed in an asymmetric structure. Then, as shown in FIG. 13a (c), the area on the plane a above the sacrifice substrate 400 is opened by the first photoresist pattern 402a, and is etched by anisotropic dry etching to sacrifice the substrate 4 A groove 404 having a probe shape is formed on the plane A above. Next, as shown in FIG. 13a (d), the lower plane B of the sacrificial substrate 400 is also etched by the same process as the upper plane, so as to form a groove 406 with a probe shape. Here, the grooves 404 and 406 formed on the sacrificial substrate 400 above and below the substrate 3 have an asymmetric structure in which the grooves 404 and 406 alternate with each other.

O:\89\89662.DOC -37- 1242647 此外’分別於犧牲基板4〇〇之上下平面A與B上形成之槽 404與406之蝕刻深度範圍在70至100微米,此係針對後續平 坦化製程之移除深度所作考量,因此蝕刻深度相對較所得 導體深度(亦即60微米)深。 而後如圖13a(e)所示,以使用化學物溶劑之濕蝕刻製程將 殘留在犧牲基板4〇〇之上下平面八與]3上之第一光阻圖案 402a與402b移除。 接著如圖13a(f)所示,形成種層408a與408b,俾施行用以 形成犧牲基板400之兩平面上之導體之電鍍製程。此處之種 層係由厚500埃之鈦層及厚5,〇〇〇埃之銅層構成。銅層係充 作後續電鍍製程中電鍍之種層用,鈦層則係用以提升犧牲 基板400與銅層間之黏著性。 而後如圖13a(g)所示,利用微影製程形成第二光阻圖案 a” 41〇b,以開啟犧牲基板4⑽之兩平面a與b上之預定 部。 、 接者如目13b(h)所示,利用電解f電㈣程於犧牲基板 〇〇之兩平面A與B上形成利用第二光阻圖案41〇績41扑開 啟之導體412a與412b。亦即以第二光阻圖案41()績41 〇b為 杈以电解貝電鍍法沉積傳導材料如鎳(Ni)或鎳合金 (Co Nl-W_co)而在犧牲基板4〇〇上形成導體412a鱼 412b。 ’、 圖13b⑴至⑻闡釋縱向圖與橫向圖,料楚解釋本發明。 如圖13(1)所示,將自第二光阻圖案他與及舰 板400之兩平面突出之部份移除,藉以將犧牲基板糊O: \ 89 \ 89662.DOC -37- 1242647 In addition, the etching depth range of the grooves 404 and 406 formed on the sacrificial substrate 400 above and below the plane A and B is 70 to 100 microns, which is for subsequent planarization The removal depth of the process is considered, so the etching depth is relatively deeper than the obtained conductor depth (ie, 60 microns). Then, as shown in FIG. 13a (e), the first photoresist patterns 402a and 402b remaining on the sacrificial substrate 400 above and below the planar substrate 3 are removed by a wet etching process using a chemical solvent. Next, as shown in FIG. 13a (f), seed layers 408a and 408b are formed, and a plating process is performed to form conductors on two planes of the sacrificial substrate 400. The seed layer here is composed of a titanium layer with a thickness of 500 angstroms and a copper layer with a thickness of 5,000 angstroms. The copper layer is used as a seed layer for electroplating in the subsequent plating process, and the titanium layer is used to improve the adhesion between the sacrificial substrate 400 and the copper layer. Then, as shown in Fig. 13a (g), a second photoresist pattern a "41b is formed by a photolithography process to open predetermined portions on the two planes a and b of the sacrificial substrate 4". As shown in the figure, the electrolytic f electric process is used to form the conductors 412a and 412b opened on the two planes A and B of the sacrificial substrate 00 with the second photoresist pattern 41. The second photoresist pattern 41 (41) OB is a conductive material such as nickel (Ni) or nickel alloy (Co Nl-W_co) deposited by electrolytic shell plating to form conductors 412a and 412b on a sacrificial substrate 400. ', Figure 13b ⑴ to ⑻ The longitudinal and lateral views are explained to explain the present invention. As shown in FIG. 13 (1), the part protruding from the two planes of the second photoresist pattern and the plane 400 is removed to paste the sacrificial substrate.

O:\89\89662.DOC -38- 1242647 之兩平面A與B平坦化。此處之平坦化製程係利用化學機械 拋光(CMP)法、研磨法、折疊(lapping)法及拋光法等施行。 但在用以形成導體412a與412b之理想電鑛製程之進程中, 僅於具探針外型之槽404與406内形成導體412a與412b(利 用第二光阻圖案41〇a與4 l〇b開啟)之情況下,平坦化製程即 可略之。此外,在導體412a與412b平坦化之後,以鍍金製 私於其上平面上形成鍵金層,藉以改善導體傳導率。 此外,在利用除電鍍製程外之方法如物理汽相沉積(pVD) 與化學汽相沉積(CVD)形成導體412a與412b之情況下,先前 形成種層408a與408b之製程即可略之。 接著如圖13b⑴所示,利用微影製程形成第三光阻圖案 414,以開啟犧牲基板400之上平面a上之中央部。 接著如圖13b(k)所示,以等向性乾餘刻製程將利用第三光 阻圖案414開啟之區域蝕刻。在此蝕刻至包含導體41仏形成 處在内之整體犧牲層的一半,藉以形成第一渠溝416。 接著如圖13c(l)所示,在將施加於第一渠溝416中充作介 私貝用之壤氧化物420熱塑化後,並在環氧化物42〇固化 前,將供支撐用之陶曼板418黏著於其上部。由於陶竟板4ΐδ 係由硬貝材料構成,故陶瓷板具有用以抵禦施加於探針上 之特定外力而避免探針形變之支撐組件功能,並可達成維 持探針外型之功能。 當完成形成環氧化物420與陶瓷板418之製程後,即完成 在犧牲板400之上平面a上之製程。 現將描述在犧牲基板4〇〇之下平面B上之其餘製程。O: \ 89 \ 89662.DOC -38- 1242647 The two planes A and B are flattened. The planarization process here is performed using a chemical mechanical polishing (CMP) method, a polishing method, a lapping method, and a polishing method. However, in the process of forming an ideal electric mining process for forming the conductors 412a and 412b, the conductors 412a and 412b are formed only in the grooves 404 and 406 having a probe shape (using the second photoresist patterns 41a and 41). b)), the planarization process can be omitted. In addition, after the conductors 412a and 412b are flattened, a gold bonding layer is formed on the upper surface thereof in gold plating to improve the conductivity of the conductor. In addition, in the case where the conductors 412a and 412b are formed by methods other than the plating process such as physical vapor deposition (pVD) and chemical vapor deposition (CVD), the previous process of forming the seed layers 408a and 408b can be omitted. Next, as shown in FIG. 13b (a), a third photoresist pattern 414 is formed by a photolithography process to open the central portion on the plane a above the sacrificial substrate 400. Next, as shown in FIG. 13b (k), the area turned on by the third photoresist pattern 414 is etched by an isotropic dry-etching process. Here, half of the entire sacrificial layer including the place where the conductor 41 仏 is formed is etched to form the first trench 416. Next, as shown in FIG. 13c (l), after the soil oxide 420 applied to the first trench 416 as a mediator is used for thermoplasticizing, and before the epoxy 420 is cured, it will be used for support. The Taoman plate 418 is adhered to the upper part. Since the ceramic plate 4ΐδ is made of hard shell material, the ceramic plate has a supporting component function to resist the specific external force applied to the probe and avoid the deformation of the probe, and can achieve the function of maintaining the appearance of the probe. After the process of forming the epoxide 420 and the ceramic plate 418 is completed, the process on the plane a above the sacrificial plate 400 is completed. The remaining processes on the plane B below the sacrificial substrate 400 will now be described.

O:\89\89662.DOC -39- 1242647 接著如圖13c㈣所示,利用微影製程形成第四光阻圖案 424,以開啟犧牲基板400之下平面b上之中央部。 接著如圖13c(n)所示,U等向性乾钮刻製程將利用第四光 阻圖案424開啟之區域姓刻。在此兹%至包含導體41以形成 處在内之整體犧牲層的一半,藉以形成用以露出環氧化物 420之第二渠溝426。 而後如圖13d(o)所示,將施加於第二渠溝426中充作介電 質用之環氧化物428熱塑化。接著如圖中所示,與上平面a 類似,亦將由硬質材料構成之陶究板附接於犧牲基板4〇〇之 下平面B中之環氧化物428之上部上。 此外,如圖13d(P)所示,利用預定化學物同時移除犧牲基 板400之上下平面上之光阻圖案414與424,接著利用化學物 如氫氧化鉀(KOH)及四甲基氫氧化氨(TMAH)選擇性蝕刻其 餘犧牲基板400。 結果即可依MEMS製程完成上下導體412&與41213呈交替 配置之用以測試平面板顯示器之導體。 換吕之’用以形成圖13b(k)中所示渠溝416與426之等向性 乾姓刻製程’係使用具特定比例之Sp6、與之混合氣 體之乾蝕刻製程。更特別言之,係利用所謂的波許製程施 行钱刻製程’其係一源自深渠溝蝕刻法之反應離子蝕刻 (RIE)。 在完成在犧牲基板4〇〇之上下平面A與B上施行之所有製 程後’即切割犧牲基板4〇〇,俾將犧牲基板4〇〇之上平面上 形成之複數個導體分割為具預定數量導體之預定單元之探O: \ 89 \ 89662.DOC -39- 1242647 Then, as shown in FIG. 13 (c), a fourth photoresist pattern 424 is formed by a photolithography process to open the central portion on the plane b below the sacrificial substrate 400. Next, as shown in FIG. 13c (n), the U isotropic dry button engraving process will use the last name of the area where the fourth photoresist pattern 424 is turned on. Here, half of the entire sacrificial layer including the conductor 41 to form the place is formed to form a second trench 426 for exposing the epoxide 420. Then, as shown in Fig. 13d (o), an epoxide 428 applied to the second trench 426 as a dielectric is thermally plasticized. Then, as shown in the figure, similar to the upper plane a, a ceramic plate made of a hard material is also attached to the upper portion of the epoxide 428 in the lower plane B of the sacrificial substrate 400. In addition, as shown in FIG. 13d (P), the photoresist patterns 414 and 424 on the upper and lower planes of the sacrificial substrate 400 are simultaneously removed by using a predetermined chemical, and then using chemicals such as potassium hydroxide (KOH) and tetramethyl hydroxide Ammonia (TMAH) selectively etches the remaining sacrificial substrate 400. As a result, the upper and lower conductors 412 & and 41213 are alternately configured for testing the conductors of the flat panel display according to the MEMS process. In another word, "the isotropic dry name engraving process for forming the trenches 416 and 426 shown in Fig. 13b (k)" is a dry etching process using a specific proportion of Sp6 and a mixed gas. More specifically, the so-called Bosch process is used to perform the money engraving process, which is a reactive ion etching (RIE) derived from the deep trench etching method. After completing all processes performed on planes A and B above and below the sacrificial substrate 400, the sacrificial substrate 400 is cut, and the plurality of conductors formed on the plane above the sacrificial substrate 400 are divided into a predetermined number Probe into the predetermined unit of conductor

O:\89\89662.DOC -40- 1242647 針群。 、之如圖25所示,切割犧牲基板400使得各導體群均 具12個導體,接著即形成探針。 °之,在上平面A上形成之各導體較在下平面b上形 ^之〇 $體之一末端部像外突出,且向外突出部長度均 同。因此,以前揭方法製造之探針,因施加於上下探針之 壓力均等而有利於探針操作。 依前揭方法製造之探針外型示如圖14。 圖14係閣釋以圖13所示製程製造之具單—犧牲基板之探 針之透視圖。 /如圖14所不,導體36(^與36叽分別以對應之預定間隔平 订配置於犧牲基板之上下平面上。導體3術與⑽祕利用 傳導材料之嵌人以微影製程與㈣製程於⑨犧牲基板之上 下平面上形成之第一渠溝中而形成。此外,均係由導電率 較忒寺導體鬲之材料製之薄層之傳導層,位於各導體“Μ 與36〇b之一平面上,以改善導體360a與360b之傳導率。 此外,亚於探針之上下部上形成介電質“。與%^。介 電質362a與雇係藉由施加介電f材料於以钱刻製程形成 於犧牲基板之兩平面上之第二渠溝中而形成。在此之介電 質材料為環氧化物較佳。 最終,在探針中具支撐組件364。支撐組件364係於介電 質362a與362b之至少-外平面上形成。支揮組件⑹係由硬 質材料構成較佳。支樓組件係藉由附接—陶£板於介電質 362a與362b上而形成較佳。 、O: \ 89 \ 89662.DOC -40-1242647 needle group. As shown in FIG. 25, the sacrificial substrate 400 is cut so that each conductor group has 12 conductors, and then a probe is formed. °, each of the conductors formed on the upper plane A protrudes outwardly than one of the ends of the body formed on the lower plane b, and the lengths of the outward protrusions are the same. Therefore, the probes manufactured by the previously disclosed method facilitate the operation of the probes because the pressure applied to the upper and lower probes is equal. The appearance of the probe manufactured according to the previous method is shown in Figure 14. FIG. 14 is a perspective view of a probe with a single-sacrificial substrate manufactured by the process shown in FIG. 13. / As shown in Fig. 14, the conductors 36 (^ and 36 平) are arranged on the upper and lower planes of the sacrificial substrate at corresponding predetermined intervals, respectively. It is formed in the first trench formed on the upper and lower planes of the sacrificial substrate. In addition, the conductive layers are made of a thin layer of a material having a higher conductivity than that of the Temple ’s conductor. On a plane to improve the conductivity of the conductors 360a and 360b. In addition, dielectrics are formed on the top and bottom of the probe. "And% ^. The dielectric 362a and the dielectric are applied by applying a dielectric f material to The money engraving process is formed in the second trench on the two planes of the sacrificial substrate. The dielectric material here is preferably an epoxide. Finally, there is a supporting component 364 in the probe. The supporting component 364 is connected to The dielectrics 362a and 362b are formed on at least the outer plane. It is preferable that the supporting members are made of hard materials. The supporting members are preferably formed by attaching ceramic plates to the dielectrics 362a and 362b. ...

O:\89\89662.DOC -41 - 1242647 (具體實施例2 - 6) 如圖15a(a)所示,將兩平面均經拋光之平坦矽(§丨)晶圓製 備為犧牲基板450。利用研磨製程或拋光製程所得之犧牲基 板450深度為4〇〇至5〇〇微米。 而後如圖15a(b)所示,利用濺鍍製程於犧牲基板45〇之整 個上平面A上形成第一種層452。此處之第一種層牦2係由厚 500埃之鈦層與厚5,〇〇〇埃之銅層構成。銅層實質上係充作 後續電鍍製程中之種層。鈦層則係用以改善犧牲基板45〇與 銅層之黏著性。 接著如圖15a(c)所示,利用微影製程形成第一光阻圖案 454,以於犧牲基板45〇之上平面a上開啟預定形成導體處: 接著如圖15a(d)所示,以電解質電鍍法沉積傳導材料如鎳 (Ni)或鎳合金(Ni-Co、Ni_w_c〇)而形成第一導體456。 接著如圖15a(e)所示,藉由移除第一導體456之上平面之 不均勻部而將其上平面平坦化。平坦化製程係利用化學機 械抛光(CMP)法、研磨法、折疊法、拋光法及研磨法等施行。 但在用以形成第一導體456之理想電鍍製程之進程中,僅 於利用第一光阻圖案454開啟處形成第一導體456之情況 下,平坦化製程即可略之。 此外,在利用除電鍍製程外之方法如物理汽相沉積(pvd) 與化學汽相沉積(CVD)形成第一導體456之情況下,先前形 成第一種層452之製程即可略之。 而後如圖15a(e)所示,於第一導體456之上部上施行鍍金 製程,藉以形成第一鍍金層458。此製程之目的係在改^探O: \ 89 \ 89662.DOC -41-1242647 (specific embodiments 2-6) As shown in Fig. 15a (a), a flat silicon (§ 丨) wafer with both surfaces polished is prepared as a sacrificial substrate 450. The sacrificial substrate 450 obtained by the grinding process or the polishing process has a depth of 400 to 5000 microns. Then, as shown in Fig. 15a (b), a first layer 452 is formed on the entire upper plane A of the sacrificial substrate 45 by a sputtering process. The first layer 牦 2 here is composed of a titanium layer with a thickness of 500 angstroms and a copper layer with a thickness of 5,000 angstroms. The copper layer is essentially used as a seed layer in the subsequent electroplating process. The titanium layer is used to improve the adhesion between the sacrificial substrate 45 and the copper layer. Next, as shown in FIG. 15a (c), a first photoresist pattern 454 is formed by a lithography process to open a predetermined conductor formed on the plane a above the sacrificial substrate 45. Then, as shown in FIG. 15a (d), The electrolytic plating method deposits a conductive material such as nickel (Ni) or a nickel alloy (Ni-Co, Ni_w_c0) to form the first conductor 456. Next, as shown in Fig. 15a (e), the upper plane of the first conductor 456 is flattened by removing uneven portions of the plane above the first conductor 456. The planarization process is performed using a chemical mechanical polishing (CMP) method, a polishing method, a folding method, a polishing method, and a polishing method. However, in the process of forming an ideal plating process for forming the first conductor 456, the planarization process may be omitted only in the case where the first conductor 456 is formed using the first photoresist pattern 454 turned on. In addition, in the case where the first conductor 456 is formed by a method other than the electroplating process such as physical vapor deposition (pvd) and chemical vapor deposition (CVD), the process of forming the first layer 452 previously may be omitted. Then, as shown in Fig. 15a (e), a gold plating process is performed on the upper portion of the first conductor 456 to form a first gold plating layer 458. The purpose of this process is to reform

O:\89\89662.DOC -42- 1242647 針之傳導率。 而後如圖15a(f)所示,利用濕韻刻製程移除第一光阻圖案 454。在此亦移除第一種層452之外露部。 接著如圖15a(g)所示’利用微影製程形成第二光阻圖案 460,以開啟第一導體456之預定部。 接著如圖15a(h)所不,施加具黏著劑功能之熱塑性環氧化 物462於第-導體456上利用第二光阻圖案46〇開啟處。 而後如圖15b⑴所示,在環氧化物咐固化前,附接陶竟 板464於環氧化物462之上部上。 接著如圖15b⑴所示,利用研磨製程將陶瓷板464之上平 面平坦化。此處之平坦化製程與第—具體實施例相同。當 完成平坦化製程後,即完成在犧牲基板45〇之上平面A上之 製程。 現將描述在犧牲基板450之下平面B上之製程。 首先如圖15b(k)所示,犧牲基板45〇面朝下。 接著如圖15b(l)所示,利用研磨製程將犧牲基板45〇之下 平面B移除至犧牲基板450原始厚度的一半。因此,在研磨 製私後,所餘犧牲基板深度範圍約在24〇至25〇微米間。 接著如圖15b(m)所示,利用微影製程形成第三光阻圖案 466,以開啟犧牲基板450之下平面B上預定形成介電質處。 而後如圖15b(n)所示,利用非等向性乾蝕刻製程將利用第 三光阻圖案466開啟之犧牲基板450之預定部移除,藉以形 成渠溝467。同時間亦移除種層452。 而後如圖15b(o-l)所示,將充作介電質之熱塑性環氧化物 O:\89\89662.DOC -43- 1242647 468施加於渠溝467中。 利用研磨製程將環氧化物之上平 而後如圖15b(p-l)所示 面平坦化。 接著如圖15c(q-l)所示, 460及第三光阻圖案466, 犧牲基板450之其餘部份, 在此形成之導體可具有 等長部。 以濕蝕刻製程移除第二光阻圖案 並以採用KOH之濕蝕刻製程移除 藉以完成依本發明之單層探針。 自陶瓷板464中央向兩側突出之 現將描述依本發明之雙層探針製造方法。 接著如圖15c(0-2)所示,在完成圖⑽⑻之製程之狀能 下,在將充作介電質與黏著劑之環氧化物470加a竿溝術 中後,並在環氧化物470固化前,附接陶竟板⑺。雖然所 附接之陶瓷板與渠溝467外型類似為矩形平行六面體,但1 亦可為平行四邊形陶究板81〇,其中兩端8ιι與M2傾斜如圖 2U所不’·或可為步階形陶竟板82〇,其兩端821與822為步 I1白=如圖21b所不。結果在所製探針中,導體之向外突出 P等長ii:在k針操作期間,施加於所有探針針部處之屢 力相同。 接著如圖15c(p-2)所不,利用研磨製程將陶瓷板π]上平 面平坦化。此處之平坦化製程可與第—具體實施例相同。 而後如圖15d(q-2)所示,在犧牲基板45〇之下平面b平坦化 #於犧牲基板45G之整個下平面B上形成供導體形成㈣ 製程用之第二種層474。卩々结— 此處之弟二種層474係由厚500埃之 4層及厚5’GGG埃之銅層構成。銅層實質充作後續電鑛製程O: \ 89 \ 89662.DOC -42- 1242647 Needle conductivity. Then, as shown in FIG. 15a (f), the first photoresist pattern 454 is removed by a wet engraving process. The exposed part of the first layer 452 is also removed here. Next, as shown in FIG. 15a (g) ', a second photoresist pattern 460 is formed by a lithography process to open a predetermined portion of the first conductor 456. Next, as shown in Fig. 15a (h), a thermoplastic epoxide 462 having an adhesive function is applied to the first conductor 456 using the second photoresist pattern 46o to open. Then, as shown in Fig. 15b (a), before the epoxy is cured, a ceramic plate 464 is attached to the upper part of the epoxy 462. Next, as shown in FIG. 15b (a), the planar surface of the ceramic plate 464 is planarized by a grinding process. The planarization process here is the same as the first embodiment. When the planarization process is completed, the process on the plane A above the sacrificial substrate 45 is completed. The process on the plane B below the sacrificial substrate 450 will now be described. First, as shown in FIG. 15b (k), the sacrificial substrate 45 is faced down. Next, as shown in FIG. 15b (l), the plane B below the sacrificial substrate 45 is removed to half of the original thickness of the sacrificial substrate 450 by a polishing process. Therefore, after grinding and manufacturing, the remaining sacrificial substrate has a depth in the range of about 24 to 25 microns. Next, as shown in FIG. 15b (m), a third photoresist pattern 466 is formed by a lithography process to open a predetermined dielectric portion on the plane B below the sacrificial substrate 450. Then, as shown in FIG. 15b (n), a predetermined portion of the sacrificial substrate 450 opened by the third photoresist pattern 466 is removed by using an anisotropic dry etching process to form a trench 467. The seed layer 452 is also removed at the same time. Then, as shown in FIG. 15b (o-1), a thermoplastic epoxy O: \ 89 \ 89662.DOC -43-1242647 468 as a dielectric is applied to the trench 467. The top surface of the epoxide is planarized by a polishing process, and then the surface is planarized as shown in Fig. 15b (p-1). Next, as shown in FIG. 15c (q-1), 460 and the third photoresist pattern 466, and the rest of the sacrificial substrate 450, the conductor formed here may have an equal length portion. The second photoresist pattern is removed by a wet etching process and removed by a wet etching process using KOH to complete the single-layer probe according to the present invention. Projecting from the center of the ceramic plate 464 to both sides will now describe a method for manufacturing a double-layered probe according to the present invention. Next, as shown in Fig. 15c (0-2), after completing the process of Fig. 能, after adding epoxide 470, which is used as a dielectric and an adhesive, to a rod groove operation, Before curing the 470, attach the pottery plate. Although the attached ceramic plate is similar to a rectangular parallelepiped in appearance to the trench 467, 1 can also be a parallelogram ceramic plate 81, in which the ends 8 and 1 are tilted as shown in Figure 2U. It is a step-shaped ceramic plate 82, and its two ends 821 and 822 are step I1 white = as shown in Figure 21b. As a result, in the manufactured probe, the conductor protrudes outward P is the same length ii: During the k-pin operation, the repeated force applied to all probe pins is the same. Next, as shown in Fig. 15c (p-2), the planar surface of the ceramic plate?] Is flattened by a grinding process. The planarization process here may be the same as that in the first embodiment. Then, as shown in FIG. 15d (q-2), the plane b under the sacrificial substrate 45 is flattened. # A second layer 474 for the conductor formation process is formed on the entire lower plane B of the sacrificial substrate 45G. Knotting-The two layers 474 here are composed of 4 layers with a thickness of 500 angstroms and a copper layer with a thickness of 5'GGG angstrom. The copper layer is essentially used for the subsequent power mining process

O:\89\89662.DOC -44- 1242647 中之種層。鈦層則係用以改善犧牲基板45〇與銅層之黏 性。 接著如圖15d(q-2)所示,在形成第二種層474時,利用微 影製程形成第四光阻圖案476,以開啟犧牲基板450之下平 面B上預定形成導體處。 接著★圖15d(r-2)所不,利用電解質電鑛法沉積傳導材料 如鎳㈣或鎳合金(Ni-C。、Ni_w_c。)而形成第二導體478。 妾著々圖15d(s-2)所不’藉由移除第二導體上平面之 不均勾部而將其上平面平坦化。此處施行之平坦化製程盘 第一具體實施例採用之方法相同。但在用以形成第二導體 W想電鑛製程之進程中,僅於第四光阻圖案Μ之開 啟部内形成導體之情況下,平坦化製程可略之。 此外,在利用除電鍍製程外之方法如物理汽相沉積㈣D) 與=學汽相沉積(CVD)形成第二導體478之情況下m 需前述種層’故形成第二種層474之製程即可略之。而後於 第二導體478之上部上施行鍍金製程,藉以形成第二鍍金層 480。此製程之目的在改善探針之傳導率。 而後如圖15d(t-2)所示,利用濕钱刻製程移除第四光阻圖 案467。同時間亦將自導體指向外突出之第二種層⑽移 除。接著利用微影製程形成第五光阻圖案482,以開啟第二 導體478中預定形成支撐組件處。 接著如圖15d(u-2)所示,技#备日&四 )所不,將熱塑性環氧化物484施加於利 用第五光阻圖案482開啟之部分第二導體478上。 而後如圖15e(v-2)所不,利用研磨製程將所施加之環氧化O: \ 89 \ 89662.DOC -44- 1242647. The titanium layer is used to improve the adhesion between the sacrificial substrate 45 and the copper layer. Next, as shown in FIG. 15d (q-2), when the second layer 474 is formed, a fourth photoresist pattern 476 is formed by a lithography process to open a predetermined conductor on the plane B below the sacrificial substrate 450. Next, as shown in Fig. 15d (r-2), a conductive material such as nickel hafnium or a nickel alloy (Ni-C., Ni_w_c.) Is deposited by an electro-electrolytic method to form a second conductor 478. Fig. 15d (s-2) shows that the upper plane of the second conductor is flattened by removing the uneven hook portion of the upper plane of the second conductor. The first specific embodiment of the flattening process disk implemented here uses the same method. However, in the process of forming the second conductor W and the electric ore manufacturing process, only in the case where a conductor is formed in the opening portion of the fourth photoresist pattern M, the planarization process can be omitted. In addition, in the case where the second conductor 478 is formed using a method other than the electroplating process such as physical vapor deposition (D) and chemical vapor deposition (CVD), m requires the aforementioned layers, so the process of forming the second layer 474 is Can be omitted. Then, a gold plating process is performed on the upper portion of the second conductor 478 to form a second gold plating layer 480. The purpose of this process is to improve the conductivity of the probe. Then, as shown in FIG. 15d (t-2), the fourth photoresist pattern 467 is removed by a wet money engraving process. At the same time, the second layer, which protrudes outward from the conductor, is also removed. Then, a fifth photoresist pattern 482 is formed by using a photolithography process to open a predetermined supporting component in the second conductor 478. Next, as shown in Fig. 15d (u-2), the technique # 备 日 & 四) does not apply a thermoplastic epoxide 484 to a portion of the second conductor 478 opened by the fifth photoresist pattern 482. Then, as shown in Figure 15e (v-2), the applied epoxidation is performed by a grinding process.

O:\89\89662.DOC -45- 1242647 物484之上平面平坦化。此處之平坦化製程與第一具體實施 例相同。 而後如圖15e(w-2)所示,利用濕蝕刻製程移除第五與第二 光阻圖案482與460。 取終,而後如圖15e(x-2)所示,以使用K〇H之濕蝕刻製程 移除梦犧牲基板450之殘餘部分。 依前述方法製造之探針外型示如圖16。 圖16係闡釋以圖15所示製程,利用單一犧牲基板製造之 探針結構。 依圖15中之製程製造之探針包括在中央部之介電質 370,示如圖丨6。藉由附接環氧化物通與陶竟板鳩而形 成戒電質370。換言之,利耗刻製程於犧牲基板之預訂部 上形成渠溝,將環氧化物37〇a施加於渠溝中,並在環氧化 物固化前’插入與附接陶£板3·,藉以形成介電们7〇。 此處之環氧化物370a係充作黏著劑之用。 此外,以預定間隔將導體372a與372b平行配置於介電質 570之上下平面上。利用微影製程於犧牲基板之上下平面上 之預:部上形成第一保護膜圖案’接著將傳導材料沉積於 利用第保5蒦臈圖案開啟之區域,藉以形成導體與 迎。此處’在以電解質電鍍法形成傳導材料之情況下:、 預先於犧牲基板之上下平面上形成種層。 此外 电率較導體3 72a與3 72b高之材料製成之傳導 層374a與374b’係位於導體灿與咖之一平面上,以改 善導體傳導率。此處之傳導材料為金(Au)較佳。O: \ 89 \ 89662.DOC -45-1242647 The plane on object 484 is flattened. The planarization process here is the same as that of the first embodiment. Then, as shown in FIG. 15e (w-2), the fifth and second photoresist patterns 482 and 460 are removed by a wet etching process. Finally, as shown in FIG. 15e (x-2), the remaining portion of the dream sacrificial substrate 450 is removed by a wet etching process using KOH. The appearance of the probe manufactured according to the aforementioned method is shown in FIG. 16. FIG. 16 illustrates a probe structure fabricated using a single sacrificial substrate using the process shown in FIG. 15. The probe manufactured according to the process in FIG. 15 includes a dielectric 370 in the center, as shown in FIG. 6. By attaching an epoxide channel to Tao Jingbanqiu, a dielectric substance 370 is formed. In other words, a cost-cutting process forms a trench on the predetermined portion of the sacrificial substrate, applies epoxide 37〇a in the trench, and inserts and attaches the ceramic plate 3 · before the epoxy solidifies, thereby forming Dielectrics 70. Here, epoxide 370a is used as an adhesive. In addition, the conductors 372a and 372b are arranged in parallel on the upper and lower planes of the dielectric 570 at predetermined intervals. The lithography process is used to form a first protective film pattern on the sacrificial substrate, and then a conductive material is deposited on the area opened with the 5th pattern to form a conductor and a welcome. Here, when a conductive material is formed by an electrolytic plating method, a seed layer is formed in advance on a plane above and below the sacrificial substrate. In addition, the conductive layers 374a and 374b 'made of a material having a higher electrical conductivity than the conductors 3 72a and 3 72b are located on one of the surfaces of the conductors to improve the conductivity of the conductors. The conductive material here is preferably gold (Au).

O:\89\89662.DOC -46- 1242647 最終,於介電質之上下平面上形成支撐組件376a與 376b,俾保護與固定導體372a與372b。支撐組件376a與37讣 係由環氧化物或以環氧化物附接與固定之陶瓷構成較佳。 以代號3 7 8表示支撐板。 (具體實施例2-7) 如圖17a(a)所示’將碎晶圓之兩平面抛光,以製備為犧牲 基板550。利用研磨製程或拋光製程製成之犧牲基板55〇厚 400至500微米。 而後如圖17a(b)所示,利用微影製程形成第一光阻圖案 552 ’已開啟犧牲基板550之預定形成介電質處。 而後如圖17a(c)所示,利用第一光阻圖案552蝕刻犧牲基 板550之上平面a至預定深度,以形成渠溝551。此處之蝕刻 深度範圍在240至250微米,較欲形成之介電質之厚度24〇微 米略深。 接著如圖圖17a(d)所示,在將充作介電質與黏著劑用之環 氧化物554施加於渠溝551中之後,並在環氧化物551固化 則,附接陶瓷板556。雖然所附接之陶質板之外型與渠溝551 類似為矩形平行六面體,但陶瓷板82〇亦可為兩端8ιι與812 傾斜如圖2U所示之平行四邊形,或者陶兗板82〇可為兩端 82丨與822為步階狀之步階形。結果在所製探針中,導體向 外突出部長度相同,使得探針操作期間施加於所有探針針 部之壓力均等。 而後如圖17a(e)所示,利用研磨製程將陶瓷板兄6之上平 面平坦化。此處之平坦化製程與第一具體實施例相同。在O: \ 89 \ 89662.DOC -46- 1242647 Finally, supporting components 376a and 376b are formed on the upper and lower planes of the dielectric, and the conductors 372a and 372b are protected and fixed. The support members 376a and 37 讣 are preferably made of epoxide or ceramics attached and fixed with epoxide. The support plate is denoted by the code 3 7 8. (Specific embodiment 2-7) As shown in FIG. 17a (a), the two surfaces of the broken wafer are polished to prepare a sacrificial substrate 550. The sacrificial substrate 55 manufactured by a grinding process or a polishing process is 400 to 500 microns thick. Then, as shown in FIG. 17a (b), the first photoresist pattern 552 'is formed by the lithography process, and the predetermined dielectric portion of the sacrificial substrate 550 is turned on. Then, as shown in Fig. 17a (c), the first photoresist pattern 552 is used to etch the plane a above the sacrificial substrate 550 to a predetermined depth to form a trench 551. The etching depth here ranges from 240 to 250 microns, which is slightly deeper than the thickness of the dielectric to be formed, which is 240 microns. Next, as shown in Fig. 17a (d), after an epoxide 554 serving as a dielectric and an adhesive is applied to the trench 551, and the epoxide 551 is cured, a ceramic plate 556 is attached. Although the shape of the attached ceramic plate is rectangular parallelepiped similar to the trench 551, the ceramic plate 820 can also be a parallelogram inclined at both ends 8 ι and 812 as shown in Figure 2U, or a ceramic slab 82 ° may be a step shape whose ends 82 丨 and 822 are step-like. As a result, in the manufactured probe, the length of the outwardly protruding portion of the conductor is the same, so that the pressure applied to all the probe pins during the probe operation is equal. Then, as shown in Fig. 17a (e), the upper surface of the ceramic plate 6 is flattened by a grinding process. The planarization process here is the same as the first embodiment. in

O:\89\89662.DOC -47- 1242647 將陶竞板556之上平面平坦化時,利用㈣製程於犧牲基板 550的整個上平面a形成供導體形成電鑛製程用之第—種声 558 〇 曰 此處之第一種層558係由厚5〇〇埃之鈦層與厚5,〇〇〇埃之 銅層構成。銅層實質上係充作後續電鑛製程中之種層。欽 層則係用以改善犧牲基板550與銅層之黏著性。 接著如圖17a(f)所示,利用微影製程形成第二光阻圖案 560’以於犧牲基板55〇之上平面a上開啟預定形成導體處。 接著如圖17伽所示,以電解質電鍍法沉積傳導材料如鎳 ⑽或錄合金(Nl_Co、Ni_ w_c〇)而形成第一導體犯。 接著如圖17a⑻所示,藉由移除第-導體562之上平面之 不均勻部或過量形成部而將其上平面平坦化。此處之平坦 化製程與第一具體實施力所揭方法相同。 但在用以形成第-導體562之理想電鐘製程之進程中,僅 於利用第二光阻圖案560開啟處形成導體之情況下,平坦化 製程即可略之。 此外,在利用除電鑛製程外之方法如物理汽相沉積(pvD) 與化學汽相沉積(CVD)形成第—導體如之情況下,形成第 一種層5 5 8之製程即可略之。 而後如圖17b(i)所示,於笛 〜 I 於弟一導體562之上部上施行鍍金 製程,藉以形成第一鍍金層564。此製程之目的係在改善探 針之傳導率。 而後如圖17吨)所不,形成第一保護膜566以保護在犧牲 土板550之上平面A上形成之第_導體562,以及第一鍍金層O: \ 89 \ 89662.DOC -47- 1242647 When flattening the upper surface of the ceramic plate 556, the entire upper plane a of the sacrificial substrate 550 is formed by using the sacrificial process to form the first sound 558 for the conductor to form the electric mining process. The first layer 558 here is composed of a titanium layer with a thickness of 5000 angstroms and a copper layer with a thickness of 5,000 angstroms. The copper layer is essentially used as a seed layer in the subsequent electric mining process. The Qin layer is used to improve the adhesion between the sacrificial substrate 550 and the copper layer. Next, as shown in FIG. 17a (f), a second photoresist pattern 560 'is formed by a lithography process to open a predetermined conductor on a plane a above the sacrificial substrate 55. Next, as shown in FIG. 17A, a conductive material such as nickel hafnium or an alloy (Nl_Co, Ni_w_co) is deposited by an electrolytic plating method to form a first conductor element. Next, as shown in Fig. 17a (a), the upper plane of the first conductor 562 is flattened by removing uneven portions or excessively formed portions of the plane above the first conductor 562. The planarization process here is the same as the method disclosed in the first embodiment. However, in the process of forming the ideal electric clock of the -conductor 562, the planarization process can be omitted only in the case where the conductor is formed by using the opening of the second photoresist pattern 560. In addition, in the case where the first conductor is formed by a method other than the power ore process such as physical vapor deposition (pvD) and chemical vapor deposition (CVD), the process of forming the first layer 5 58 can be omitted. Then, as shown in FIG. 17b (i), a gold plating process is performed on the upper part of the dipole conductor 562 to form a first gold plating layer 564. The purpose of this process is to improve the conductivity of the probe. Then, as shown in FIG. 17T), a first protective film 566 is formed to protect the first conductor 562 and the first gold plating layer formed on the plane A above the sacrificial soil plate 550.

O:\89\89662.DOC -48 , 1242647 5 64。在此係以膠帶或光阻充作保護膜。 結果即已完成犧牲基板550之上平面A上之製程,接著開 始在其下平面B上之製程。 首先如圖17b(k)所示,犧牲基板5 50面朝下,並利用研磨 或抛光法研磨犧牲基板550之下平面B。將犧牲基板550研磨 至得以露出陶瓷板556之厚度。 接著如圖17b(l)所示,於犧牲基板550之整個下平面b上形 成供導體形成電鍍製程用之第二種層568。而後利用微影製 程形成第三光阻圖案570,以開啟犧牲基板55〇之下平面6 上預定形成導體部。 而後如圖17b(m)所示,於利用第三光阻圖案57〇開啟處上 形成第二導體572。 接著如圖17b(n)所示,若第二導體572之上平面不均勻, 則於其上平面上施行平坦化製程。在此之平坦化製程與第 一具體實施力所揭方法相同。 但在用以形成第二導體572之理想電鍍製程之進程中,僅 於第二光阻圖案570之開啟部内形成第二導體Μ之情況 下,平坦化製程可略之。 此外,在利用除電鑛製程外之方法如物理汽相沉積(pvc 與,學汽相沉積(CVD)形成第:導體⑺之情況下,先_ 成第二種層568之製程可略之。 而後如圖17b(o)所示,於第—瀑 乐一¥體572之上平面上施行邀 孟‘程’藉以形成第二鑛全肩 、 又至層574。此製程之目的在改善拐 針傳導率。而後利用濕蝕O: \ 89 \ 89662.DOC -48, 1242647 5 64. Here is a protective film with tape or photoresist. As a result, the process on the plane A above the sacrificial substrate 550 has been completed, and then the process on the plane B below it has begun. First, as shown in Fig. 17b (k), the sacrificial substrate 550 faces downward, and the lower plane B of the sacrificial substrate 550 is polished by grinding or polishing. The sacrificial substrate 550 is polished to a thickness where the ceramic plate 556 is exposed. Next, as shown in Fig. 17b (l), a second layer 568 is formed on the entire lower plane b of the sacrificial substrate 550 for the conductor forming plating process. Then, a third photoresist pattern 570 is formed by a photolithography process to open a conductor portion on the plane 6 below the sacrificial substrate 55. Then, as shown in FIG. 17b (m), a second conductor 572 is formed on the place where the third photoresist pattern 57 is turned on. Next, as shown in FIG. 17b (n), if the plane above the second conductor 572 is not uniform, a planarization process is performed on the upper plane. The planarization process here is the same as the method disclosed in the first implementation. However, in the course of an ideal plating process for forming the second conductor 572, only in the case where the second conductor M is formed in the opening portion of the second photoresist pattern 570, the planarization process may be omitted. In addition, in the case of using methods other than the process of power ore such as physical vapor deposition (PVC and CVD) to form the first: conductor, the process of forming the second layer 568 can be omitted. As shown in Fig. 17b (o), the “Meng Cheng” process is performed on the plane above the first waterfall body 572 to form the second shoulder of the entire mine, and then to the layer 574. The purpose of this process is to improve the needle conduction Wet erosion

衣私將在犧牲基板550之上平SClothing private will flat S on the sacrificial substrate 550

O:\89\89662.DOC -49- 1242647 A上形成之第 案 560與 570。 -保護膜移除,並同時移除第二與第三光阻圖 在此亦移除第二種層568之外露部。 而後如圖17c⑻所示,於犧牲基板55〇之上平面A上形成 第二保護膜576,以保護上平面a。接著利用微影製程形成 第四光阻圖案578,以開啟第二導體572上預定形成支撐缸 件處。 接著而後如圖17c(q)所示,將熱塑性環氧化物58〇施加於 利用第四光阻圖案578開啟處。 而後如圖17c(r)所#,利用研磨製程將環氧化物之上 平面平坦化。平坦化製程與第一具體實施例相同。 而後如圖17c(s)所示,將犧牲基板55〇之上平面a上之第 二保護膜576移除。接著形成第五光阻圖案582,以開啟第 一導體562之預定形成支撐組件處。 接著如圖17c⑴所示,施加熱塑性環氧化物584於利用第 五光阻圖案582開啟處,接著利用研磨製程將環氧化物π# 之上平面平坦化。 最終如圖17c(u)所示,以濕蝕刻製程同時移除第四與第五 光阻圖案578與582,並以使用KON之濕蝕刻製程選擇性移 除第一與第二導體562與572間之犧牲基板55〇殘餘部分。 在移除犧牲基板550後,即完成本發明之探針。 (具體實施例2 - 8 ) 如圖1 8a所示,將兩平面被拋光之矽晶圓製備為犧牲芙板 650 ’以研磨製程或拋光製程製備之犧牲基板65〇厚24〇微 米0 O:\89\89662.DOC -50- 1242647 接著如圖l8a(b)所示,將犧牲基板65〇之下平面3附接一 膠帶以避免污染,或者塗佈一塗佈材料652如光阻於其上。 接著如圖18a(C)所示,利用切方製程以預定外型沿切割部 653切割犧牲基板650之中央部。 接著如圖18a(d)所示,將以切方製程產生具預定尺寸之犧 牲基板區塊654,亦即中央矽區塊’自犧牲基板65〇移除。 結果即在犧牲基板650之中央部上形成渠溝655。 接著如圖18a(e)所示,將充作介電質用之陶瓷板656插入 渠溝655中,接著施加環氧化物658,將之嵌入陶瓷板656與 犧牲基板650間之間隙中。此處之環氧化物具有附接陶瓷板 565與犧牲基板650之功能。 接著如圖18a(f)所示,將犧牲基板65〇之上平面a平坦化。 接著如圖18a(g)所示,將在犧牲基板65〇之下平面B上形 成之塗佈材料652移除,並與犧牲基板65〇之上平面a類似, 將下平面B平坦化。 接著如圖1 8a(h)所示,於犧牲基板650之整個下平面b上 形成供導體形成電鐘製程用之第一種層660與662。 此處之第一種層660與662係由厚500埃之鈦層及厚5,000 土矢之銅層構成。銅層係充作後續電鍍製程中電鍍之種層 用’鈦層則係用以改善犧牲基板650與銅層間之黏著性。 接著如圖18a(i)所示,於犧牲基板650之下平面B上形成用 以保護種層662之第一保護膜667,並利用微影製程於犧牲 基板65 0之上平面a上形成第一光阻圖案664,以開啟犧牲基 板650之預定導體形成處。O: \ 89 \ 89662.DOC -49- 1242647 A. Cases 560 and 570. -The protective film is removed, and the second and third photoresist patterns are removed at the same time. The exposed part of the second layer 568 is also removed here. Then, as shown in FIG. 17c (a), a second protective film 576 is formed on the plane A above the sacrificial substrate 55 to protect the upper plane a. Then, a fourth photoresist pattern 578 is formed by a photolithography process, so as to turn on the second conductor 572 where a support cylinder is to be formed. Then, as shown in Fig. 17c (q), a thermoplastic epoxide 58 is applied to the place where the fourth photoresist pattern 578 is turned on. Then, as shown in FIG. 17c (r), the upper surface of the epoxide is planarized by a polishing process. The planarization process is the same as the first embodiment. Then, as shown in Fig. 17c (s), the second protective film 576 on the plane a above the sacrificial substrate 55 is removed. A fifth photoresist pattern 582 is then formed to turn on the first conductor 562 at a predetermined formation supporting member. Next, as shown in FIG. 17c (a), a thermoplastic epoxide 584 is applied at the opening where the fifth photoresist pattern 582 is opened, and then a plane above the epoxide π # is planarized by a grinding process. Finally, as shown in FIG. 17c (u), the fourth and fifth photoresist patterns 578 and 582 are simultaneously removed by a wet etching process, and the first and second conductors 562 and 572 are selectively removed by a wet etching process using KON. The remaining portion of the sacrificial substrate 55 is left in between. After the sacrificial substrate 550 is removed, the probe of the present invention is completed. (Specific embodiments 2 to 8) As shown in FIG. 18a, a silicon wafer with two planes polished is prepared as a sacrificial wafer 650 '. The sacrificial substrate 65 prepared by a grinding process or a polishing process is 65 mm thick and 240 μm: \ 89 \ 89662.DOC -50- 1242647 Then, as shown in Fig. 18a (b), attach a tape to the plane 3 below the sacrificial substrate 65 to avoid contamination, or apply a coating material 652 such as a photoresist on it on. Next, as shown in FIG. 18a (C), the center portion of the sacrificial substrate 650 is cut along the cutting portion 653 with a predetermined shape by a tangent process. Then, as shown in FIG. 18a (d), a sacrificial substrate block 654 having a predetermined size, that is, a central silicon block, is removed from the sacrificial substrate 65 by a tangent process. As a result, a trench 655 is formed in the central portion of the sacrificial substrate 650. Next, as shown in Fig. 18a (e), a ceramic plate 656 serving as a dielectric is inserted into the trench 655, and then an epoxide 658 is applied and embedded in the gap between the ceramic plate 656 and the sacrificial substrate 650. The epoxide here has a function of attaching the ceramic plate 565 and the sacrificial substrate 650. Next, as shown in FIG. 18a (f), the plane a above the sacrificial substrate 65o is flattened. Next, as shown in FIG. 18a (g), the coating material 652 formed on the plane B below the sacrificial substrate 650 is removed, and similar to the plane a above the sacrificial substrate 650, the lower plane B is planarized. Next, as shown in FIG. 18a (h), the first layers 660 and 662 for the conductor clock process are formed on the entire lower plane b of the sacrificial substrate 650. The first layers 660 and 662 here consist of a titanium layer with a thickness of 500 angstroms and a copper layer with a thickness of 5,000 soil layers. The copper layer is used as a seed layer for electroplating in the subsequent electroplating process. The titanium layer is used to improve the adhesion between the sacrificial substrate 650 and the copper layer. 18a (i), a first protective film 667 for protecting the seed layer 662 is formed on the plane B below the sacrificial substrate 650, and a photolithography process is used to form a first protective film 667 on the plane a above the sacrificial substrate 650. A photoresist pattern 664 is used to open a predetermined conductor formation portion of the sacrificial substrate 650.

O:\89\89662.DOC -51 - 1242647 而後如圖18a⑴所示,於利用第一光阻圖案6料開啟處上 形成第一導體666。此處之第一導體666係藉由電解質電鍍 去沉積傳導材料如鎳(Ni)或鎳合金(Ni_c〇、Ni_w_c〇)而形 接著如圖18b(k)所示,藉由移除第一導體666之上平面之 不均勻處而將第一導體666之上平面平坦化。在此之平坦化 製程與第一具體實施例所揭方法相同。 但在用以形成第一導體666之理想電鍍製程之進程中,僅 於第一光阻圖案664之開啟部内形成第一導體666之情況 下,平坦化製程即可略之。 而後於第一導體666之整個上部上施行鍍金製程,藉以形 成一第一鍍金層668。 此外,在利用除電鑛製程外之方法如物理汽相沉積(PVD) 與化學汽相沉積(CVD)形成第一導體666之情況下,由於無 舄種層,故先前形成第一種層660之製程可略之。 接著如圖18b(l)所示,利用膠帶或光阻於形成第一導體 666處开》成用以保護犧牲基板650之上平面A之第二保護膜 670。在完成第二保護膜67〇之形成後,即完成在犧牲基板 650之上平面A上之弟一製程。而後將犧牲基板朝下,接著 移除用以保護犧牲基板650之下平面之保護膜667。 現將描述犧牲基板650之下平面B上之製程。 接著如圖1 8b(m)所示,利用微影製程形成第二光阻圖案 672 ’以開啟犧牲基板650之下平面B上預定形成導體處。 接著如圖18b(n)所示,於利用第二光阻圖案672開啟部上 O:\89\89662.DOC -52- 1242647 形成第二導體674。此處係利用電鍍製程沉積傳導材料如鎳 (Ni)或錄合金(Ni_c〇、Ni_w_c〇)而形成第三導體。八 接著如圖18b(0)所示,藉由移除第二導體674之上平面之 不均:處,將其上平面平坦化。此處之平坦化製程與第一 具體實施例所揭方法相同。在平坦化製程完成後,於第二 導體674之整個上部上施行鍍金製程,藉以形成第二鍍金: 仁在用以形成第^導體674之理想電路製程之進程中,僅 於利用第二光阻圖案672開啟處内形成導體之情況下,平坦 化製程即可略之。 一 此外,在利用除電鑛製程外之方法如物理汽相沉積㈣D) 舆化學汽相沉積(CVD)形成第二導體⑺之情況下,先前形 成種層662之製程可略之。 接著如圖18b(P)所示’利用濕蚀刻製程移除第二光阻圖案 672。在此亦移除第二種層662之外露部。此外,可同時移 除受第二保護膜670保護之第一光阻圖案664。 接著如圖18b⑷所示,利用微影製程形成第三光阻圖案 678 ’以開啟第二導體674中預定形成支撐組件處。 接著如圖18C⑴所示’利用第三光阻圖案678為模,施加 環氧化物680於第二導體674之開啟部。 接著如圖18c(s)所示,利用研磨製程將環氧化物680之上 平面平坦化。 '接著如圖18C⑴所示’移除在犧牲基板650之上平面a上形 成之第—保4膜670。接著則濕㈣製程移除第“光阻圖O: \ 89 \ 89662.DOC -51-1242647 Then, as shown in Fig. 18a, a first conductor 666 is formed on the opening using the first photoresist pattern. Here, the first conductor 666 is formed by depositing a conductive material such as nickel (Ni) or a nickel alloy (Ni_c0, Ni_w_c〇) by electrolytic plating, followed by removing the first conductor as shown in FIG. 18b (k). The unevenness of the plane above 666 flattens the plane above the first conductor 666. The planarization process here is the same as the method disclosed in the first embodiment. However, in the process of forming an ideal plating process for forming the first conductor 666, only in the case where the first conductor 666 is formed in the opening portion of the first photoresist pattern 664, the planarization process may be omitted. Then, a gold plating process is performed on the entire upper portion of the first conductor 666, thereby forming a first gold plating layer 668. In addition, in the case where the first conductor 666 is formed by using methods other than the power ore process such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), since there is no seed layer, the first layer 660 was previously formed. The process can be omitted. Next, as shown in FIG. 18b (l), a second protective film 670 is formed on the plane A above the sacrificial substrate 650 by using an adhesive tape or a photoresist at the place where the first conductor 666 is formed. After the formation of the second protective film 67o is completed, the process of the brother on the plane A on the sacrificial substrate 650 is completed. Then, the sacrificial substrate is directed downward, and then the protective film 667 for protecting the lower surface of the sacrificial substrate 650 is removed. The process on the plane B below the sacrificial substrate 650 will now be described. Next, as shown in FIG. 18b (m), a second photoresist pattern 672 'is formed by a lithography process to open a predetermined conductor position on the plane B below the sacrificial substrate 650. Next, as shown in FIG. 18b (n), a second conductor 674 is formed on O: \ 89 \ 89662.DOC -52-1242647 on the opening of the second photoresist pattern 672. Here, a third conductor is formed by depositing a conductive material such as nickel (Ni) or an alloy (Ni_co, Ni_w_co) by an electroplating process. Next, as shown in FIG. 18b (0), the upper plane of the second conductor 674 is removed by flattening it. The planarization process here is the same as the method disclosed in the first embodiment. After the planarization process is completed, a gold plating process is performed on the entire upper portion of the second conductor 674 to form a second gold plating: In the process of forming an ideal circuit for the ^ th conductor 674, only the second photoresist is used. When a conductor is formed in the opening of the pattern 672, the planarization process can be omitted. In addition, in the case of using a method other than a power ore process such as physical vapor deposition (D) and chemical vapor deposition (CVD) to form the second conductor, the previous process of forming the seed layer 662 can be omitted. Next, as shown in FIG. 18b (P) ', the second photoresist pattern 672 is removed by a wet etching process. The exposed part of the second layer 662 is also removed here. In addition, the first photoresist pattern 664 protected by the second protective film 670 can be removed at the same time. Then, as shown in FIG. 18b (a), a third photoresist pattern 678 'is formed by using a lithography process to open a predetermined supporting component in the second conductor 674. Next, as shown in FIG. 18C ', using the third photoresist pattern 678 as a mold, an epoxide 680 is applied to the opening of the second conductor 674. Next, as shown in FIG. 18c (s), a plane above the epoxide 680 is planarized by a polishing process. 'Next, as shown in FIG. 18C', the first-protection film 670 formed on the plane a above the sacrificial substrate 650 is removed. Then the wet process removes the "photoresist

O:\89\89662.DOC -53 - 1242647 案664,且—併移除種層660之外露部。 接著如圖⑻所利用微影製程形成第四光阻圖宰 681,以開啟第一導體666中預定形成支撐組件處。而後利 用弟四光阻圖案682施加環氧化物684於導體咖之開啟部 上。接著利用研磨製程將環氧化物684之上平面平坦化。 接著如圖18C(V)所示,利用濕姓刻製程同時移除第三與第 四光阻圖案678與682 ’且—併以使用κ〇Η之濕钱刻製程移 除犧牲基板650之殘餘部分。 接著如圖I8c(w)所示,在移除環氧化物658後,即完成本 發明之探針。 (具體貫施例2-9) 如圖19a(a)所示,將兩平面經均抛光之陶竟板製備為犧牲 基板750。經過研磨製程或拋光製程後之犧牲基板π叫彻 至500微米。 接著如圖19a⑻所*,利用切方製程於犧牲基板75〇之上 平面A上之預定部上形成兩渠溝752。 接著如圖19a(c)所示,於犧牲基板75〇之上平面a上形成 渠溝752處形成供銅電鍍結構形成電鍍製程用之第一種層 754,並形成渠溝,其中以銅電鍍結構作為渠溝埋入材料' 此處之第一種層754係由鈦層與銅層構成。 接著如圖19a(d)所示,利用微影製程形成第一光阻圖宰 756,以開啟犧牲基板750之上平面人上預定形成渠溝乃2處^ 接著如圖19a(e)所示,利用電鍍製程在為第一光阻圖案 756開啟之渠溝上形成作為渠溝埋入材料用之鍍銅結構 O:\89\89662.DOC -54- 1242647 758 ° 接著如圖19a(f)所示,移除第一光阻圖案756以及自犧牲 基板750向上突出之部分鍍銅結構758,藉以將犧牲基板 之上平面A平坦化。施行平坦化製程直到犧牲基板75〇之上 平面A表面與鍍銅結構758相互毗鄰為止。 接著如圖19a(g)所示,於犧牲基板75〇之上平面a上形成 供導體形成電鏟製程用之第二種層76〇。此處之第二種層 760係由厚5〇〇埃之鈦層及厚5,_埃之銅層構成。銅層實^ 上係充作後續電鍍製程中電鑛之種制,鈦層則係用以提 升犧牲基板750與銅層間之黏著性。 接著如圖19b⑻所示’利用微影製程形成第二光阻圖案 762,以開啟犧牲基板75〇上預定形成導體處。 乂著如圖19b⑴所示,在利用第二光阻圖案—開啟處上 形成第-導體764。在此係以電解質電鍍法沉積傳導材料如 鎳(N〇或錄合金(Ni_Co、Nl專c〇)而形成第一導體⑽。 接著如圖19b(j)所示 藉由移除第一導體764之上平面之 此處之平坦化製程與第一 不均勻處而將其上平面平坦化 具體實施例所揭方法相同。 但在用以形成第-導體764之理想電鍵製程之進程中,僅 於弟二光阻圖案762之開啟部内形成導體之情況拉化 製程即可略之。 一 此外,在利用除電鍍製程外O: \ 89 \ 89662.DOC -53-1242647 Case 664, and—and remove the exposed part of the seed layer 660. Then, a fourth photoresist pattern 681 is formed using a photolithography process as shown in FIG. ,, so as to open a predetermined supporting component in the first conductor 666. Then, an epoxide 684 is applied to the opening of the conductor using the photoresist pattern 682. Then, a planarization process is performed on the top surface of the epoxide 684 by a polishing process. Then, as shown in FIG. 18C (V), the third and fourth photoresist patterns 678 and 682 ′ are simultaneously removed by a wet last process, and the residue of the sacrificial substrate 650 is removed by a wet money process using κ〇Η. section. Then, as shown in Fig. I8c (w), after the epoxide 658 is removed, the probe of the present invention is completed. (Specific Example 2-9) As shown in Fig. 19a (a), a ceramic plate having both surfaces polished is prepared as a sacrificial substrate 750. The sacrificial substrate π after being polished or polished is called 500 micrometers. Next, as shown in FIG. 19a, two trenches 752 are formed on a predetermined portion on the plane A above the sacrificial substrate 75 by a tangent process. Next, as shown in FIG. 19a (c), a trench 752 is formed on the sacrificial substrate 75 on the plane a to form a first layer 754 for the copper plating structure to form a plating process, and a trench is formed, in which copper plating is used. The structure is used as a trench-buried material 'The first layer 754 here is composed of a titanium layer and a copper layer. Next, as shown in FIG. 19a (d), a first photoresist pattern 756 is formed using a lithography process to open two predetermined trenches on a flat surface above the sacrificial substrate 750. Then, as shown in FIG. 19a (e) A copper-plated structure is formed on the trench opened for the first photoresist pattern 756 as a trench buried material by an electroplating process. O: \ 89 \ 89662.DOC -54- 1242647 758 ° Then as shown in Figure 19a (f) As shown, the first photoresist pattern 756 and a portion of the copper-plated structure 758 protruding upward from the sacrificial substrate 750 are removed, thereby planarizing the plane A above the sacrificial substrate. The planarization process is performed until the surface A of the plane A and the copper-plated structure 758 above the sacrificial substrate 75 are adjacent to each other. Next, as shown in Fig. 19a (g), a second layer 76o is formed on the plane a above the sacrificial substrate 75o for the conductor forming process. The second layer 760 here is composed of a titanium layer with a thickness of 500 angstroms and a copper layer with a thickness of 5 angstroms. The copper layer is used as a seed for electric ore during the subsequent electroplating process, and the titanium layer is used to improve the adhesion between the sacrificial substrate 750 and the copper layer. Next, as shown in FIG. 19b (a), a second photoresist pattern 762 is formed by a lithography process to open a predetermined conductor formed on the sacrificial substrate 75o. As shown in Fig. 19b, a -conductor 764 is formed on the place where the second photoresist pattern is opened. Here, the first conductor ⑽ is formed by depositing a conductive material such as nickel (N0 or alloy (Ni_Co, N1)) by an electrolytic plating method. Then, as shown in FIG. 19b (j), the first conductor 764 is removed 764 The planarization process of the upper plane here is the same as the method disclosed in the first embodiment for planarizing the upper plane of the unevenness. However, in the process of forming the ideal key bond process of the -conductor 764, only The drawing process of the case where a conductor is formed in the opening of the second photoresist pattern 762 can be omitted. In addition, in addition to the use of the plating process

私跟衣枉外之方法如物理汽相沉積(PVE 與化學汽相沉積(CVD)形成第 士、# — )成弟冷體764之情況下,先前5 烕弟一種層760之製程即可略之。In the case of methods other than clothing, such as physical vapor deposition (PVE and chemical vapor deposition (CVD) to form Di Shi, # —) to form the cold body 764, the previous process of a layer 760 can be omitted. Of it.

O:\89\89662.DOC -55- 1242647 接著如圖19b(k)所示,於第一導體764之整個上部上施行 鍍金製程,藉以形成第一鍍金層766。 接著如圖19b(l)所示,在犧牲基板750之上平面a上形成用 以保護第一導體764之保護膜768,並形成第一鍍金層766, 在前述製程完成前即已完成在犧牲基板75〇之上平面a上 之製程。 現將描述在犧牲基板750之下平面b上之製程。 首先如圖19b(m)所示,以研磨製程研模犧牲基板75〇到直 得以露出犧牲基板750之下平面b與鍍銅結構758之下平面 之程度。 接著如圖19b(n)所示,於犧牲基板75〇之整個下平面上形 成供導體形成電鍍製程用之第三種層77〇。此處之第三種層 770係由厚500埃之鈦層及厚5,〇〇〇埃之銅層構成。銅層實質 上係充作後續電鍍製程中電鍍之種層用,鈦層則係用以改 善犧牲基板750與銅層間之黏著性。接著利用微影製程形成 第二光阻圖案772,以開啟犧牲基板75〇之上平面上預定形 成導體處。 接者如圖19c(〇)所示,於利用第三光阻圖案772開啟處上 形成第二導體774。在此係以電解質電鍍法沉積傳導材料如 鎳(Ni)或鎳合金(Ni_c〇、Ni_ w_c〇)而形成第三導體774。 接者如圖19c(p)所示,藉由移除第三導體774之上平面之 不均勻處,將其上平面平坦化。此處之平坦化製程與第一 具體實施例中所揭方法相同。在完成平坦化製程後,、於第 三導體774之整個上部上施行鍍金製程,藉以形成第二鍍金O: \ 89 \ 89662.DOC -55- 1242647 Then, as shown in FIG. 19b (k), a gold plating process is performed on the entire upper portion of the first conductor 764 to form a first gold plating layer 766. Next, as shown in FIG. 19b (l), a protective film 768 for protecting the first conductor 764 is formed on the plane a above the sacrificial substrate 750, and a first gold-plated layer 766 is formed. Process on the plane a above the substrate 75. The process on the plane b below the sacrificial substrate 750 will now be described. First, as shown in FIG. 19b (m), the sacrificial substrate 75 is mold-molded in a polishing process until the plane b below the sacrificial substrate 750 and the plane below the copper-plated structure 758 are exposed. Next, as shown in Fig. 19b (n), a third layer 770 for forming a conductor for electroplating is formed on the entire lower plane of the sacrificial substrate 75o. The third layer 770 here is composed of a titanium layer with a thickness of 500 angstroms and a copper layer with a thickness of 5,000 angstroms. The copper layer is essentially used as a seed layer for electroplating in the subsequent plating process, and the titanium layer is used to improve the adhesion between the sacrificial substrate 750 and the copper layer. Next, a second photoresist pattern 772 is formed by a lithography process to open a predetermined conductor formed on the plane above the sacrificial substrate 75 °. As shown in FIG. 19c (0), a second conductor 774 is formed on the place where the third photoresist pattern 772 is opened. Here, the third conductor 774 is formed by depositing a conductive material such as nickel (Ni) or a nickel alloy (Ni_co, Ni_w_co) by an electrolytic plating method. As shown in FIG. 19c (p), the upper plane is flattened by removing unevenness on the plane above the third conductor 774. The planarization process here is the same as the method disclosed in the first embodiment. After the planarization process is completed, a gold plating process is performed on the entire upper portion of the third conductor 774 to form a second gold plating process.

O:\89\89662.DOC -56- 1242647 層776 但在用以形成第三導體774 价隻一上 里心私鍍製程之進程中,僅 、-先阻圖案772之開啟部内形成導體之情 製程即可略之。 卞一 1匕 此外’在利用除電鍍製程外之方… 物理&相沉積(P VD) 舁,相沉積(CVD)形成第三導體774之情況下,先前形 成第二種層770之製程即可略之。 接著如圖丨9e⑷所[制錢_料除㈣膜偏, 並㈣移除第二與第三光阻圖案762與772。此處,也會移 除第二種層760及第三種層770。 接著如圖19d⑴所示,利用微影製程形成第四與第五光阻 圖案778與780,以開啟第一與第二導體764與774中預定形 成支撐組件處。 / 接著如圖19d(s)所示,於利用第四光阻圖案778開啟之部 为弟一導體7 7 4上施加熱塑性環氧化物7 $ 2。 接著如圖19d(t)所示,利用研磨製程將環氧化物782之上 平面平坦化。 接著如圖19d(u)所示,利用相同製程於犧牲基板75〇之上 平面上形成環氧化物層784。接著如圖19d(v)所示,利用研 磨製程將環氧化物784之上平面平坦化。 接著如圖19d(w)所示,利用濕蝕刻製程同時將殘留在犧 牲基板750之上下平面上之第四與第五光阻圖案778與78〇 移除。 最終藉由施加外力於殘餘犧牲基板7 5 0上而移除犧牲基 O:\89\89662.DOC -57- 1242647 极^並且藉由選擇性餘刻製程來移除渠溝埋入材料 758,藉以完成本發明之探針。 換σ之’圖20闡釋依圖π、18與19所示方法製造之探針 結構。 圖20係闡釋藉由使用根據本發明實施例製造之 所形成之探針的剖視圖。 如圖20所示,介電質38〇位於探針之中央部,導體382a與 382b刀別以預定間隔位於介電質彻之上下平面上。此外, 支樓、、且件384a舆384b分別附接於介電質38〇之上下平面上 導體382a與382b所在處。此外,由導電率較導體382&與3似 之材料構成之薄層386a與386b分別位於導體382a與382b之 外平面上。 ' 仏形成’I私負用之渠溝係於犧牲基板之預定部上形成, :著將介電質材料嵌入渠溝中,藉以形成介電質38〇。介電 質材料為陶变較佳。介電質兩端之剖面可具步階差外型或 傾斜外型。利用微影製程於介電質380之兩平面上形成第一 保濩膜,並接著於利用第一保護膜開啟之區域上沉積傳導 材料而形成導體382a與382b。此外,利用微影製程於犧牲 基板之兩平面上形成導體382a與382b處形成第二保護膜, 亚接著將支撐材料嵌入利用第二保護膜開啟之區域中,藉 以形成支標組件384a與384b。 此外,依具體實施例2-6製造之使用單一犧牲基板之探針 結構與圖25相同。因此,探針結構之細部描述略之。 圖2 la係闡釋本發明中使用之陶瓷板之透視圖與剖面O: \ 89 \ 89662.DOC -56- 1242647 Layer 776 However, in the process of forming the third conductor 774, the price is only 100%, and the process of forming the conductor only involves the formation of a conductor in the opening of the first-resistance pattern 772. The process can be omitted. (1) In addition to the use of methods other than the plating process ... physical & phase deposition (PVD) 舁 In the case of phase deposition (CVD) to form the third conductor 774, the previous process of forming the second layer 770 is Can be omitted. Then, as shown in FIG. 9e, the film deviation is removed, and the second and third photoresist patterns 762 and 772 are removed. Here, the second layer 760 and the third layer 770 are also removed. Then, as shown in FIG. 19d (b), the photolithography process is used to form the fourth and fifth photoresist patterns 778 and 780, so as to open the first and second conductors 764 and 774 to form predetermined support components. / Next, as shown in FIG. 19d (s), a thermoplastic epoxide 7 $ 2 is applied to the first conductor 7 7 4 at the portion opened with the fourth photoresist pattern 778. Next, as shown in FIG. 19d (t), a plane above the epoxide 782 is planarized by a polishing process. Next, as shown in FIG. 19d (u), an epoxide layer 784 is formed on the plane above the sacrificial substrate 75 by the same process. Next, as shown in FIG. 19d (v), a plane above the epoxide 784 is planarized by a grinding process. Next, as shown in FIG. 19d (w), the fourth and fifth photoresist patterns 778 and 78o remaining on the upper and lower planes of the sacrificial substrate 750 are simultaneously removed by a wet etching process. Finally, the sacrificial substrate O: \ 89 \ 89662.DOC -57-1242647 is removed by applying an external force on the residual sacrificial substrate 7 50, and the trench buried material 758 is removed by a selective etching process, This completes the probe of the present invention. For σ ', Fig. 20 illustrates the structure of a probe manufactured according to the methods shown in Figs. Fig. 20 is a cross-sectional view illustrating a probe formed by using the probe according to an embodiment of the present invention. As shown in FIG. 20, the dielectric 38 is located at the center of the probe, and the conductors 382a and 382b are located at a predetermined interval above and below the dielectric. In addition, the branch towers 384a and 384b are respectively attached to the conductors 382a and 382b on the upper and lower planes of the dielectric 38o. In addition, the thin layers 386a and 386b made of a material having a conductivity higher than that of the conductors 382 & 3 are located on the outer planes of the conductors 382a and 382b, respectively. The formation of the trench is performed on a predetermined portion of the sacrificial substrate, and a dielectric material is embedded in the trench to form a dielectric 38. The dielectric material is preferably ceramic. The profile at both ends of the dielectric can have a stepped profile or an inclined profile. A lithography process is used to form a first protective film on the two planes of the dielectric 380, and then a conductive material is deposited on the area opened by the first protective film to form the conductors 382a and 382b. In addition, a lithography process is used to form the second protective film on the conductors 382a and 382b on the two planes of the sacrificial substrate, and then the supporting material is embedded in the area opened by the second protective film to form the anchor components 384a and 384b. In addition, the probe structure using a single sacrificial substrate manufactured according to the specific embodiment 2-6 is the same as that shown in FIG. Therefore, the detailed description of the probe structure is omitted. Fig. 2a is a perspective view and a cross-section illustrating a ceramic plate used in the present invention

O:\89\89662.DOC -58- 1242647 圖,其中剖面係平行四邊形;圖21b係闡釋本發明中使用之 陶瓷板之透視圖與刮面圖。這些外型適用於依本發明之所 有具體貫施例。 (探針組之第一具體實施例) π圖22a係闡釋具有依本發明之用以測試平面板顯示器之 =針之第—探針組之透視圖;圖—係其剖面圖。此處將不 資述前述探針片之特殊架構及其製造方法。 么翏閱1122a與22b ’在依本發明之第依具體實施例之探針 組中,其中有複數個單元結構附接與固定於一可透光模9〇1 2之探針,係固定於探針區塊9〇4之下部上。在此,各單元 =冓均包括具檢測尖端9〇2與連結尖端(未圖示)之光束構件 、,利用雙面膠帶或黏著劑使探針與探針區塊9〇4相互附接 並固定。探針區塊904係由可透光材料如丙稀酸製成,以確 保其透光性。 此外,第一介面板908位於探針區塊9〇4上方,相互間並 為4田門904之π齒合而固定。第二介面板91〇與探針固持器犯 依序位於第-介面板908上方,且相互間為錨閂914之嚙合 而固定。 匕卜第與第二介面板908與910為固定栓9〇7嚙合在一 起以進一步增加其間之嚙合力。第二介面板91〇與探針固 持器912間亦為固定栓911所嚙合,俾進一步增加其間之 合力。 位於探針片之光束構件_之一末端部處之連結尖端(未O: \ 89 \ 89662.DOC -58- 1242647 Figures, where the cross section is a parallelogram; Figure 21b illustrates a perspective view and a scraped view of a ceramic plate used in the present invention. These shapes are suitable for all specific embodiments according to the invention. (First specific embodiment of the probe set) π FIG. 22a is a perspective view illustrating a first probe set having a pin for testing a flat panel display according to the present invention; FIG. Is a sectional view thereof. The special structure of the aforementioned probe sheet and its manufacturing method will not be described here. Modal reading 1122a and 22b 'In the probe set according to the first embodiment of the present invention, there are a plurality of unit structures attached and fixed to a light-transmitting mold 9102, which is fixed to The lower part of the probe block 904. Here, each unit = 冓 includes a light beam member having a detection tip 902 and a connection tip (not shown), and the probe and the probe block 904 are attached to each other with a double-sided tape or an adhesive and fixed. The probe block 904 is made of a light-transmissive material such as acrylic acid to ensure its light-transmitting property. In addition, the first interface panel 908 is located above the probe block 904, and is fixed to each other by the π-tooth combination of 4 Tianmen 904. The second interface panel 91 and the probe holder are sequentially located above the first interface panel 908, and are fixed to each other by the engagement of the anchor 914. The first and second interface plates 908 and 910 are engaged with the fixing bolt 907 to further increase the meshing force therebetween. The second interface panel 91 and the probe holder 912 are also engaged by the fixing bolt 911, which further increases the combined force therebetween. The connecting tip (not at the end of one of the beam members of the probe sheet)

O:\89\89662.DOC -59- 1242647 圖示)經導引膜930連結至位於捲帶式封裝(Tcp)932上之圖 案。 更特別言之,該結構係藉由配置探針(形成連結尖端處) 於第一介面板980之下部上,並接著藉由固定組件922與錨 問9 2 4喷合捸針與第一介面板而構成。 更特別言之,將由絕緣陶瓷材料構成之上封閉黏著組件 926及下封閉黏著組件928分別插入探針與第一介面板9〇8 間及tcp 932與固定組件922間。此外,探針之連結尖端難 與TCP 932經由上下封閉黏著組件926與928間之導引膜93〇 相互連結。 此外,壓縮錨閂929進一步位於固定組件922之下部,使 得探針之連結尖端9〇2]3與1^? 932得以在錨閃929之轉動壓 縮下’經由導引膜932而更強烈連結在一起。 再者,以錨閃920將探針固持器912與操縱器916嚙合在一 起。在測試製程期間,可以物理力F將連結至操縱器916之 探針固持器912上下移動。 、更特別s之,探針固持器912之一側與操縱器916之一側 為導引執918嚙合在一起,使得第一介面板9〇8、連結至探 針固持裔912之第二介面板91〇,以及探針區塊9〇4得以於測 。式‘私期間,為上下物理力F上下移動。 特別g之,具預定彈力之彈簧921位於連結探針固持哭 912與操縱器916之固定組件92〇周圍,使得在測試製程: 間,為上下物理力?上下移動之第一介面板9〇8、連結至探 針口持杰912之第二介面板91〇以及探針區塊9〇4得以藉由O: \ 89 \ 89662.DOC -59- 1242647 (illustrated) is connected to the pattern on the tape and reel package (Tcp) 932 via the guide film 930. More specifically, the structure is configured by arranging a probe (forming the connection tip) on the lower part of the first interface panel 980, and then by using the fixing component 922 and the anchor 9 2 4 to spray the needle and the first interface Panel. More specifically, the upper closed adhesive component 926 and the lower closed adhesive component 928 made of an insulating ceramic material are inserted between the probe and the first interface panel 908 and between the TCP 932 and the fixed component 922, respectively. In addition, the connecting tip of the probe is difficult to be connected to the TCP 932 through the guide film 93 between the upper and lower closed adhesive components 926 and 928. In addition, the compression anchor bolt 929 is further located below the fixing component 922, so that the connection tip of the probe 902] 3 and 1 ^? 932 can be more strongly connected by the guide compression 932 under the rotation compression of the anchor flash 929. together. Furthermore, the probe holder 912 and the manipulator 916 are engaged with each other by the anchor flash 920. During the test process, the probe holder 912 connected to the manipulator 916 can be moved up and down by a physical force F. More specifically, one side of the probe holder 912 and one side of the manipulator 916 mesh with the guide holder 918 so that the first interface panel 908 and the second interface connected to the probe holder 912 are engaged. Plate 91 and probe block 904 were tested. The expression ‘Private period’ is the vertical physical force F to move up and down. In particular, the spring 921 with a predetermined elasticity is located around the fixed component 92o that connects the probe holding clamp 912 and the manipulator 916, so that during the test process, is the upper and lower physical force? The first interface panel 908 moving up and down, the second interface panel 91 and the probe block 904 connected to the probe port holder 912, and

O:\89\89662.DOC -60- J242647 彈簧921之彈力恢復至其初始位置。 在另-具體實施例中,如圖23所示,前述位於第一解面 板_之下部上之Μ組件可略之。此外,不具連結尖端與 TCP 932之探針光束構件位於非等向性傳導膜(ACF)935 上’並利用壓縮製程與加熱製程相互連結。O: \ 89 \ 89662.DOC -60- J242647 The spring force of the spring 921 returns to its initial position. In another embodiment, as shown in FIG. 23, the aforementioned M component located on the lower part of the first solution panel can be omitted. In addition, the probe beam member without the connection tip and TCP 932 is located on the anisotropic conductive film (ACF) 935 'and is connected to each other by a compression process and a heating process.

因此,將以一系列製造平面板顯示器之製程獲得之平面 板顯示器固接於-探測儀器上,並藉由移動裝置之移動探 針區塊904以及預定物理力之施加於平面板顯示器之電極 墊上。於平面板顯示器上施行電氣測試製程。 _此時,位於探針區塊904下部之檢測尖端9〇2與平面板顯 示器之電極墊接觸。輸入至探測儀器之電氣信號即經由TCP 932、探針光束構件與檢測尖端9〇2施加於平面板顯示器之 電極塾。 ' (探針組之第二具體實施例) 圖24a係闊釋具有依本發明之用以測試平面板顯示器之 掩針之第二探針組之透視圖;圖24b係其剖 前述探針架構及其製造方法。 將不头这 兄參閱圖24a與24b,在依本發明之第二具體實施例之第二 心針組中’以由金屬如不鏽鋼製成之高彈性金屬板936取代 探針組中位於第一介面板9〇δ下部處之可透光材料 衣鉍針區塊。金屬板936經錨閂9〇3固定於第一介面板卯$之 下錢’亚以黏著劑經由高彈性橡膠938固定探針於金屬板 936下部。 藉由施加預定物理力F於平面板顯示器之電極墊上而施Therefore, the flat panel display obtained by a series of processes for manufacturing the flat panel display is fixed on the detection instrument, and the mobile probe block 904 and the predetermined physical force are applied to the electrode pad of the flat panel display. . Perform an electrical test process on a flat panel display. _ At this time, the detection tip 902 located at the lower part of the probe block 904 is in contact with the electrode pad of the flat panel display. The electrical signal input to the detection instrument is applied to the electrode 塾 of the flat panel display via TCP 932, the probe beam member and the detection tip 902. '(Second specific embodiment of the probe set) FIG. 24a is a perspective view of a second probe set with a mask for testing a flat panel display according to the present invention; FIG. 24b is a cross-sectional view of the probe structure And its manufacturing method. Referring to Figs. 24a and 24b, in the second set of needles according to the second embodiment of the present invention, the first set of probes is replaced with a highly elastic metal plate 936 made of metal such as stainless steel, which is the first set The light-transmissive material is coated with bismuth needle blocks at the lower part of the interface board 90 °. The metal plate 936 is fixed to the first interface panel through the anchor 903, and the probe is fixed to the lower portion of the metal plate 936 with an adhesive through a high elastic rubber 938. By applying a predetermined physical force F to the electrode pad of the flat panel display

DOC 0:\的\89662 -61 - 1242647 行電氣測試製程時,由 ^ ΟΠδ-ττ^ ^ ^針組中具有位於第一介而 板〇8下邛處之彈性金屬 面 (探針組之第三體實施例)〃_938’故可增加彈性。 圖25係闡釋具有依本發 _係其❹i W之探針組之透視圖,·圖 ^圖25與26 ’在依本發明之第三具體實施例之探針組 六’多,探針係在一堆疊結構中。如上述,多層探針包括 又曰堆宜但不相互重疊之上探針之導體则與下探針之導 體950 木針之各導體96〇之一末端部較各導體㈣更為向 卜犬出且上下$體之外露部#長,冑具相^電氣與物理 性質及傳導性。 利用附接-固疋工具如錨閂將堆疊結構中之探針相互固 定於探針區塊955之傾斜平面上。探針區塊955可由可透光 材料如丙烯酸製成,以確保其透光性。 此外’第一介面板965位於探針區塊955上方。探針固持 1§ 970位於第一介面板965上方,且為錨閂967之嚙合固定在 一起。 第一介面板965與探針固持器970為固定栓967所嚙合,以 進一步增加其間的喷合力。 此外,第二介面板975亦藉由固定栓967之嚙合而固定於 第一介面板965之下平面上之探針區塊955背側。TCP 972 附接並固定於第二介面板975之下平面上。 就附接並固定於探針區塊955之傾斜平面上之TCP 972與 多層探針之導體950與960之連結而言,多層探針之各導體 O:\89\89662.DOC -62- 1242647 950與960之一端在一在導引膜974上形成之孔(未標示代號) 之導引下,連結至位於TCP 972上之對應圖案。 此外,以錨閂982將探針固持器970與操縱器980嚙合在一 起。在測試製程期間,可以上下物理力F將連結至操縱器980 之探針固持器970上下移動。 更特別言之,探針固持器970之一侧與操縱器980之一側 為導引執984嚙合在一起,使得連結至探針固持器970之第 一介面板965及探針區塊955得以於測試製程期間,為上下 物理力F上下移動。 特別言之,具預定彈力之彈簧986位於連結探針固持器 970與操縱器980之固定組件982周圍,使得在測試製程期 間,為上下物理力F上下移動之連結至探針固持器970之第 一介面板965及探針區塊955得以藉由彈簧986之彈力恢復 至其初始位置。 因此,將以一系列製造平面板顯示器之製程獲得之平面 板顯示器固接於一探測儀器上,並藉由移動裝置之移動探 針區塊955以及預定物理力之施加於平面板顯示器之電極 墊上。於平面板顯示器上施行電氣測試製程。 此時,位於探針區塊955下部之多層探針之針部950與960 與平面板顯示器之電極墊接觸。輸入至探測儀器之電氣信 號即經由TCP 972、探針光束構件與探針之針部950及960 施加於平面板顯示器之電極墊。 工業應用性 依本發明,易於利用切方鋸齒製程以及附接針狀導體之 O:\89\89662.DOC -63- 1242647 製程’在由硬質材料構成之 " 於得以縮減製造探針f 衣&探針,故優點在 此外,依本發明,可並因而增加生產率。 製程,並可利用光學對齊心==複數個導體之 數及人工操作差異造成之探針不對==熱膨㈣ 精確度對齊探針之優點。 -有可以較同 犧:L#先别技蟄中之製程不同,依本發明可採用單- 精確度之改善而提昇良率,=在::因製t之減少與 格,並可改善製程良率與生產率。了降低仏針生產價 雖已詳述本發明及其優點,應知本發明不以前述 施例及隨附圖式為限’熟悉此技藝者應知在不㈣隨附之 申請專利範圍所界定之本發明之精神與範訂,可 改變、取代及替換。 【圖式簡單說明】 自下列較佳具體實施例之描述暨隨附圖式,將可瞭解本 發明之上述及其他目的、優點與特徵,其中·· 圖la係闡釋依本發明一具體實施例之用以測試平面板顯 不态之探針及其製造方法之透視圖;圖“係圖^之縱向剖 面圖;圖lc係圖ia之橫向剖面圖; 圖2a與2b係闡釋依圖1&至ic製造之用以測試平面板顯示 器之探針之另一具體實施例之製程之透視圖;圖孔係圖以 之縱向剖面圖;圖2c係圖2a之橫向剖面圖; 圖3a至3e係闡釋依圖2a至2c製造之用以測試平面板顯示 O:\89\89662.DOC -64- 1242647 杰之揼針之另一具體實施例之製程之透視圖; 圖4a與处係闡釋依本發明之MEMS製程製造之用以測試 平面板顯示器之雙層探針之透視圖; 圖5a係闡釋依本發明之MEMS製程製造之用以測試平面 板頒不器之單層探針之透視圖;圖5b係圖5a之縱向剖面圖; 圖6a至6p係闡釋依另一具體實施例製造用以測試平面板 顯示器之探針之方法之剖面圖; 圖7a至7:ι係闡釋依另一具體實施例製造用以測試平面板 顯示器之探針之方法之剖面圖; 圖8a至8t係闡釋依另一具體實施例製造用以測試平面板 顯示器之探針之方法之剖面圖; 。。圖9係闡釋依另一具體實施例製造用以測試平面板顯示 斋之探針之方法之透視圖; 圖l〇a係闡釋依另一具體實施例之探針之放大透視圖 1 〇b係其剖面圖; 圖11係闡釋依另-具體實施例之用以測試平面板顯示哭 之探針之透視圖; 圖l_2a至12:1係闡釋依另—具體實施例製造用以測試平面 板頒示裔之探針之方法之剖面圖; 圖13a至13d係闡釋依另—具體實施例製造用以測試平面 板顯示器之探針之方法之各製程之剖面圖; 圖Η係依圖U a至13d所示方法製造之探針之透視圖; 圖,至15e係閣釋依另一具體實施例製造用以測試平面 板顯不器之探針之方法之各製程之剖面圖;DOC 0: \ 's \ 89662 -61-1242647 During the electrical test process, the ^ ΟΠδ-ττ ^ ^ ^ needle group has an elastic metal surface located at the bottom of the first interface plate 08 (the first of the probe group Three-body embodiment) 〃_938 'can increase flexibility. FIG. 25 is a perspective view illustrating a probe set having a probe according to the present invention, FIG. 25 and FIG. 25 and FIG. 25 are a diagram showing a probe set according to a third embodiment of the present invention; In a stacked structure. As mentioned above, the multi-layer probe includes the conductor of the upper probe, which does not overlap each other, but the conductor of the lower probe and the conductor of the lower probe 950. One end of each of the conductors of the wooden needle is more outward than the conductors. Moreover, the upper and lower parts of the body are exposed long, and have similar electrical and physical properties and conductivity. The probes in the stacked structure are fixed to each other on the inclined plane of the probe block 955 by using attachment-fixing tools such as anchors. The probe block 955 may be made of a light-transmissive material such as acrylic to ensure its light-transmitting property. In addition, the first interface panel 965 is located above the probe block 955. The probe holding 1 § 970 is located above the first interface panel 965 and is fixed together by the engagement of the anchor 967. The first interface plate 965 and the probe holder 970 are engaged by the fixing bolt 967 to further increase the spraying force therebetween. In addition, the second interface panel 975 is also fixed to the back side of the probe block 955 on the plane below the first interface panel 965 by the engagement of the fixing bolt 967. The TCP 972 is attached and fixed on a plane below the second interface panel 975. For the connection of TCP 972 and the conductors 950 and 960 of the multilayer probe attached and fixed on the inclined plane of the probe block 955, each conductor of the multilayer probe O: \ 89 \ 89662.DOC -62- 1242647 One end of 950 and 960 is guided by a hole (unlabeled) formed in the guide film 974, and is connected to a corresponding pattern on TCP 972. In addition, the probe holder 970 and the manipulator 980 are engaged with each other by the anchor 982. During the test process, the probe holder 970 connected to the manipulator 980 can be moved up and down by the up and down physical force F. More specifically, one side of the probe holder 970 and one side of the manipulator 980 are engaged with each other as a guide 984, so that the first interface panel 965 and the probe block 955 connected to the probe holder 970 can be During the test process, it moves up and down for the physical force F. In particular, the spring 986 with a predetermined elasticity is located around the fixed component 982 connecting the probe holder 970 and the manipulator 980, so that during the test process, the upper and lower physical forces F move up and down to the probe holder 970. An interface panel 965 and a probe block 955 can be restored to their initial positions by the spring force of the spring 986. Therefore, the flat panel display obtained by a series of processes for manufacturing the flat panel display is fixed to a detection instrument, and the mobile probe block 955 and a predetermined physical force are applied to the electrode pads of the flat panel display. . Perform an electrical test process on a flat panel display. At this time, the needle portions 950 and 960 of the multilayer probe located under the probe block 955 are in contact with the electrode pads of the flat panel display. The electrical signals input to the detection instrument are applied to the electrode pads of the flat panel display via TCP 972, the probe beam member and the needle portions 950 and 960 of the probe. Industrial Applicability According to the present invention, it is easy to use the tangent zigzag process and the O: \ 89 \ 89662.DOC -63- 1242647 process for attaching a needle conductor. The process is made of a hard material and can be reduced in manufacturing probes. & Probes have the additional advantage that, according to the present invention, productivity can be increased accordingly. Manufacturing process, and can use the optical alignment center == the number of conductors and the probe caused by the difference in manual operation == thermal expansion 对 the advantages of precision alignment probe. -It can be compared with the same sacrifice: the manufacturing process in L # is different. According to the present invention, a single method can be used.-The accuracy is improved to improve the yield, = in :: due to the reduction of the system t, and the process can be improved. Yield and productivity. Although the present invention and its advantages have been described in detail in order to reduce the production price of needles, it should be understood that the present invention is not limited to the foregoing embodiments and accompanying drawings. The spirit and model of the present invention can be changed, replaced and replaced. [Brief description of the drawings] The above and other objects, advantages, and features of the present invention will be understood from the description and accompanying drawings of the following preferred embodiments. Among them, FIG. 1a illustrates a specific embodiment according to the present invention. A perspective view of a probe for testing the appearance of a flat plate and a manufacturing method thereof; FIG. “Is a longitudinal sectional view of FIG. ^; FIG. Lc is a transverse sectional view of FIG. Ia; FIGS. 2a and 2b are explanatory views according to FIG. 1 & A perspective view of the manufacturing process of another specific embodiment of a probe for testing a flat panel display manufactured by IC; a picture hole is a longitudinal sectional view of the figure; FIG. 2c is a transverse sectional view of FIG. 2a; and FIGS. 3a to 3e are A perspective view illustrating the manufacturing process of another specific embodiment of the flat-panel display O: \ 89 \ 89662.DOC -64- 1242647 manufactured in accordance with FIGS. 2a to 2c; FIG. 4a and A perspective view of a double-layered probe for testing a flat panel display manufactured by the invented MEMS process; FIG. 5a is a perspective view illustrating a single-layered probe for testing a flat panel display device manufactured according to the MEMS process of the present invention; Fig. 5b is a longitudinal sectional view of Fig. 5a; Figs. 6a to 6p are explanations according to another Sectional views of a method for manufacturing a probe for testing a flat panel display according to a specific embodiment; Figures 7a to 7: ι are sectional views illustrating a method for manufacturing a probe for testing a flat panel display according to another embodiment; 8a to 8t are cross-sectional views illustrating a method for manufacturing a probe for testing a flat panel display according to another embodiment; FIG. 9 illustrates a probe for testing a flat panel display according to another specific embodiment; A perspective view of the method; FIG. 10a is an enlarged perspective view illustrating a probe according to another embodiment. FIG. 10b is a cross-sectional view thereof. FIG. 11 is a view illustrating a flat panel display according to another embodiment. A perspective view of a crying probe; Figures 1-2a to 12: 1 are cross-sectional views illustrating a method for manufacturing a probe for testing a flat panel display; Figures 13a to 13d are illustrating another method. Example A cross-sectional view of each process of a method for manufacturing a probe for testing a flat panel display; Figure Η is a perspective view of a probe manufactured according to the method shown in Figures Ua to 13d; A specific embodiment is manufactured to test flat Plates were cross-sectional views of a method of routing a probe of the device is not;

0;\89\89662.D〇C -65- I242647 圖16係依圖15a至15e所示方法製造之探針之透視圖; 圖17a至17<:㈣釋依另—具體實施例製造用以測試平面 板顯示器之探針之方法之各製程之剖面圖; 圖18a至18e係《釋依另—具體實施例製造用以測試平面 板顯示器之探針之方法之各製程之剖面圖; 圖19a至19d係闡釋依另—具體實施例製造用以測試平面 板顯示器之探針之方法之各製程之剖面圖,· 圖20係依圖i?u17d所示方法製造之探針之透視圖; 圖2la係闡釋本發明中使用之陶究板之透視圖與剖面 圖’其中剖面係平行四邊形;圖21b係闡釋本發明中使用之 陶瓷板之透視圖與剖面圖,其中剖面係步階形,· ”圖22a係闡釋具有依本發明之用以測試平面板顯示器之 探針之第一探針組之透視圖;圖22b係其剖面圖; 圖23係闡釋圖22與24中所示捲帶式封裝(Tcp)與單元導 體組件間之連結圖; ' 圖24a係闡釋具有依本發明之用以測試平面板顯示器之 探針之第二探針組之透視圖;圖24b係其剖面圖; 圖25係闡釋具有依本發明之探針之探針組之透視圖;及 圖26係闡釋具有依本發明之探針之探針組之剖面圖。 【圖式代表符號說明】 10,80 11 類板狀介電質 線 2〇a,20b ’ 50 ’ 284,286,302 ’ 312 ’ 360a, 導體 360b,372a,372b,412a,412b,950,9600; \ 89 \ 89662.D〇C -65- I242647 Figure 16 is a perspective view of a probe manufactured according to the method shown in Figures 15a to 15e; Figures 17a to 17 < Cross-sectional views of the various processes of the method for testing the flat-panel display probe; FIGS. 18a to 18e are cross-sectional views of the various processes of the method of manufacturing a probe for testing the flat-panel display by a specific embodiment; FIG. 19a 19 to 19d are cross-sectional views illustrating each process of a method for manufacturing a probe for testing a flat panel display according to another embodiment. FIG. 20 is a perspective view of a probe manufactured according to the method shown in FIG. 2la is a perspective view and a cross-sectional view of a ceramic plate used in the present invention, where the cross-section is a parallelogram; FIG. 21b is a perspective and a cross-sectional view of a ceramic plate used in the present invention, where the cross-section is a step shape. 22a is a perspective view illustrating a first probe set having a probe for testing a flat panel display according to the present invention; FIG. 22b is a cross-sectional view thereof; and FIG. 23 is a view illustrating a tape-and-reel type shown in FIGS. 22 and 24. The connection diagram between the package (Tcp) and the unit conductor assembly; 'Figure 24a A perspective view illustrating a second probe set having a probe for testing a flat panel display according to the present invention; FIG. 24b is a sectional view thereof; FIG. 25 is a perspective view illustrating a probe set having a probe according to the present invention And FIG. 26 is a cross-sectional view illustrating a probe set having a probe according to the present invention. [Description of Representative Symbols of the Drawings] 10, 80 11 Type Plate-shaped Dielectric Lines 20a, 20b '50' 284, 286 , 302 '312' 360a, conductor 360b, 372a, 372b, 412a, 412b, 950, 960

O:\89\89662.DOC -66 - 1242647 30a,30b,282,364,376a,376b 40 40a , 40b 60 70 90 , 100 , 218 , 308 , 318 9 卜 101,110 93 , 103 , 112 95 , 105 , 114 97a,97b,107a,144,467,551,655, 752 98 108 , 118 109,304,314,370a,370b,420,428, 462,470,484,554,580,658,684, 782 , 784 116a,256a,256b,334a,416 120,200,250,330,400,450,550, 650 , 750 122 , 202 , 261 124,204,262 126 , 206 , 260 , 336 , 408a , 408b 128,,208,252 129,210,254,332,402a,402b,454, 支撐組件 傳導材料 薄傳導材料 類板狀支樓組件 鑛金層 支撑板 第一突出區 中央槽 第二突出區 渠溝 下導體 上導體 環氧化物 第一渠溝 犧牲基板 欽層 銅層 種層 第一光阻 第一光阻圖案 O:\89\89662.DOC •67- 1242647 552 , 664 , 756 130 , 272 , 306 , 316 131 , 212 , 266 132a , 132b , 288 134 , 264 136,210,265,338,410a,410b,460, 560 , 762 138 , 148 , 282 , 378 140 , 214 142,222,270,414,560,570,678, 762 , 772 146 , 280 258 , 334b , 426 274 276 , 424 , 476 , 578 , 682 278 280 282 300 310 320 322 324a 324b 介電質板 傳導膜 對齊鍵 第二光阻 第二光阻圖案 支撐板 第三光阻 第三光阻圖案 黏著劑 第二渠溝 第四光阻 第四光阻圖案 第三渠溝 第一犧牲基板 第二犧牲基板 第一探針 第二探針 單元導體 光束構件 檢測尖端 連結尖端 O:\89\89662.DOC -68- 1242647 342 薄膜 370a,370b,418,472,556,656,810, 陶瓷板 820 362a , 362b , 370 介電質 374a , 374b 傳導層 386a , 386b 薄層 404 槽 452 , 558 , 660 , 662 , 754 第一種層 456 , 562 , 666 , 764 第一導體 458 , 564 , 668 , 766 第一鍍金層 474 , 568 , 760 第二種層 478 , 572 , 674 , 774 第二導體 480 , 676 , 776 第二鍍金層 482 , 578 , 582 第五光阻圖案 566 第一保護膜 576 , 670 第二保護膜 652 塗佈材料 653 切割部 654 犧牲基板區塊 667 , 768 保護膜 758 鍍銅結構 770 第三種層 774 第三導體 821 , 822 端 O:\89\89662.DOC -69- 1242647 900 902 904 , 955 907,91 卜 967 908 , 965 910 , 975 912 , 970 914,924,982 916 , 980 918 , 984 921 , 986 922 , 982 926 928 929 930 , 974 932 , 972 935 936 938 光束構件 檢測尖端 探針區塊 固定栓 第一介面板 第二介面板 探針固持器 錨閂 操縱器 導引執 彈簧 固定組件 上封閉黏著組件 下封閉黏著組件 壓縮錨閂 導引膜 捲帶式封裝 非等向性傳導膜 金屬板 高彈性橡膠 O:\89\89662.DOC -70-O: \ 89 \ 89662.DOC -66-1242647 30a, 30b, 282, 364, 376a, 376b 40 40a, 40b 60 70 90, 100, 218, 308, 318 9 Bu 101, 110 93, 103, 112 95, 105, 114 97a, 97b, 107a, 144, 467, 551, 655, 752 98 108, 118 109, 304, 314, 370a, 370b, 420, 428, 462, 470, 484, 554, 580, 658, 684, 782, 784 116a, 256a, 256b, 334a, 416 120, 200, 250, 330, 400, 450, 550, 650, 750 122, 202, 261 124, 204, 262 126, 206, 260, 336, 408a, 408b 128, 208, 252 129, 210, 254, 332, 402a, 402b, 454, support component conductive material, thin conductive material, plate-like branch support component, mineral gold layer support plate, first protruding area, central groove, second protruding area, trench Lower conductor upper conductor epoxide first trench sacrificial substrate copper layer seed layer first photoresist first photoresist pattern O: \ 89 \ 89662.DOC • 67-1242647 552, 664, 756 130, 272, 306 , 316 131, 212, 266 132a, 132b, 288 134, 264 136, 210, 265, 338, 410a, 410b, 460, 560 762 138, 148, 282, 378 140, 214 142, 222, 270, 414, 560, 570, 678, 762, 772, 146, 280, 258, 334b, 426, 274 276, 424, 476, 578, 682 278 280 282 300 310 320 322 324a 324b Dielectric plate conductive film alignment key second photoresist second photoresist pattern support plate third photoresist third photoresist pattern adhesive second trench fourth photoresist fourth photoresist pattern third Trench first sacrificial substrate second sacrificial substrate first probe second probe unit conductor beam member detection tip connection tip O: \ 89 \ 89662.DOC -68- 1242647 342 film 370a, 370b, 418, 472, 556, 656, 810, ceramic plate 820 362a, 362b, 370 dielectric 374a, 374b conductive layer 386a, 386b thin layer 404 slot 452, 558, 660, 662, 754 first layer 456, 562, 666, 764 first conductor 458, 564, 668, 766 First gold plating layer 474, 568, 760 Second layer 478, 572, 674, 774 Second conductor 480, 676, 776 Second gold plating layer 482, 578, 582 Fifth photoresist pattern 566 First guarantee Film 576, 670 Second protective film 652 Coating material 653 Cutting section 654 Sacrificial substrate block 667, 768 Protective film 758 Copper-plated structure 770 Third layer 774 Third conductor 821, 822 Terminal O: \ 89 \ 89662.DOC -69- 1242647 900 902 904, 955 907, 91, 967 908, 965 910, 975 912, 970 914, 924, 982 916, 980 918, 984 921, 986 922, 982 926 928 929 930, 974 932, 972 935 936 938 Beam member detection tip probe block fixing bolt first interface panel second interface panel probe holder anchor manipulator guide holding spring fixed component closed adhesive component lower closed adhesive component compression anchor guide film roll tape Encapsulation non-isotropic conductive film metal plate high elastic rubber O: \ 89 \ 89662.DOC -70-

Claims (1)

12426471242647 凜092132733號專利申請案 中文申請專利範圍替換本(94年4月) 拾、申如申請專利範圍: 1 · 種用以測試一平面板顯示器裝 一類板狀介電質; 平行配置之複數個導體;及 位於該介電質之上與下平面中之至少一、, 渠溝,俾以一預定配置 二:面上之第、 中。 予稷歎個導體於該介電賢 2. :申專利範圍第1項…測試-平面板顯示器裝置之 質積之第一與第二突出區位於-該介電 甘击— 中央槽位於該—平面上,·及 ,、中在㈣第一與第二突出區上之 於該中央槽。 弟木溝連結 如申請專利範圍第旧之用以測試 4± 貝不斋裝置之探 4· 十,,、中^供一次級探針以與該探針重疊;及 其中該等重疊探針之導體相互平行。 請專利範圍第2項之用以測試一平面板顯示器 ::置之棟針,其中該中央槽係利用一切方⑷一)製程形 5. 如申請專利範圍第!項之用以測 之 曲扳顯不态裝置 之奴針,其中該等導體具尖銳末端部。 =專利範圍第2項之用以測試-平面板顯示器裝置 其中在該等第—突出區上形成之該等第一渠溝 之間隔與在該等第二突出區上形成之該等第—渠溝之間 6. 1242647 隔相異。 8. 如:請專利範圍第【項之用以測試一平面板顯示器裝置 之奴針,其中該介電質係由一陶瓷材料製成。 如"專利範圍第w之用以測試一平面板顯示器裝置 之铋針,其中該探針進一步包括一堆疊於該介電質之$ 士:面或該下平面上之支撐組件,以固定該等導體於: "電質上之該等第一渠溝中。 9.如申請專利範圍第i項之用以測試一平面板顯 之探針, 其中該等第—渠溝係利用—微影製程及第— 刻製程形成。 /、弟一蝕 10·如申請專利範圍第9項之用以測試一平面板顯示 之探針, w双罝 其中歷經該第一蝕刻製程之各該等第—渠溝均具 金字塔或截面圓錐體外型;及 面 其中以該第二姓刻製程進一步姓刻具截面金字 面圓錐體外型之各該等第一渠溝直到一預定深产,以 -各該等渠溝之底部歷經一圓化(roundlng)’製:,广及 11. -種用以測試-平面板顯示器裝置之探針,包括以— 定間隔分離地位於並固定於—薄膜之預 元接觸組件,其中該薄膜具一預定 ^是數個單 頂疋尺寸,該等單元接 組件均包括-具桿料型之光束構件,及其__ 端係以整合方式位於該光束構件之一端上。 π d次 12. 如申請專利範圍第U項之用以 ^ 十面板顯示器裝置 O:\89\89662-940408.DOC 1242647 kt $結尖端位於該光束構件之另 13·如申請專利範圍第1? 而。 之探針,其中兮薄膜广用以測試一平面板顯示器裝置 成。 。 、係由-環氧化物或-聚對二甲苯製 14 一種用以測試-平面板顯示器裝置之探針,包括· 一犧牲基板; 利用诞衫製程與_蝕刻製程形成之第—渠 =導臈㈣程…預定間隔位於該犧牲基 敬上之s玄寺弟—渠溝中之導體; 一在該等導體上形成之第一介電質;及 利用u影製程與_蝕刻製程形成之第二渠 露該等導體於-該犧牲基板之下平面上;… " 一藉由將一介電質材料 第二介電質。 年弟一冓中而形成之 15.如申請專利範圍第14項之用以 之您# '千面板顯示器裝置 中該第-介電質係由-環氧化物製成。 •如申4專利範圍第14項之用以測試 之探針,其令該第二介 /、不為裝置 板。 貝係黏者一裱氧化物之陶瓷 17· 一種使用一單一犧牲基板形成之探針,包括 一類板狀介電質;及 複數個導體, 程形成,其令一 數個導體係以一 其中的渠溝係由—微影製程與—蝕刻製 傳導材料埋於該等渠溝中,纟中該等複 預定間隔位於該介電質之該等上與下平 O:\89\89662-940408.DOC 1242647 面上,及其中在該上平面上形成之該等導體與在該下平 面上形成之該等導體平行。 队如申請專利範圍第17項之使用一單一犧牲基板形成之探 針,其中该捸針進一步包括一堆疊於該介電質之該上平 面或該下平面上之類板狀支撐組件,以固定該等導體之 位置。 A如申請專利範圍仏項之使用—單—犧牲基板形成之探 針,其中該等複數個導體等長。 20. 如申請專利範圍第19項之使用一單一犧牲基板形成之探 針’其中在遠介電質之該上平面上形成之等長之該等導 體係以-預定距離向該介電質之―側偏移,藉以使得金 在該介電質之該下平面上形成之各該等導體相較,在該 電質之該上平面上形成之各該等導體均具進一步突出 之一端與進一步凹陷之另一端。 21. 如申請專利範圍第17項之使用一單一犧牲基板形成之探 針,其中该介電質之兩端均具步階差(step-difference)外 型,藉以使得在該介電質之該等上與下平面上形成之該 等導體自該介電質以等長向外突出。 泣如:請專利範圍第圍第17項之使用一單_犧牲基板形成 之奴針,其中该介電質之兩端均具傾斜外型,藉以使得 在该介電質之該等上與下平面上形成之該等導體自該介 電質以等長向外突出。 23.::申:專利範圍第17項之使用-單-犧牲基板形成之探 其中㈣介電質之該上平面上形成之該等導體均位 O:\89\89662-940408.DOC 1242647 於在該介電質之該下平面上形成之兩相鄰導體間。 24· 一種使用—單一犧牲基板形成之探針,包括: 一類板狀第一介電質; 堆豐之第二介電質,其在一該第一介電質之上部形 成一步階差; 乂 以一預定間隔配置之複數個導體,以穿透該 第二介電質;及 、 贫 藉由-預定電錢方法堆疊-傳導材料於各該等導體 之一平面上以形成一傳導層。 25·如申請專利範圍第24項之使用一單-犧牲基板形成之探 針’其中該探針進-步包括_堆疊於該第—介電質之: 上平面與該第二介電質之該下平面之至少一平面上: 撐組件。 又 26· -種使用一單一犧牲基板形成之探針,包括: 一藉由堆疊一陶瓷板於一環氧化物之上與下平面上 形成之介電質; 以一預定間隔於該介電質之該等上與下平面上形 複數個導體; ^ I 一藉由一預定電鍍方法堆疊於—各該等導體之平面 之傳導層;及 Λ 堆疊於該介電質之^玄$卜· Τ τ 1 包貝之3寺上與下平面上之支撐組件, 固定該等導體之位置。 27. —種使用一單一犧牲基板形成之探針,包括: 一類板狀介電質; O:\89\89662-940408.DOC 1242647 面上形成之 之一平面上 以一預定間隔於嗜介雷皙 A "包貝 <該等上與下平 複數個導體; 藉由預疋電鍍方法堆曼於各該等導體 之傳導層; 以 :疊:該介電質之該等上與下平面上之支擇組件, 固定該等導體之位置。 28· —種製造一用以測試一平面板 _ τ叫攸頌不斋裝置之探針 包括步驟: 一於一介電質之上與下平 , <主少 十面上形成第一 渠溝之第一渠溝形成步驟, 啤此以一預疋配置固定複激 個導體於該介電質上;及 -堆疊-支撐組件於該介電質之一上平面或—下平面 上之支樓組件形成步驟,藉此固定該等導體於該介電質 上之該等第一渠溝中。 、 29.如申請專利範圍第28項之製造_用以測試__ + ^^ 器裝置之探針之方法, 其中該方法進一步包括一於一該介電質之中央區上祀 成一中央槽之中央槽形成步驟,藉此於該介電質之兩俱 部上形成一第一突出區與一第二突出區,該等第一與第 一突出區具一預定面積;及 其中在該等第一與第二突出區上之該等第一渠溝連# 於該中央槽。 V ϋ 3〇·如申請專利範圍第28項之製造一用以測試一平面 一 杰裝置之探針之方法,其中堆疊一次級探針於該探詞 O:\89\89662-940408.DOC -6- I242647 31 、 σ久、、及操針之導體與該探針之導體平行。 W·如申請專利範圍第29j百+希』 „ . 4 員之衣义一用以測試一平面板顯示界 ^ 之方去,其中利用一切方製程形成該等第一 渠溝與該中央槽。 乐 32.==範圍第29項之製造一用以測試一平面板顯示 。置::針之方法,其中在該第一突出區上形成之該 寺弟一以之間隔與在該第二突出區上形成之該 渠溝之間隔相異。 33· 專利範圍第28項之製造一用以測試一平面 以:置之探針之方法,其中在該介電質之該上平面或該 、’面上$《n组件,俾固^該等導體於該 之該等第一渠溝中。 电貝 34.種製造-用以測試一平面板顯示器裝置之 包括: 电 一導體形成步驟’其係㈣—微影製程與—傳導膜形 成製程於-具—駭厚度之單—犧牲基板之—上平面斑 二下:面之至少一平面上形成具-預定厚度之光阻圖 木,藉以形成導體; —介電質形成步驟,其係利用-微影形成光阻圖案, 俾開啟—各該等導體之中央部,並於各該等導體之開啟 中央部上形成一介電質; 、,巨、朱溝形成步驟,其係利用—微影與一钱刻製程形成 渠溝’俾露出各該等導體之該下平面· -藉由埋入_支撐材料於該等渠溝中而形成一支擇組 O:\89\89662-940408.DOC 1242647 件之支撐組件形成步驟;及 移除该犧牲基板之完結步驟。 35. 如申請專利範圍第34項之製造—用以測試―平 _ 器裝置之探針之方法,其中在該導體形成步驟前,; 法進一步包括—於該犧牲基板之該上部上形成一種屏方 種層形成步驟。 9之 36. 1請專利範圍第則之製造一用以測試一平面板顯示 ™衣置之採針之方法,其中在該導體形成步驟中,同時 形成該等導體與對齊鍵,該等對齊鍵與該等導體間具二 特定距離。 〃 A :申請專利範圍第34項之製造-用以測試-平面板顯示 ^置之板針之方法,其中在該導體形成步驟中,在形 成該等導體前,於一該犧牲基板之上部上形成一種層。7 38·=請專利範圍第34項之製造一用以測試一平面板顯示 时衣置之抓針之方法,其中在該介電質形成步驟與該支 標、、且件$成步驟中,在形成該介電質與該支撐組件後, 研磨該介電質與該支撐組件。 39·種衣造一用以測試一平面板顯示器裝置之探針之方法, 包括: 利用诸影製程及第—與第二蝕刻製程形成具有歷 經:圓广製程之底部之第一渠溝之第一渠溝形成步驟; 導體开/成步驟’其係利用-微影製程開啟具該等第 —渠溝之中央部’接著將—傳導材料埋入開啟區中,藉 以形成導體; O:\89\89662-940408.DOC 1242647 一利用一微影製程與一介電膜形成製程於一各該等導 體之上部上形成一介電質之介電質形成步驟;及 一移除該犧牲基板之完結製程。 40.如申請專利範圍第39項之製造一用以測試一平面板顯示 器裝置之探針之方法,其中在該第一渠溝形成步驟後: 該導體形成步驟前,該方法進一步包括一形成一種 種層形成步驟。 3 礼如申請專利範圍第39項之製造一用以測試一平面板顯示 器裝置之探針之方法, W 其中歷經該第一蝕刻製程之各該等第一渠溝均具截 金子塔或截面圓錐體外型; 其中藉由該第二蝕刻製程進一步蝕刻具截面金字塔 截面圓錐體外型之各該等第一渠溝直到一預定深度且 各該等第一渠溝之底部均歷經一圓化製程。 且 42. -種製造一用以測試一平面板顯示器裝置之探針片之方 法,包括步驟: ^-犧牲基板上形成-第—保護„案,藉此界& 成複數個單元接觸組件之尖端之區域,· ; 利用該第-保護膜圖案為钱刻罩,藉由施行—钱刻制 程於該犧牲基板上形成渠溝; A 移除該第一保護膜圖案; 移除該第一保護膜處之該犧牲基板上形成—第二保 護膜圖案’藉此界定形成複數個單元接觸組件 件之區域,· A束構 O:\89\89662-940408.DOC -9- 1242647 藉由在形成該第二保護膜圖案處之該犧牲基板上形成 一金屬膜而形成該單元接觸組件之光束構件. 藉由移除該第二保護膜圖案而開啟該單元接觸組件之 該等光束構件; 以一預定尺寸將開啟該單元接觸給件之該等光束構件 處之該犧牲基板切方; 將一具一預定尺寸之薄膜置於切方之犧牲美凛 092132733 Patent Application Chinese Application Patent Scope Replacement (April, 1994) Pick up and apply for patent application scope: 1 · A type of plate dielectric used to test a flat panel display; a plurality of conductors arranged in parallel; And at least one of the channels located above and below the dielectric, and the trenches are arranged in a predetermined configuration two: the first and the middle of the surface. A conductor of the electric conductor in the Dixian 2. The scope of the patent application item 1 ... Test-the first and second protruding areas of the mass of the flat panel display device are located-the dielectric strike-the central slot is located- On the plane, and,, the central groove is on the first and second protruding regions of the cymbal. The Dimugou link is the oldest one in the scope of the patent application for testing the 4 ± Beibu Zhai device. The probe is designed to overlap with the probe, and the overlapping probes. The conductors are parallel to each other. Please use the second item of the patent scope to test a flat panel display :: set the needle, in which the central groove is used all the methods (1) process shape 5. If the patent scope of the first item is used to measure the curved display Slave pins for immobile devices, where the conductors have sharp ends. = Patent No. 2 for testing the flat-panel display device wherein the interval between the first trenches formed on the first protruding areas and the first trenches formed on the second protruding areas 6. 1242647 between the grooves are different. 8. For example, please ask for a slave pin for testing a flat panel display device according to item [of the patent], wherein the dielectric is made of a ceramic material. For example, the bismuth needle used to test a flat panel display device according to the "W" of the patent, wherein the probe further includes a supporting component stacked on the dielectric material: the surface or the lower surface to fix these The conductor is in: " these first trenches on the electric property. 9. If a probe for testing a flat panel display is provided in item i of the scope of patent application, wherein the -ditch is formed by the -lithographic process and the -engraving process. / 、 Yi Yi Eclipse 10. If the probe for testing a flat panel display is applied for item 9 in the scope of patent application, each of the first and second trenches that have undergone the first etching process has a pyramid or a cross-section cone. And the first canals in which the second surname engraving process is further engraved with a cross-section gold-shaped conical outer shape until a predetermined deep production, so that-the bottom of each canal goes through a roundlng (roundlng ) 'System :, broad and 11.-a probe for testing-flat panel display device, including a pre-element contact assembly separately located at a fixed interval and fixed to a film, wherein the film has a predetermined ^ is In several single-top cymbal sizes, these unit connectors include a beam member with a rod shape, and its __ end is integrated on one end of the beam member. π d times 12. If it is used for item U of the patent scope ^ Ten-panel display device O: \ 89 \ 89662-940408.DOC 1242647 kt $ The knot tip is located at the other of the beam member 13. If the scope of patent application is the first? and. The thin film is widely used for testing a flat panel display device. . Made of -epoxide or -para-xylene 14 A probe for testing a flat panel display device, including a sacrificial substrate; the first channel formed by the birthday shirt process and the etching process-channel = guide Process ... The conductors at predetermined intervals are located in the s-Xuansi brother-ditch on the sacrificial base; a first dielectric formed on these conductors; and a second formed using the U shadow process and the etching process These conductors are exposed on a plane below the sacrificial substrate; ...-by placing a dielectric material into a second dielectric. The younger brother was formed in the middle of time 15. If the scope of application for patent No. 14 is used in the "thousand-panel display device", the -dielectric is made of -epoxide. • If the probe of item 4 in the scope of patent No. 4 is used for testing, it makes the second interface, not the device board. A ceramic bonded with oxides 17. A probe formed using a single sacrificial substrate, including a type of plate-like dielectric; and a plurality of conductors formed by a process that causes a plurality of conductive systems to be one of The trenches are buried in these trenches by —lithographic process and —etching conductive materials. The predetermined intervals in the trenches are located above and below the dielectric. O: \ 89 \ 89662-940408.DOC The 1242647 plane, and the conductors formed on the upper plane, are parallel to the conductors formed on the lower plane. If the team applied for item 17 of the scope of patent application, a probe formed using a single sacrificial substrate, wherein the pin further includes a plate-like supporting component stacked on the upper plane or the lower plane of the dielectric to fix the The location of these conductors. AAs in the application of the scope of patent application (single)-single-sacrificial probe formed by the substrate, wherein the plurality of conductors are the same length. 20. For example, a probe formed using a single sacrificial substrate in the scope of patent application No. 19, wherein the conductive systems of the same length formed on the upper plane of the remote dielectric are directed to the dielectric by a predetermined distance. ―Side offset, so that each of the conductors formed on the lower plane of the dielectric has a further protruding end and further compared with each of the conductors formed on the upper plane of the dielectric. The other end of the depression. 21. For example, a probe formed by using a single sacrificial substrate in the scope of patent application No. 17, wherein both ends of the dielectric have a step-difference appearance, so that the dielectric The conductors formed on the upper and lower planes protrude outward from the dielectric with equal length. Weep like: Please use a single _ sacrificial needle formed by sacrificial substrate, in the 17th area of the patent, where both ends of the dielectric have a slanted shape, so that the upper and lower of the dielectric The conductors formed on the plane protrude outward from the dielectric material at an equal length. 23.::Application: Exploration of the use of single-sacrifice substrate formation in the scope of patent No. 17: The conductors formed on the upper plane of the plutonium dielectric are all positioned O: \ 89 \ 89662-940408.DOC 1242647 in Between two adjacent conductors formed on the lower plane of the dielectric. 24. A probe formed using a single sacrificial substrate, comprising: a type of plate-shaped first dielectric; a second dielectric of a heap, which forms a step difference on top of the first dielectric; 乂A plurality of conductors arranged at a predetermined interval to penetrate the second dielectric; and, a conductive material is stacked on a plane of each of the conductors by a predetermined electrical method to form a conductive layer. 25. If a single-sacrificial substrate-formed probe is used for item 24 of the scope of patent application, wherein the probe further includes _ stacking on the first dielectric: the upper plane and the second dielectric On at least one of the lower planes: a brace assembly. 26. A probe formed using a single sacrificial substrate includes: a dielectric formed by stacking a ceramic plate above and below an epoxide; and a predetermined interval between the dielectric A plurality of conductors formed on the upper and lower planes; ^ I-a conductive layer stacked on a plane of each of these conductors by a predetermined plating method; and ^ x $ τ stacked on the dielectric 1 The supporting components on the upper and lower planes of Baobei 3 Temple fix the positions of these conductors. 27. A probe formed using a single sacrificial substrate, including: a type of plate-like dielectric; O: \ 89 \ 89662-940408.DOC 1242647 on a plane formed on a plane at a predetermined interval on a mesophilic mine A " Baube " These upper and lower flat conductors; stacked on the conductive layers of each of these conductors by a pre-plating method; stack: the upper and lower planes of the dielectric Optional components to fix the position of these conductors. 28 · —A method of manufacturing a probe for testing a flat plate _ τ called Euson ’s fasting device includes the steps: one above and below one dielectric, < A trench formation step, in which a complex excitation conductor is fixed on the dielectric in a pre-arranged configuration; and-a stack-support assembly is formed on an upper plane of the dielectric or a branch assembly on a lower plane. Step to fix the conductors in the first trenches on the dielectric. 29. The method of manufacturing a probe for testing __ + ^^ device as claimed in item 28 of the scope of patent application, wherein the method further includes sacrifice a central groove on a central area of the dielectric. A central groove forming step, thereby forming a first protruding area and a second protruding area on the dielectric portion of the dielectric, the first and first protruding areas having a predetermined area; and One is connected to the first grooves on the second protruding area in the central groove. V ϋ 30. The method of manufacturing a probe for testing a plane and a device as described in item 28 of the scope of patent application, wherein a primary probe is stacked on the probe O: \ 89 \ 89662-940408.DOC- 6- I242647 31, σ Jiu, and the conductor of the needle are parallel to the conductor of the probe. W · If the scope of application for the patent is 29j hundred + Greek "....... 4 members of Yi Yiyi is used to test a flat panel display world ^, where the first channel and the central groove are formed by all-side processes. 乐32. == Manufacturing of item 29 of the range is used to test a flat panel display. Setting: The needle method, wherein the temples formed on the first protruding area are spaced apart from each other on the second protruding area. The gaps formed between the trenches are different. 33. The method of manufacturing a flat surface to test a flat surface in the scope of the 28th patent: a method of placing a probe, in which the upper surface of the dielectric or the surface The components are fixed in the first trenches. 34. Kinds of manufacturing-used to test a flat panel display device includes: Steps to form a conductor-its system-micro The shadowing process and the conductive film forming process are made of a single sheet with a thickness of sacrifice, a sacrificial substrate, and two upper plane spots: a photoresist pattern with a predetermined thickness is formed on at least one plane of the surface to form a conductor; Electric mass formation step, which uses-lithography to form a photoresist pattern , 俾 Open—the central part of each of these conductors, and a dielectric substance is formed on the open central part of each of these conductors; Steps for forming giant and Zhugou, which are formed using the lithography and a money carving process The trench 'reveals the lower plane of each of these conductors.-A support group of O: \ 89 \ 89662-940408.DOC 1242647 is formed by embedding _ support material in these trenches. And the final step of removing the sacrificial substrate. 35. For example, a method for manufacturing a probe for testing a leveler device according to item 34 of the scope of patent application, wherein before the conductor forming step, the method further includes: -Forming a screen seed layer forming step on the upper portion of the sacrificial substrate. 9 of 36.1 claims a method of manufacturing a needle for testing a flat panel display ™ garment, wherein the conductor In the forming step, the conductors and the alignment keys are formed at the same time, and there are two specific distances between the alignment keys and the conductors. 〃 A: Manufacturing of the 34th area of the patent application-for testing-flat panel display Needle method where In the conductor forming step, a layer is formed on an upper portion of a sacrificial substrate before the conductors are formed. 7 38 · = Please make a 34th item of the patent scope for testing a grip on a flat panel display The method of needle, wherein in the step of forming the dielectric and the support, and the step of forming the support, after the dielectric and the supporting component are formed, the dielectric and the supporting component are ground. A method for fabricating a probe for testing a flat panel display device includes: forming first trenches with first trenches at the bottom of a round-broad process using the shadow process and the first and second etching processes; Steps; Conductor opening / forming step 'It is the opening of the central part of the -ditch with a -lithographic process', and then-the conductive material is buried in the opening area to form a conductor; O: \ 89 \ 89662-940408 .DOC 1242647-a dielectric forming step of forming a dielectric on an upper portion of each of the conductors using a lithography process and a dielectric film forming process; and a finishing process of removing the sacrificial substrate. 40. The method of manufacturing a probe for testing a flat panel display device according to item 39 of the patent application scope, wherein after the first trench forming step: before the conductor forming step, the method further includes forming a kind of Layer formation step. 3 Li Ru, a method of manufacturing a probe for testing a flat panel display device under item 39 of the scope of patent application, where each of the first trenches that have undergone the first etching process has a gold-cutting tower or a cross-section cone Wherein each of the first trenches having a cross-section pyramidal cross-section outer shape is further etched by the second etching process to a predetermined depth and a bottom of each of the first trenches undergoes a rounding process. And 42.-A method of manufacturing a probe sheet for testing a flat panel display device, comprising the steps of: ^-forming on a sacrificial substrate-the first protection case, by which the unit &Area; using the first-protective film pattern as a money engraving mask to form a trench on the sacrificial substrate by performing a money-engraving process; A removing the first protective film pattern; removing the first protective film A second protective film pattern is formed on the sacrificial substrate to thereby define a region where a plurality of unit contact components are formed. A beam structure O: \ 89 \ 89662-940408.DOC -9- 1242647 A metal film is formed on the sacrificial substrate at the second protective film pattern to form a beam member of the unit contact assembly. The beam members of the unit contact assembly are turned on by removing the second protective film pattern; The size will open the sacrificial substrate tangent to the beam contact members of the unit; the sacrificial beauty of the tangent will be placed on a film with a predetermined size. 附接與固定該單元接觸組件之該等光束構件於該薄膜: 該下部上;及 时藉由移除附接與固㈣薄膜處之該犧牲基板而開啟該 單元接觸組件之該等尖端。 43. 如申請專利範圍第42項之製造一用以測試一平面板顯示 器裝置之探針片之方法,其中該第—與該第二保護膜圖 案之形成係由: 塗佈光阻於該犧牲基板上之步驟;及 一將該光阻曝光與顯影之步驟。Attach and fix the beam contact members of the unit contact assembly on the film: on the lower portion; and open the tips of the unit contact assembly by removing the sacrificial substrate at the attachment and fixation film. 43. For example, a method for manufacturing a probe sheet for testing a flat panel display device according to item 42 of the patent application range, wherein the formation of the first and the second protective film patterns is: coating a photoresist on the sacrificial substrate The above steps; and a step of exposing and developing the photoresist. 44. 如申請專利範圍第42項之製造一用以測試一平面板释干 -裝置之探針片之方法,其中該薄膜係由一環 一聚對二甲笨製成。 45· -種使用-單—犧牲基板製造一探針之方法,包括: =利用—微影與-姓刻製程於該單一犧牲基板之上與 下平面上形成第-渠溝之第-渠溝形成步驟,其中該單 一犧牲基板具—預定厚度; 一藉由埋入—傳導材料於該等第一㈣中而形成導體 O:\89\89662-940408.DOC -10- 1242647 之導體形成步驟; ^利用一微影與一蝕刻製程於該等導體之下部上形成 第二渠溝之第二渠溝形成步驟,· # —藉由埋入一傳導材料於該等第二渠溝中而形成介電 質之介電質形成步驟; t 一於形成該介電質處之該犧牲基板之該等上與下平面 之至少一平面上形成一支撐組件之支撐組件形成步驟,· 一移除該犧牲基板之完結步驟。 46. 47. 48. 49. 如申請專利範圍第4 5項之使用—單—犧牲基板製造一探 針之方法,其中該犧牲基板係一矽晶圓。 如申請專利範圍第45項之使用-單—犠牲基板製造一探 =之方法,其t藉由施加—環氧化物於該等渠溝中,接 著在固化5玄裱氧化物前插入與附接陶瓷板於該等第一渠 溝中而形成該介電質’其中該等陶竟板係以—適於被插 入該等渠溝中之尺寸預先製備。 如申請專利範圍第45項之使用—單—犧牲基板製造一探 針之方法’其中藉由插入陶瓷板於該等渠溝中,接著施 加契附接%氧化物於該等渠溝與該等陶莞板間形成之 間隙中而形成該介電質,其中該等陶瓷板係以一適於被 插入該等渠溝中之尺寸預先製備。 如申請專利範圍第45項之使用—單—犧牲基板製造一探 針之方法’其中在該導體形成步驟中,藉由在該犧牲基 板上形成-種層,接著施行—電解f電鍍製程而形成該 O:\89\89662-940408.DOC -11 - 1242647 等導體。 50·如申請專利範圍第45項之使用一單一犠牲基板製造一探 針之方法,其中該方法進一步包括一傳導層形成步驟, 其係利用一電鍍製程而堆疊一傳導材料於該等導體之上 平面上而形成一傳導層。 51· —種使用一單一犠牲基板製造一探針之方法,包括·· 一於該單一犧牲基板上形成一第一保護膜之第一保護 膜形成步驟,其中該單一犧牲基板具一預定厚度,其中 利用該第一保護膜圖案形成導體; 一藉由埋入一傳導材料於該第一保護膜圖案中而形成 上導體之上導體形成步驟; 於形成该等導體處之該犧牲基板上形成一第二保護 膜之第一保護膜形成步驟,其中利用該第二保護膜圖案 形成一支撐組件; 一於該第二保護膜圖案中形成一上支撐組件之上支撐 形成步驟; 一使用一微影製程與一蝕刻製程以露出該上導體,以 於該犠牲基板之下平面上形成渠溝之渠溝形成步驟; 一藉由埋入一介電質材料於該等渠溝中而形成一介電 質之介電質形成步驟;及 一移除該犧牲基板之步驟。 52.如申請專利範圍第51項之使用—單一犧牲基板製造一探 針之方法, /、中在私除σ亥犧牲基板之步驟前,該方法進一步包括 O:\89\89662-940408.DOC -12- 1242647 其係藉由在該介電質形成步驟中形44. For example, a method for manufacturing a probe sheet for testing a flat-plate release-drying device according to item 42 of the patent application range, wherein the film is made of a ring, a polymer, and a pair of dimethylbenzene. 45 · A method of manufacturing a probe using a single-sacrifice substrate, including: = using -lithography and-last name engraving process to form a first-ditch on the single-sacrifice substrate and on a lower plane. A forming step, wherein the single sacrificial substrate has a predetermined thickness; a conductor forming step of forming a conductor O: \ 89 \ 89662-940408.DOC -10- 1242647 by embedding-conducting material in the first ridges; ^ Using a lithography and an etching process to form a second trench on the lower part of the conductors, the second trench formation step is performed by burying a conductive material in the second trenches. A dielectric forming step of the dielectric; t a supporting component forming step of forming a supporting component on at least one of the upper and lower planes of the sacrificial substrate at which the dielectric is formed, · removing the sacrificial The end step of the substrate. 46. 47. 48. 49. According to the application of the scope of patent application No. 45-single-sacrificial substrate manufacturing method of a probe, wherein the sacrificial substrate is a silicon wafer. For example, in the application of the scope of patent application No. 45-a method of manufacturing a single substrate, the method is to apply-epoxy in these trenches, and then insert and attach before curing Ceramic plates are formed in the first trenches to form the dielectric, wherein the ceramic panels are pre-prepared at a size suitable for being inserted into the trenches. For example, the use of item 45 in the scope of patent application—single-sacrifice substrate manufacturing method of a probe ', in which ceramic plates are inserted into the trenches, and then a percentage of oxide is attached to the trenches and the trenches. The dielectric is formed in a gap formed between the ceramic plates, wherein the ceramic plates are prepared in advance at a size suitable for being inserted into the trenches. For example, the use of item 45 in the scope of patent application-a single-sacrificial substrate manufacturing method of a probe 'wherein in the conductor forming step, a seed layer is formed on the sacrificial substrate, and then an electrolytic-plating process is performed. The O: \ 89 \ 89662-940408.DOC -11-1242647 and other conductors. 50. The method of manufacturing a probe using a single substrate as described in item 45 of the scope of patent application, wherein the method further includes a step of forming a conductive layer, which uses a plating process to stack a conductive material on the conductors A conductive layer is formed on the plane. 51 · A method for manufacturing a probe using a single substrate, including a first protective film forming step of forming a first protective film on the single sacrificial substrate, wherein the single sacrificial substrate has a predetermined thickness, Wherein, the first protective film pattern is used to form a conductor; a step of forming a conductor on the upper conductor by burying a conductive material in the first protective film pattern; and forming a conductor on the sacrificial substrate where the conductors are formed. A first protective film forming step of a second protective film, wherein a support component is formed by using the second protective film pattern; a support forming step of forming an upper support component in the second protective film pattern; using a lithography And an etching process to expose the upper conductor to form a trench forming step on a plane below the substrate; a trench is formed by embedding a dielectric material in the trenches A step of forming a dielectric; and a step of removing the sacrificial substrate. 52. If the use of item 51 in the scope of the patent application-a method for manufacturing a probe with a single sacrificial substrate, /, before the step of sacrifice the sacrifice substrate, the method further includes O: \ 89 \ 89662-940408.DOC -12- 1242647 It is formed by forming 一下導體形成步驟,其係 成之該介電質上形成一第 導材料於該第三保譆膜圖 '’其中藉由施加一環氧化物於該等渠溝中,接 著在忒%氧化物固化前插入與附接陶瓷板於該等第一渠 溝中而形成该介電質,其中該等陶瓷板係以一適於被插 入該等渠溝中之尺寸預先製備。 55·如申請專利範圍第51項之使用一單一犠牲基板製造一探 針之方法,其中藉由插入陶瓷板於該等渠溝中,接著施 加與附接一環氧化物於該等渠溝與該等陶瓷板間形成之 間隙中而形成該介電質,其中該等陶瓷板係以一適於被 插入該等渠溝中之尺寸預先製備。 56_如申請專利範圍第51項之使用一單一犠牲基板製造一探 針之方法,其中在該導體形成步驟中,藉由在該犧牲基 板上形成一種層,接著施行一電解質電鍍製程而形成該 等導體。 57·如申請專利範圍第5 1項之使用一單一犠牲基板製造一探 針之方法,其中該方法進一步包括一傳導層形成步驟, O:\89\89662-940408.DOC -13 - 1242647 其係利用一電鍍製程而堆疊一傳導材料於該等導體之上 平面上而形成一傳導層。 58·如申明專利範圍第51項之使用—單-犠牲基板製造一探 針之方法’其中在該支撐組件形成步驟中,利用一微影 =與-蝕刻製程形成渠溝,接著施加一支撐材料於: 等渠溝中’藉此形成該支撐組件。 59. -種使用-單—犠牲基板製造—探針之方法,包括: 一於一該單—犧牲基板之預定部上形成第一渠溝之第The next step of conductor formation is to form a conductive material on the dielectric to form the third film. The epoxide is applied in the trenches, and then cured in 忒% oxide. The dielectric is formed by inserting and attaching ceramic plates in the first trenches, wherein the ceramic plates are prepared in advance in a size suitable for being inserted into the trenches. 55. The method for manufacturing a probe using a single substrate as described in item 51 of the scope of the patent application, wherein a ceramic plate is inserted into the trenches, and then an epoxy is applied and attached to the trenches and the trenches. The dielectric is formed in a gap formed between ceramic plates, wherein the ceramic plates are prepared in advance at a size suitable for being inserted into the trenches. 56_ The method of manufacturing a probe using a single substrate as described in item 51 of the scope of patent application, wherein in the conductor forming step, the layer is formed by forming a layer on the sacrificial substrate and then performing an electrolytic plating process And so on. 57. The method for manufacturing a probe using a single substrate as described in item 51 of the scope of patent application, wherein the method further includes a step of forming a conductive layer, O: \ 89 \ 89662-940408.DOC -13-1242647 A conductive material is stacked on a plane above the conductors by a plating process to form a conductive layer. 58. The use of item 51 of the stated patent scope—method for manufacturing a probe with a single-plate substrate ', wherein in the supporting component formation step, a lithography = and-etching process is used to form a trench, and then a supporting material is applied In: Waiting in the trench to form the support assembly. 59. A method for using a single-single-substrate substrate manufacturing-probe, comprising: forming a first trench on a predetermined portion of the single-sacrifice substrate; :渠溝形成步驟,其中該單—犧牲基板係由—預定材料 製成,並歷經一抛光製程以具—預定厚度,纟中利用該 寺ίκ溝形成一'介電質; 一藉由埋入一介電材料於該等第-渠ί冓中而形成該介 電質之介電質形成步驟;A trench formation step, in which the single-sacrificial substrate is made of a predetermined material, and undergoes a polishing process to have a predetermined thickness, and the temple uses the temple to form a dielectric; A dielectric material forming step in the first channel to form the dielectric material; 一導體形成步驟,其係藉由在形成該介電處之該犧牲 基板之上與下平面上形成—保護膜圖案而形成導體,接 著埋入一傳導材料於該保護膜圖案;及 移除该犧牲基板之完結步驟。 士申„月專利犯圍第59項之使用—單—犠牲基板製造-針之方法’其中該犧牲基板係一石夕晶圓。 61·如申請專利範圍第59項之使用_單一犠牲基板製造-’’十之方法其中利用一乾蝕刻製程形成該等第一杀淺 62·如申請專利範圍第59項之使用-單-犠牲基板製t 針之方法’其中利用—切方製程形成該等第一渠溝。 63.如申請專利範圍第,之使用_單一犧牲基板製造- O:\89\89662-940408.DOC -14- 1242647 針之方法,其中藉由施加一環氧化物於該等第一渠溝 二丄t著在固化該環氧化物前插入與附接陶瓷板於該等 弟-渠溝中而形成該介電質,其中該等陶瓷板係以一適 於被插入該等第—渠溝中之尺寸預先製備。 64. 如申請專利範圍第59項之使用一單一犧牲基板製造一探 針之方法,其中藉由插入陶究板於該等第一渠溝中,接 从 /、附接%氧化物於該等第一渠溝與該等陶瓷板 門开/成之間隙中而形成該介電質’其中該等陶瓷板係以 一適於被插入該等第一渠溝中之尺寸預先 65. 如申請專利範圍第59項之使用一單—犧牲基板製造一探 針之方法,其中在該導體形成步驟中,藉由在該犧牲基 板上形成—種層,接著施行—電解質電錢製程而形成該 等導體。 66. 如申請專利範圍第59項之使用一單一犠牲基板製造一探 二之方法,其中該方法進一步包括—於該犧牲基板之該 等上_下平面之一平面上形成一支撐組件之支撐組件形 成步驟。 67. 68. 如申請專利範圍第66項之使用_單_犠牲基板製造一探 針之方法,其巾在該支撐組件形成步驟中,施加一環氧 化物,接著附接一陶瓷板於一該環氧化物之上平面上。 如申請專利範圍第66項之使用-單_犠牲基板製造一探 針之方法,其中在該支撐組件形成步驟中,利用一微影 製程形成渠溝,接著施加一支撐材料於該等渠溝中,藉 此形成該支撐組件。 O:\89\89662-940408.DOC -15- 1242647 69·如申請專利範圍第59項之使用一單一犧牲基板製造一探 針之方法,其中該方法進一步包括一傳導層形成步驟, 其係利用一電鍍製程而堆疊一傳導材料於該等導體之該 等上平面上而形成一傳導層。 70· 種使用一單一犠牲基板製造一探針之方法,包括: 於單一犧牲基板之一上平面之一預定區上形成具 預定深度之渠溝之渠溝形成步驟; 一於形成渠溝處之該犧牲基板上形成一第一保護膜圖 案之第一保護膜圖案形成步驟,藉此開啟該等渠溝; — 埋入渠溝埋入材料於該第一保護膜圖案開啟之該 々等渠溝中之渠溝埋入步驟,其中藉由一蝕刻製程移除該 專渠溝埋入材料; #利用y微影製程於該犧牲基板之上與下+面上形成 =第二保護膜之第二保護膜圖案形成步驟,其中利用該 第二保護膜圖案形成導體; ^ 一於該第二保護膜圖案所界定之特定位置處形成導體 之導體形成步驟; 命綠 一於形成該等導濟# ♦體處之该犧牲基板之該等上與下平3 上形成一第三保謨膜岡安 # 又胰圖案之弟三保護膜圖案形成步驟, 其中利用該第三俾喝 一保〜馭圖案形成一支撐組件; 於5亥第二保護膜圖荦 撐έ且#夕… 口茶所界疋之特疋位置處形成一戈 棕件之支撐組件形成步驟;及 一移除部分為該梁、、善 移木溝埋入材料分隔之犧牲基板並接著 亥木溝埋入材料之完結步驟。 O:\89\89662-940408.DOC -16- 1242647 71 •如申請專利範圍第70項之使用一單一犠牲基板製造一探 針之方法,在形成該等導體前,該方法進一步包括一利 :一研磨製程移除在該犧牲基板之該上平面上形成之該 μ保‘膜圖案以及自該犧牲基板向上突出之該渠溝埋入 材料之平坦化步驟。 •如申凊專利範圍第70項之使用一單一犠牲基板製造一 λ r ^ 之方去,其中在形成第二保護膜圖案形成步驟中之該 犧牲基板之該下平面上之該等導體前,該方法進一步包 括一利用一研磨製程移除該犧牲基板以露出該介電質之 平坦化步驟。 ' 73·如中請專利範圍第7G項之使H犠牲基板製造-探 方法其中该犧牲基板係由一陶兗材料製成。 74.如申請專利範圍第70項之使用一單-犠牲基板製造-探 針之方法,其中以一切方製程形成該等渠溝。 75·如申請專利範圍㈣項之使用-單-犠牲基板製造-探 方去其中以一電解質電鑛製程形成該渠溝埋入材 料。 76·如中請專利範圍第7G項之使H犠牲基板製造-探 針之方法,其中該導體形成步驟包括一種層形成步驟, 其係在形成該等導體前,於該犧牲基板之該等上與下平 面上形成種層。 士申叫專利範圍第70項之使用一單一犠牲基板製造—探 針之方法,其中該方法進—步包括—利用—傳導材料堆 疊傳導層於各該等導體之上平面上之傳導層形成步驟。 O:\89\89662-940408.DOC 1242647 78. 79. 如申ό青專利範圊 圍弟77項之使用一單一犠牲基板製造一探 針之方法,复Φ户—& , ▲ ”在遠傳導層形成步驟中,以一濺鍍製成 I °亥傳導材料於該等導體之上平面上。 二申請專利範圍第7G項之使用—單―犠牲基板製造一探 針之方法,苴中力吟 甲在该完結步驟中,以一濕蝕刻製程選擇 性移除該渠溝埋入材料。 O:\89\89662-940408.DOCA conductor forming step of forming a conductor by forming a protective film pattern on and above the sacrificial substrate where the dielectric is formed, and then burying a conductive material in the protective film pattern; and removing the The final step of sacrificing the substrate. Shi Shen „The use of item 59 of the monthly patent offense—single-sacrifice substrate manufacturing method-needle method ', where the sacrificial substrate is a stone wafer. 61 · If the application of the scope of patent application No. 59_single-sacrifice substrate manufacturing- '' Ten methods of which use a dry etching process to form these first killings 62. Such as the application of the scope of the patent application No. 59 use-single-犠 animal substrate t-pin method 'where the use-tangent process to form the first 63. If the scope of the patent application is the first, the use of _ single sacrificial substrate manufacturing-O: \ 89 \ 89662-940408.DOC -14-1242647 needle method, wherein an epoxy is applied to the first channels The dielectric is formed by inserting and attaching ceramic plates in the trenches before curing the epoxide, wherein the ceramic plates are adapted to be inserted into the first trenches. The dimensions in the trenches are prepared in advance. 64. The method of manufacturing a probe using a single sacrificial substrate as described in item 59 of the patent application scope, wherein by inserting ceramic plates into the first trenches, connecting / attaching Connect% oxide to the first trenches and the ceramic plates The dielectric material is formed in the open / completed gap, wherein the ceramic plates are 65 in advance with a size suitable for being inserted into the first trenches. For example, the use of a single item in the scope of the patent application 59-sacrifice A method for manufacturing a probe on a substrate, wherein in the conductor forming step, these conductors are formed by forming a seed layer on the sacrificial substrate and then performing an electrolyte electrolyte process. 67. 68. Such an application is a method of manufacturing a two-piece method using a single sacrifice substrate, wherein the method further includes—a support component forming step of forming a support component on one of the upper and lower planes of the sacrificial substrate. A method for manufacturing a probe using the patent scope item 66_single substrate. In the step of forming the supporting assembly, an epoxide is applied, and then a ceramic plate is attached to a plane above the epoxide. For example, a method for manufacturing a probe using the single-strip substrate on the basis of the scope of patent application No. 66, wherein in the supporting component formation step, a lithography process is used to form a trench, and then applied A support material is added to the trenches to form the support assembly. O: \ 89 \ 89662-940408.DOC -15-1242647 69 · As a result of using a single sacrificial substrate to manufacture a patent, the scope of the application is 59. Needle method, wherein the method further includes a conductive layer forming step, which uses a plating process to stack a conductive material on the upper planes of the conductors to form a conductive layer. 70. A method using a single substrate A method for manufacturing a probe includes: a trench forming step of forming a trench with a predetermined depth on a predetermined area on a flat surface of a single sacrificial substrate; and forming a first on the sacrificial substrate where the trench is formed The first protective film pattern forming step of the protective film pattern, thereby opening the trenches;-burying the trench, burying the material in the trench embedding step in the first trench, where the first protective film pattern is opened, where The etch trench embedded material is removed by an etching process; # the second protective film pattern forming step of forming a second protective film on the sacrificial substrate and on the + surface using the y lithography process, where The second protective film pattern forms a conductor; ^ a conductor forming step of forming a conductor at a specific position defined by the second protective film pattern; Ming Lu Yi in forming the sacrifice substrate at the body Wait for the upper and lower flat 3 to form a third Baomo film Gang'an # Another step of the protective film pattern forming step of the younger one of the pancreas pattern, in which the third shovel is used to form a supporting component; a second protective component is formed at the 5th protection; Membrane picture 荦 架着 ## ... A step of forming a support assembly forming a brown piece at a special position on the boundary of the mouth tea; and a sacrifice where the removed part is separated by the beam and the well-moving trench The substrate and the completion step of the burying material in the Haimugou. O: \ 89 \ 89662-940408.DOC -16- 1242647 71 • If the method for manufacturing a probe using a single substrate is applied to item 70 of the scope of patent application, before forming the conductors, the method further includes an advantage: A polishing process removes the planarization step of the μ-protection film pattern formed on the upper plane of the sacrificial substrate and the trench buried material protruding upward from the sacrificial substrate. • The method of manufacturing a λ r ^ using a single substrate as claimed in item 70 of the patent scope, wherein before the conductors on the lower plane of the sacrificial substrate in the step of forming the second protective film pattern, The method further includes a planarizing step of removing the sacrificial substrate by a polishing process to expose the dielectric. '73. Please refer to the patent scope of 7G for the manufacturing method of the H-substrate substrate, wherein the sacrificial substrate is made of a ceramic material. 74. A method of manufacturing a single-probe substrate-probe using the scope of patent application item 70, wherein these channels are formed by an all-inclusive process. 75. If the use of the scope of the patent application for item 1-single-battery substrate manufacturing-exploration, go to one of them to form the trench and embed the material by an electrolytic power ore process. 76. The method of making a H.sub.substrate substrate-probe according to item 7G of the patent, wherein the conductor forming step includes a layer forming step, which is performed on the sacrificial substrate before forming the conductors. A seed layer is formed on the lower plane. Shi Shen called the 70th method of manufacturing a probe using a single substrate in the patent scope, wherein the method further includes the step of forming a conductive layer on a plane above each of the conductors by using a conductive material to stack the conductive layers. . O: \ 89 \ 89662-940408.DOC 1242647 78. 79. The method of manufacturing a probe using a single substrate as described in the 77th item of the patent application of Fan Qingwei, is to rename a household— & In the step of forming the conductive layer, an I ° conductive material is made on the planes of these conductors by a sputtering method. 2. Use of the 7G of the patent application scope—single-slab substrate manufacturing method of a probe Yinjia selectively removes the trench buried material by a wet etching process in this finishing step. O: \ 89 \ 89662-940408.DOC
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KR10-2002-0072990A KR100474420B1 (en) 2002-11-22 2002-11-22 Probe sheet for testing flat pannel display, method thereby, probe assembly having it
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KR10-2003-0007654A KR100517729B1 (en) 2003-02-07 2003-02-07 Probe for manufacturing probe for testing flat pannel display, probe thereby, probe assembly having its
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