KR101133407B1 - A method of manufacturing for a probe and a probe device - Google Patents

Abstract

The present invention provides a method for etching a region in which a first probe and a second probe of a multilayer structure having a fine pitch are formed to be in contact with a minute pitch terminal formed in a semiconductor device to probe a semiconductor device or an LCD panel. The method may include: generating a first probe and a second probe having a multilayer structure by plating the etched region, and a probe coupling step of coupling a plurality of probes including the first probe and the second probe to a circuit board. The present invention provides a method of manufacturing a probe and a probe device, and since the wafer is etched to generate a first probe and a second probe of a multilayer structure, there is an effect of finely adjusting a plurality of probe pitches including the first probe and the second probe. .

Description

Probe and probe device manufacturing method {A METHOD OF MANUFACTURING FOR A PROBE AND A PROBE DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a probe device for selecting a defective semiconductor or defective LCD panel device by contacting a terminal of a semiconductor device or a flat panel display (LCD).

BACKGROUND Semiconductor devices incorporating circuit elements such as integrated circuits (ICs) and large scale integrated circuits (LSIs) using wafers go through various and complex manufacturing processes depending on the type of device or the object in which the device is used. In particular, in the manufacture of flat panel display devices, a light guide plate, a polarizing plate, a driver, and a backlight unit are assembled with an LCD panel, and these devices undergo an inspection process to determine whether a product is defective. A device for inspecting such a semiconductor device or an LCD panel, the probe device such as a probe card for selecting a defective semiconductor device or a probe card for selecting a defective semiconductor device by applying an electrical signal by contacting the probe to the wafer or LCD panel Is being used.

However, a conventional probe device such as a probe card or a probe unit has a problem of being applied to a semiconductor or LCD panel device which is manufactured by individual manual integration and highly integrated.

In order to solve this problem, a technology for a probe card that minimizes defect rate and enables rapid response in miniaturization due to high integration of semiconductor chips is disclosed in Korean Patent Application Publication No. 10-2009-0128186 (Invention: Probe of Probe Card). Needle structure and a method of manufacturing the same).

However, since the above-mentioned technology simply forms a photoresist layer by applying photoresist and then stacks metal according to a mask pattern to generate a probe, the probe having a fine pitch to be in contact with a fine pitch terminal formed in a semiconductor device or an LCD panel. There is a problem that can not manufacture.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object thereof is to provide a probe and a probe device for contacting a terminal of a minute pitch formed on a semiconductor device or an LCD panel to probe each device.

In order to achieve the above object, a method of manufacturing a probe device according to the present invention includes a probe region etching step of etching a region on which a first probe and a second probe having a fine pitch are to be formed on a wafer; Generating a first probe and a second probe by plating the etched region; A probe coupling step of coupling the first probe and the second probe with a circuit board; And a wafer removal step of removing the one wafer while leaving the first probe and the second probe coupled through the probe coupling step. It includes, The first probe and the second probe is characterized in that it consists of a multilayer structure.

The plurality of first and second probes of the multilayer structure generated according to the probe generation step may be generated on the wafer.

In addition, the non-forming region etching step of etching a region other than the region where the first probe and the second probe of the multilayer structure is to be formed; It characterized in that it further comprises.

The etching of the probe region may include etching the upper surface of the wafer, and the etching of the non-forming region, etching the lower surface of the wafer.

The etching of the probe region may include: a first etching process of etching a portion where a tip (TIP) of the first probe and the second probe of the multilayer structure is to be formed; A second etching process of additionally etching a portion where a tip (TIP) of the first probe and the second probe etched by the first etching process is to be formed; And a third etching process of etching portions of the body of the first probe and the second probe to be formed. Characterized in that it comprises a.

In the second etching process, the wafer is etched using potassium hydroxide according to the single crystal structure of the wafer.

In addition, the third etching process is characterized in that the wafer is etched using an Inductive Coupled Plasma (ICP) Etcher or Deep Silicon Etcher.

In addition, the first probe and the second probe of the multilayer structure generated according to the probe generation step is characterized in that the first projection and the second projection for coupling with the circuit board is formed, respectively.

The generating of the probe may include depositing a conductive thin film on a region where the first probe and the second probe of the multilayer structure are to be formed; Plating a conductive material on a region where the conductive thin film is deposited; Characterized in that it comprises a.

In addition, the conductive thin film is characterized by consisting of titanium (Ti) and copper (Cu).

The conductive material is made of at least one of nickel (Ni), nickel cobalt (NiCo), platinum (Pt), tungsten (W) and rhodium (Rh).

In addition, a probe grinding step of grinding the first probe and the second probe of the multilayer structure to maintain the flatness of the first and second probes of the multilayer structure generated by the probe generation step; It characterized in that it further comprises.

The first probe, the second probe, and the circuit board of the multilayer structure coupled according to the probe bonding step may be coupled by a flip chip bonder.

In addition, the probe bonding step is a process of applying a photoresist to the circuit board; Patterning the applied photoresist; And generating a bump by plating a conductive material on the circuit board according to the pattern. It includes, the probe is characterized in that coupled to the bump.

The conductive material is made of at least one of nickel (Ni), nickel cobalt (NiCo), platinum (Pt), tungsten (W) and rhodium (Rh).

In addition, the tip portion of the first probe and the second probe of the multilayer structure is characterized in that formed at the same time.

Meanwhile, in order to achieve the above object, the method for manufacturing a probe according to the present invention includes a probe tip for etching a wafer to generate a region in which a first probe and a second probe tip of a multilayer structure having a fine pitch are to be formed. Region generation step; A probe body region generating step of etching a wafer on which the tips of the first and second probes of the multilayer structure are formed to generate a region in which a body of the first and second probes of the multilayer structure is to be formed; A probe generation step of plating the probe tip region and the probe body region to generate the first probe and the second probe of the multilayer structure; And a wafer removing step of combining the first probe and the second probe with a circuit board and removing the wafer. Characterized in that it comprises a.

The plurality of first and second probes of the multilayer structure generated according to the probe generation step may be generated on the wafer.

The generating of the probe tip region may include: a first etching process of etching portions of the first probe and the second probe of the multilayer structure to be formed by using a deep silicon etchant; And a second etching process of additionally etching a portion of the tip (TIP) of the first and second probes etched by the first etching process along the single crystal structure of the wafer using potassium hydroxide. Characterized in that it comprises a.

The generating of the probe body region may include applying a photoresist to the wafer; Patterning the applied photoresist; Etching the wafer according to the pattern; The wafer may be etched by an ICP (Inductive Coupled Plasma) Etcher or Deep Silicon Etcher.

The generating of the probe may include depositing a conductive thin film on a region where the first probe and the second probe are to be formed; Plating a conductive material on a region where the conductive thin film is deposited; Characterized in that it comprises a.

The first probe and the second probe of the multilayer structure generated according to the probe generation step are characterized in that the first projection and the second projection for coupling with the circuit board are formed, respectively.

In addition, a probe grinding step of grinding the first probe and the second probe of the multilayer structure to maintain the flatness of the first and second probes of the multilayer structure generated by the probe generation step; It characterized in that it further comprises.

The first probe and the second probe of the multilayer structure bonded to the circuit board may be coupled to each other by a flip chip bonder.

As described above, according to the present invention, since the plurality of probes including the multilayer probes of the first probe and the second probe are generated from one wafer, the multilayer structure of the first probe and the second probe is formed. There is an effect that can be finely adjusted a plurality of probe pitch, including the probe.

In addition, since a single wafer is used to generate a plurality of probes including a multilayer probe of a first probe and a second probe having a fine pitch, there is an economic effect of improving productivity and reducing manufacturing cost.

In addition, since a plurality of probes including the multilayer probes of the first and second probes are simultaneously generated, the manufacturing time and the cost and time are reduced by reducing the manufacturing time.

In addition, since a plurality of probes including the multilayer structure of the first probe and the second probe are formed and other regions are etched, a plurality of probes including the multilayer probe of the first probe and the second probe are generated. It is convenient to remove the back wafer, and the chemical material used at this time has the effect of significantly reducing the chemical stress that may be applied to the probe and the circuit board.

In addition, since titanium and copper are deposited and then a conductive material, such as nickel or nickel alloy, is plated with good durability, the durability of the probe may be improved, and thus the economic performance of the probe may be maintained even after long-term use.

In addition, by bundling wafers and circuit boards in which multiple probes having a multilayer probe structure are formed by using a flip chip bonder, the accuracy and reproducibility of fine pitches are superior to those of manual work, thereby improving quality and productivity. There is an effect to be improved.

1 is a perspective view of a probe device according to the present invention.
2A to 2U are partial cross-sectional views of a process for generating a probe device according to the present invention.
3A to 3F are partial cross-sectional views of a process for producing a probe device according to the present invention.

The preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings, in which the technical parts already known will be omitted or compressed for simplicity of explanation.

<Description of Configuration>

Probe device 100 according to the present invention by etching the wafer to form a fine pitch that is the interval between the tip of the first probe and the tip of the second probe to inspect the semiconductor device or LCD panel, such as the probe card and probe unit Description of the device is made with reference to the drawings shown in FIG.

The probe device 100 according to the present invention includes a first probe 110, a second probe 120, a circuit board 130, and the like.

The first probe 110 is in contact with a first terminal (not shown) of the semiconductor device, and includes a first probe tip 111 and a first probe body 112.

The first probe tip 111 is in direct contact with the first terminal (not shown) of the semiconductor device. The first probe tip 111 may be formed in any form as long as it can be in contact with the first terminal (not shown), so as to reduce wear of the tip and to contact the first terminal (not shown) of a fine width. It is preferable that it consists of trapezoidal form.

The material of the first probe tip 111 may be made of any material as long as it is a conductive material capable of flowing current, but at least one of nickel, nickel cobalt, platinum, tungsten, and rhodium, or nickel, nickel cobalt, It is preferably made of an alloy in which two or more materials of platinum, tungsten and rhodium are mixed.

In addition, it is preferable that a conductive thin film is formed on the outer surface of the first probe tip 111 to enhance durability. At this time, the conductive thin film is preferably made of titanium and copper in order to improve the adhesion density and conductivity of the first probe tip 111.

The conductive thin film is preferably made in the order of the first probe tip 111, the copper thin film, the titanium thin film from the inside out.

The first probe body 112 is coupled to the first probe tip 111 and the circuit board 130 and includes a first stick part 112a and a first protrusion part 112b.

The first stick part 112a is coupled to the first probe tip 111 and the first protrusion part 112b, so that an impact generated when the first probe tip 111 comes into contact with the first terminal of the semiconductor device. In order to disperse efficiently, it is preferably made in the form of sticks.

The first protrusion 112b is a place where the first stick part 112a and the circuit board 130 are coupled, and may be formed to protrude on one side of the first probe body 112.

That is, the first probe body 112 may be formed in the form of "━ 형태" combined with the stick portion and the protrusion.

In addition, the material of the first probe tip 111 may be made of any material as long as it is a conductive material capable of flowing current, but at least one or more of nickel, nickel cobalt, platinum, tungsten, and rhodium, or nickel, nickel cobalt, It is preferably made of an alloy in which two or more materials of platinum, tungsten and rhodium are mixed.

The first probe tip 111 and the first probe body 112 may be manufactured in various ways according to the manufacturing process, the first probe on the other side of the first probe body 112 to increase the durability of the first probe. It is preferable that the probe tip 111 is manufactured in the form of an integrated " ┓━┓ "

The second probe 120 is in contact with a second terminal (not shown) of the semiconductor device, and includes a second probe tip 121 and a second probe body 122. The second probe body 122 includes a second stick part 122a and a second protrusion part 122b. Descriptions of the shape and material of the second probe tip 121 and the second probe body 122 are the same as those of the first probe tip 111 and the first probe body 112 and are omitted.

In addition, the pitch, which is the distance between the tips of the first probe and the second probe, may have various values according to the manufacturing process of the first probe 110 and the second probe 120, and the fine pitch formed in the semiconductor device or the LCD panel. It is preferred that the first terminal (not shown) and the second terminal (not shown) of the fine to be in contact with.

The circuit board 130 is coupled with a plurality of probes (not shown) including the first probe 110 and the second probe 120 to balance the plurality of probes in order to inspect the semiconductor device or the LCD panel for defects. It is a fixed board with a circuit that supports it. The circuit board 130 includes bumps 131 and bumps protruding on one side of the circuit board 130 so that the first probe 110 and the second probe 120 can be easily coupled. It is desirable to have.

<Description of the method>

Hereinafter, a method of manufacturing the probe apparatus 100 described above will be described with reference to the drawings illustrated in FIGS. 2A to 3F. In addition, the method of manufacturing the probe device 100 according to the present invention may produce a plurality of multilayer probes by manufacturing a plurality of multilayer probes including a first probe and a second probe on a wafer, but for convenience of description, A method of manufacturing one multilayer probe consisting of one probe and a second probe will be described.

2A, oxides 202 and 203 are formed by injecting oxygen into the first wafer 201 through a diffusion furnace or a furnace. At this time, the step of forming the oxide film (202, 203) is preferably performed at a temperature of 800 ℃ to 1500 ℃. The oxide films 202 and 203 can also be formed by low pressure vapor deposition using LPCVD.

Thereafter, as shown in FIG. 2B, the first photoresist is applied to the upper surface of the first wafer 201, and then baked in a hot plate or a convection oven to bake the first photoresist layer 204. To form. At this time, the temperature of the hot plate or convection oven is preferably made of 70 ℃ to 150 ℃.

Next, as shown in FIG. 2C, a pattern 204a of the first probe tip and the second probe tip is formed using a mask using a UV aligner. Subsequently, the oxide film of the portion where the photoresist layer is removed by UV aligner is etched using a BOE (Buffered Oxide Echant) solution to form oxide patterns 202a of the first probe tip and the second probe tip. .

Then, as shown in FIG. 2D, the silicon of the patterned portion is etched using the Deep Silicon Etcher to form the second wafer 201a and form the region 205 of the first probe tip and the region 206 of the second probe tip. .

Next, as shown in FIG. 2E, the region 205 of the first probe tip etched and the region 206 of the second probe tip are etched using potassium hydroxide to form silicon and then the third wafer 201b. It is preferable to generate the and form an extension region 205a of the first probe tip and an extension region 206a of the second probe tip. In addition, the extended region 205a of the first probe tip and the extended region 206a of the second probe tip may be adjusted in depth and shape according to the contact time of potassium hydroxide and silicon, and the extended region of the first probe tip ( Etching may be performed such that the diameters of the portions 205a) and the extension region 206b of the second probe tip are 5 µm to 20 µm. At this time, etching by potassium hydroxide to form portions of the extended region 205a of the first probe tip and the extended region 206b of the second probe tip is performed at the place where the probe device 100 according to the present invention is used and the semiconductor device. Although it can be made at various angles according to the size of the terminal formed on the LCD panel, etc., it is preferably made at a constant angle of 57.4 degrees.

Next, as shown in FIG. 2F, a second photoresist for forming an alignment key is applied to the top and bottom surfaces of the third wafer 201b, and baked to bake the top photoresist layer 207 and the bottom photoresist layer ( Not shown). After that, the alignment key pattern 208 is formed on the bottom surface only by using a UV aligner. Thereafter, the exposed portion is etched using the BOE (Buffered Oxide Echant) solution after forming the alignment key pattern 208, and then the oxide pattern 203a of the alignment key is formed, and then immersed in potassium hydroxide to pattern the oxide patterned silicon. Etch to form a fourth wafer (201c) to complete the alignment key. This alignment key enables various patterns on the fourth wafer 201c and various patterns on the mask to be accurately aligned across all areas within the fourth wafer 201c.

Thereafter, as shown in FIG. 2G, all photoresist applied to the fourth wafer 201c is removed, and the third photoresist is applied to the upper surface of the fourth wafer 201c and baked. Subsequently, a UV probe is used to form the pattern 209 of the second probe body using a mask.

Next, as shown in FIG. 2H, the oxide layer of the portion where the photoresist layer is removed by UV Aligner is etched using a BOE (Buffered Oxide Echant) solution to form an oxide layer pattern 202b of the second probe body. do.

Thereafter, as shown in FIG. 2I, all photoresist applied to the fourth wafer 201c is removed.

Next, as shown in FIG. 2J, the silicon of the patterned portion is etched by using an ICP Etcher or Deep Silicon Etcher to generate a fifth wafer 201d and a second probe body. Form an area 210.

Then, as illustrated in FIG. 2K, a conductive thin film is deposited on the first probe tip extension region 205a, the second probe tip extension region 206a, and the region 210 of the second probe body by using a spatter or CVD to form a first thin film ( 211 and a second thin film 212 are formed. In this case, the conductive thin film may be made of titanium (Ti) and copper (Cu). In addition, the conductive thin film is preferably deposited in the order of titanium (Ti) and copper (Cu).

Next, as shown in FIG. 2L, the first plating body 213 and the second plating are plated by conducting a conductive material on the first probe tip, the second probe tip and the second stick part of the second probe body by using an electroplating method. Sieve 214 is formed. Here, the first probe tip 111 of the first probe 110 is generated through the first thin film 211 and the first plating body 213. In addition, the second probe tip 121 of the second probe 120 and the second stick portion 122a of the second probe body 122 are generated through the second thin film 212 and the second plating member 214. do. The conductive material may be at least one of nickel (Ni), cobalt (Co), platinum (Pt), tungsten (W) and rhodium (Rh) or nickel, cobalt, platinum, tungsten and rhodium, such as NiCo and NiCoW. It is preferable that the alloy is made of a mixture of two or more materials. In addition, the length of the second probe body 122 may be made of 500um to 4000um. In addition, the thickness and the width of the second stick part 122a of the second probe body 122 may be made of 35um to 150um.

Thereafter, after the fourth photoresist is applied and baked as shown in FIG. 2M, the pattern 215 of the second protrusion region of the second probe body is formed using a mask.

Next, as shown in FIG. 2N, the third plating body 214a is formed by plating a conductive material parallel to the upper surface of the fifth wafer 201d on a part of the protruding portion of the second probe body by using an electroplating method. The conductive material may be at least one of nickel (Ni), nickel cobalt (NiCo), platinum (Pt), tungsten (W) and rhodium (Rh) or nickel, cobalt, platinum, tungsten and rhodium such as NiCo and NiCoW. It is preferable that the alloy is made of a mixture of two or more of them.

After removing the photoresist layer and filling the fixing body 216 on the upper surface of the second stick portion of the second probe as shown in FIG. 2o, CMP or grinding is performed to form the upper surface of the fifth wafer 201d. The fixture 216 is shaved to have the same height. In this case, the fixture 216 may be made of an easy bond (EZ-Bond), a crystal bond or a photoresist.

Next, as illustrated in FIG. 2P, a fifth photoresist is applied to the upper surface of the fifth wafer 201d to form the first probe body pattern 217. Thereafter, a conductive thin film is deposited on the first probe body region using a spatter or CVD to form a third thin film 218. In this case, the conductive thin film may be made of titanium (Ti) and copper (Cu). In addition, the conductive thin film is preferably deposited in the order of titanium (Ti) and copper (Cu). The photoresist layer is then removed.

Thereafter, as illustrated in FIG. 2Q, the sixth photoresist is applied to the upper surface of the fifth wafer 201d, and the first stick part of the first probe body and the second protrusion part of the second probe body are formed 219. A portion of the stick portion region and the second protrusion portion region is plated with a conductive material by using an electroplating method to form the fourth plating member 213a and the fifth plating member 214b. Here, the first stick part 112a of the first probe body 112 of the first probe 110 is generated through the third thin film 218 and the fourth plating body 213a. The conductive material may be at least one of nickel (Ni), nickel cobalt (NiCo), platinum (Pt), tungsten (W) and rhodium (Rh) or nickel, cobalt, platinum, tungsten and rhodium such as NiCo and NiCoW. It is preferable that the alloy is made of a mixture of two or more of them. Herein, the conductive materials to be plated with the first stick part and the second protrusion part are preferably the same material. The photoresist layer is then removed. In addition, the length of the first probe body may be made of 500um to 4000um. In addition, the thickness and width of the first stick portion 112a of the first probe body 112 may be made of 35um to 150um.

Next, as illustrated in FIG. 2R, a seventh photoresist is applied to the upper surface of the fifth wafer 201d, and the pattern 220 of the first protrusion of the first probe body and the second protrusion of the second probe body is formed. The sixth plating member 213b and the seventh plating member 214c are formed by plating a conductive material on the remaining portions of the first protrusion region and the second protrusion region using an electroplating method. In this case, the upper surfaces of the sixth plating member 213b and the seventh plating member 214c are preferably processed by CMP or grinding to be smoothly coupled to the circuit board or the bump. That is, in order to maintain the flatness of a 1st protrusion part and a 2nd protrusion part, the part which protruded unnecessarily is ground. Here, the first protrusion 112b of the first probe body 112 of the first probe 110 is generated through the sixth plating body 213b. In addition, a second protrusion 122b of the second probe body 122 of the second probe 120 is generated through the fifth plating body 214b and the seventh plating body 214c. That is, the first probe 110 and the second probe 120 are generated by etching a wafer to deposit a thin film and plate a metal. The conductive material may be at least one of nickel (Ni), nickel cobalt (NiCo), platinum (Pt), tungsten (W) and rhodium (Rh) or nickel, cobalt, platinum, tungsten and rhodium such as NiCo and NiCoW. It is preferable that the alloy is made of a mixture of two or more of them. Herein, the conductive materials to be plated on the first stick part 112a and the second protrusion part 122b are preferably the same material. The photoresist layer is then removed.

The solder paste formed on the circuit board 130 or the bump 131 due to the first protrusion 112b and the second protrusion 122b formed on the sixth plating body 213b and the seventh plating body 214c. Solder Paste or conductive epoxy flows between the fine pitch of the first probe 110 and the second probe 120, causing the probe device to malfunction or to flow into the first probe body or the second probe body. The phenomenon that the adhesive force weakens can be prevented.

Thereafter, as shown in FIG. 2S, after the first probe, the second probe, and the circuit board are combined, a part of the lower surface of the fifth wafer 201d (first probe and second probe) is formed to smoothly separate the fifth wafer 201d and the probe. After the eighth photoresist is applied and baked on the lower surface of the fifth wafer 201d so as to float (area other than the region to be formed), the floating pattern 221 is formed.

Next, as illustrated in FIG. 2T, the oxide layer of the patterned portion is etched on the bottom surface of the fifth wafer 201d with a buffered oxide etch (BOE) solution to form a floating oxide pattern 203b. Thereafter, the silicon of the patterned portion is etched using an ICP etcher or a deep silicon etchant to produce a sixth wafer 201e.

Then, as shown in FIG. 2u, all photoresist is removed using a strip solution. The photoresist layer may be removed by dipping for 10 minutes to 30 minutes in a NaOH solution at 60 ° C. to 80 ° C. in a heated condition, or all photoresist layers may be removed using acetone (Acetone: CH 3 CoCH 3). In addition, when the fixture 216 filled on the upper surface of the second stick part of the second probe is an easy bond (EZ-Bond) or a crystal bond, the sixth wafer 201e is heated to 100 ° C to 130 ° C to recover fluidity. Easy bonds or crystal bonds can be removed and the remaining residue can be removed with alcohol.

Next, as shown in FIG. 3A, a photoresist is applied to the circuit board 130 coupled to the sixth wafer 201e where the probe is generated, and baked to form a photoresist layer 301.

Thereafter, as illustrated in FIG. 3B, a bump pattern 301a is formed using a mask using a UV aligner.

Next, as illustrated in FIG. 3C, the conductive material is plated according to the bump pattern 301a to generate the bump 131. The conductive material may be at least one of nickel (Ni), nickel cobalt (NiCo), platinum (Pt), tungsten (W) and rhodium (Rh) or nickel, cobalt, platinum, tungsten and rhodium such as NiCo and NiCoW. It is preferable that the alloy is made of a mixture of two or more of them. At this time, the height of the bump 131 is preferably made of 50um to 900um so that the first probe 110 and the second probe 120 can be easily coupled.

Thereafter, as illustrated in FIG. 3D, a solder paste or a conductive epoxy is sprayed or printed onto the bumps using a dispenser or a screen printer to generate an adhesive part 302.

Next, as illustrated in FIG. 3E, the sixth wafer 201e on which the first probe 110 and the second probe 120 are formed and the circuit board 130 on which the bumps 131 are formed are aligned using a bonder. Bond by applying heat. In this case, a bonding process using a bonder may be applied to high pin counts or fine pitch, and the upper surface of the sixth wafer 201e and the upper surface of the circuit board 130 are smoothly coupled. The sixth wafer 201e in which the first probe 110 and the second probe 120 are formed and the circuit board 130 in which the bumps 131 are formed may be bonded by using a flip chip bonder. It is preferable to (Bonding). Here, the temperature to be heated may be made of 150 ℃ to 450 ℃, this temperature may be adjusted to an appropriate temperature depending on the binder used.

Thereafter, as illustrated in FIG. 3F, the conductive thin film between the first probe 110 and the second probe 120, the sixth wafer 201e, and the oxide films 202b and 203b are removed to manufacture the probe device 100.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. And the scope of the present invention should be understood as the following claims and their equivalents.

100: probe device
110: first probe
111: first probe tip
112: first probe body
112a: first stick part 112b: first protrusion part
120: second probe
121: second probe tip
122: second probe body
122a: second stick portion 122b: second projection portion
130: circuit board
131 bump

Claims (24)

A probe region etching step of etching a region in which a first probe having a constant pitch and a second probe having a multilayer structure with the first probe are formed in one wafer;
Generating a first probe and a second probe by plating the etched region;
A probe coupling step of coupling the first probe and the second probe with a circuit board; And
A wafer removal step of removing the one wafer while leaving the first and second probes coupled through the probe coupling step; Including;
The tip of the first probe and the tip of the second probe are formed at the same time,
The stick portion of the body portion of the first probe and the stick portion of the body portion of the second probe is characterized in that formed at each other
Probe device manufacturing method. The method of claim 1,
A plurality of first and second probes of the multilayer structure generated by the probe generation step is generated on the wafer
Probe device manufacturing method. The method of claim 1,
A non-forming region etching step of etching regions other than regions where the first and second probes of the multilayer structure are to be formed; &Lt; RTI ID = 0.0 &gt;
Probe device manufacturing method. The method of claim 3,
In the probe region etching step, the upper surface of the wafer is etched,
In the non-forming region etching step, the bottom surface of the wafer is etched.
Probe device manufacturing method. The method of claim 1,
The probe region etching step
A first etching process of etching a portion in which a tip (TIP) of the first probe and the second probe of the multilayer structure is to be formed;
A second etching process of additionally etching a portion where a tip (TIP) of the first probe and the second probe etched by the first etching process is to be formed; And
A third etching process of etching portions of the body of the first probe and the second probe to be formed; Characterized in that it comprises
Probe device manufacturing method. The method of claim 5,
In the second etching process, the wafer is etched using potassium hydroxide according to the single crystal structure of the wafer.
Probe device manufacturing method. The method of claim 5,
In the third etching process, the wafer is etched using an inductive coupled plasma (ICP) etchant or a deep silicon etchant.
Probe device manufacturing method. The method of claim 1,
The first probe and the second probe of the multilayer structure generated according to the probe generation step are characterized in that the first protrusion and the second protrusion for coupling to the circuit board are formed, respectively.
Probe device manufacturing method. The method of claim 1,
The probe generation step
Depositing a conductive thin film on a region where the first probe and the second probe of the multilayer structure are to be formed; And
Plating a conductive material on a region where the conductive thin film is deposited; Characterized in that it comprises
Probe device manufacturing method. 10. The method of claim 9,
The conductive thin film is characterized in that consisting of titanium (Ti) and copper (Cu)
Probe device manufacturing method. 10. The method of claim 9,
The conductive material is made of at least one of nickel (Ni), nickel cobalt (NiCo), platinum (Pt), tungsten (W) and rhodium (Rh)
Probe device manufacturing method. The method of claim 1,
A probe grinding step of grinding the first probe and the second probe of the multilayer structure to maintain the flatness of the first and second probes of the multilayer structure generated according to the probe generation step; &Lt; RTI ID = 0.0 &gt;
Probe device manufacturing method. The method of claim 1,
The first probe, the second probe, and the circuit board of the multilayer structure coupled according to the probe bonding step may be coupled by a flip chip bonder.
Probe device manufacturing method. The method of claim 1,
The probe coupling step
Applying a photoresist to the circuit board;
Patterning the applied photoresist; And
Generating a bump by plating a conductive material on the circuit board according to the pattern; Including;
The probe is coupled to the bump
Probe device manufacturing method. The method of claim 14,
The conductive material is made of at least one of nickel (Ni), nickel cobalt (NiCo), platinum (Pt), tungsten (W) and rhodium (Rh)
Probe device manufacturing method. delete A probe tip region generation step of etching one wafer to generate a region where a first probe and a second probe tip of a multilayer structure having a constant pitch are formed;
A probe body region generating step of etching a wafer on which the tips of the first and second probes of the multilayer structure are formed to generate a region in which a body of the first and second probes of the multilayer structure is to be formed;
A probe generation step of plating the probe tip region and the probe body region to generate the first probe and the second probe of the multilayer structure; And
A wafer removing step of combining the first probe and the second probe of the multilayer structure with a circuit board and removing the one wafer; Including;
The tip of the first probe and the tip of the second probe are formed at the same time,
The stick portion of the body portion of the first probe and the stick portion of the body portion of the second probe is characterized in that formed at each other
Probe preparation method. The method of claim 17,
A plurality of first and second probes of the multilayer structure generated by the probe generation step is generated on the wafer
Probe preparation method. The method of claim 17,
The probe tip area generation step
A first etching process of etching portions of the first probe and the second probe of the multilayer structure to be formed using a deep silicon etcher; And
A second etching process of additionally etching portions of the first probe and the second probe, which are etched by the first etching process, along the single crystal structure of the wafer using potassium hydroxide; Characterized in that it comprises
Probe preparation method. The method of claim 17,
The generating of the probe body region is
Applying a photoresist to the wafer;
Patterning the applied photoresist; And
Etching the wafer according to the pattern; Including;
The wafer is etched by an ICP (Inductive Coupled Plasma) Etcher or Deep Silicon Etcher
Probe preparation method. The method of claim 17,
The probe generation step
Depositing a conductive thin film in a region where the first probe and the second probe are to be formed; And
Plating a conductive material on a region where the conductive thin film is deposited; Characterized in that it comprises
Probe preparation method. The method of claim 17,
The first probe and the second probe of the multilayer structure generated according to the probe generation step are characterized in that the first protrusion and the second protrusion for coupling to the circuit board are formed, respectively.
Probe preparation method. The method of claim 17,
A probe grinding step of grinding the first probe and the second probe of the multilayer structure to maintain the flatness of the first and second probes of the multilayer structure generated according to the probe generation step; &Lt; RTI ID = 0.0 &gt;
Probe preparation method. The method of claim 17,
The first probe and the second probe of the multilayer structure coupled to the circuit board are coupled by a flip chip bonder.
Probe preparation method.

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