TW200419159A - Probe for testing flat panel display and manufacturing method thereof - Google Patents
Probe for testing flat panel display and manufacturing method thereof Download PDFInfo
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- TW200419159A TW200419159A TW92132733A TW92132733A TW200419159A TW 200419159 A TW200419159 A TW 200419159A TW 92132733 A TW92132733 A TW 92132733A TW 92132733 A TW92132733 A TW 92132733A TW 200419159 A TW200419159 A TW 200419159A
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- probe
- dielectric
- sacrificial substrate
- forming
- substrate
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
Abstract
Description
玖、發明說明: 【發明所屬之技術領域】 本發明係關於與用以測試平面板顯 製造方法有關。更特別言 、、^ 木針及其 一 口心本發明與用以測續承;』 不器之探針有關,其中平 …千面板顯 ^ ^ 置之複數個導體堆A私v 個其它導體間,—探針 纟且於絲 Λι 必^木針,本發明並盥掣侔外2 針及該探針組之方法有關。 乃工/、衣4该探 特別言之,本發明與用 關,J:由卢^] 4平面板顯示器之探針有 ^ 產‘程期間,無需於一 MEMS單元中 機黏著探針導體之製程 早Hi用接合 獲侍精確對齊之導體,本發 月亚14製造該探針之方法有關。 此外,本發明與用以測試平面板顯示器之探針有關,盆 中利用在單-犧牲基板上之MEMS製程,於料—犧牲基板 之兩平面上形成探針導體,本發明並與製造該探針之方法 有關。 【先前技術】 概言之,TFT-LCD(薄膜冑晶體液晶顯示器)裝置係一平面 板顯不器’其包括具預定尺寸之下板,其中具有多個薄膜 U體(TFT)及各像素電極’·—與該下板間具預定距離之用 以著色之彩色濾波器;一與該下板間具預定距離且依序具 有共用電極之下板,以及介於上下板間之液晶。 該TFT-LCD裝置包括複數個TFT,其係由上下板間之液晶 產生之切換構件、電容器區與輔助電容器區;用以驅動TFT 之ΟΝ/OFF之閘極驅動電極;以及用以施加外部影像信號之 O:\89\89662.DOC -6- 200419159 影像信號電極,藉以顯示 ..^ ^ 如像(包含移動影像)。 一 ^ 4造完成後,平面板顯示器如TFT-LCDI^ ¥ 經探針組與平面板顯示器之電極墊接。、Μ 保平面板顯示器正常, ^ υ /過程,以与 ^ η # 1除不良平面板顯示器。 居別4係利用具探針組之 種類型之摆π , 卞儀為知仃。丽已發展出各 針儀盗。探針儀器包含針形探針儀 儀器。、开J木針儀…及他⑽(微電機系統)探針 度積體化而極度銳化 平需發展具有優良再產率與高生產率,並且足敷 千面板顯示器之精細間距(piteh)t求之探針組。 【發明内容】 本發明之設計係為符合前階發展需求 在於提供可符外制< ^ ^目的 、8衣程,並因而縮減製程時間之用以測試平 面板顯示H探針’及製造該探針之方法。 本發明之另—目的在於提供可在生產製程期間,去除在 /EMS單元中利用接合機黏著探針導體之製程,並因而獲 传極精確對齊之輕 、、、 ^ 、+ ¥體之用以測試平面板顯示器之探 針,及製造該探針之方法。 本卷月之一目的在於提供一種用以測試平面板顯示器之2. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a manufacturing method for testing a flat panel display. More specifically, the wooden needle and its mouthpiece The present invention relates to a probe for measuring renewal; the probe of which is not flat, in which the flat panel is placed on a plurality of conductor stacks and other conductors -The probe must be a wooden needle in the wire, and the present invention relates to the method of using the outer 2 needles and the probe set. In particular, this probe is related to the present invention. The invention is related to the use, J: from Lu ^] During the production process of the probe of the flat panel display, it is not necessary to adhere the probe conductor in a MEMS unit. The manufacturing process uses a spliced conductor to precisely align the conductors, which is related to the method of manufacturing the probe. In addition, the present invention relates to a probe for testing a flat panel display. A MEMS process on a single-sacrificial substrate is used in the basin to form a probe conductor on two planes of the material-sacrificial substrate. The present invention is also related to manufacturing the probe. Needle-related. [Prior art] In summary, a TFT-LCD (thin film crystalline liquid crystal display) device is a flat panel display 'which includes a lower panel with a predetermined size, which has a plurality of thin film U bodies (TFT) and pixel electrodes' -A color filter with a predetermined distance from the lower plate for coloring; a lower plate with a predetermined distance from the lower plate and sequentially having a common electrode, and a liquid crystal interposed between the upper and lower plates. The TFT-LCD device includes a plurality of TFTs, which are switching members, capacitor regions and auxiliary capacitor regions generated by liquid crystal between upper and lower plates; gate drive electrodes for driving ON / OFF of the TFTs; and for applying external images Signal O: \ 89 \ 89662.DOC -6- 200419159 Image signal electrode for display .. ^ ^ Such as image (including moving image). After the ^ 4 fabrication is completed, the flat panel display such as TFT-LCDI ^ ¥ is connected to the electrode pad of the flat panel display via the probe set. 2. Make sure that the flat-panel display is normal, and ^ υ / process to divide the bad flat-panel display with ^ η # 1. Jubei 4 uses a pendulum with a probe set of various types, and the funeral is known. Lai has developed various needle instrument thefts. Probe instruments include needle probe instruments. , Open J wooden needle meter ... and other (micro-motor system) probes are integrated and extremely sharp. Need to develop with excellent re-productivity and high productivity, and the fine pitch of the thousand-panel display (piteh) t Find the probe set. [Summary of the invention] The design of the present invention is to meet the requirements of the previous stage of development, which is to provide an external system < ^ ^ purpose, 8 processes, and thus reduce the process time to test the flat panel display H probe 'and manufacture the Probe method. Another object of the present invention is to provide a process that can eliminate the use of a bonding machine to bond the probe conductor in the / EMS unit during the production process, and thus obtain a light ,,, ^, + ¥ body that is extremely accurately aligned. Test a probe for a flat panel display, and a method for manufacturing the probe. One of the purposes of this volume is to provide a
制1、及其衣&方法,藉由針對一單一犧性基板使用MEMS 衣転’该探針就能夠在一犧性基板上之兩個面板上 針導體。Method 1, and a garment & method thereof, by using a MEMS garment for a single sacrificial substrate, the probe can pin conductors on two panels on a sacrificial substrate.
O:\89\89662.DOC 200419159 拓:達ί述目的,本發明之一態樣提供-種用以測試平面 '、、不态之探針,該顯示器包括-類板狀介電質 平行導體,以及位於該介電質之上下平面中:二:數個 土之第-渠溝’俾以預定配置固定該等複體二: 電質中。 ¥體於该介 本1明之另—態樣提供一種用以測試 針,該顯示界包括以瑕頒不益之探 一預疋間隔位於並固定於-薄膜之下 =之複數個單元接觸組件,其中該薄膜具 中一檢測尖端係以敫人古々 九束構件,及其 鳊係以正合方式位於該光束構件之一 本發明之另一能样趄报 和上。 針,該顯示哭^以測試平面板顯示器之探 #lJ 匕括犧牲基板;利用一微影製程盥Ut. 製程形成之第—準溝.刹田^...衣私與一蝕刻 間一位於該犧牲基板上之該等第一渠溝 等導體上形成之第一介電質;及利用一微鱼一在該 製程形成之第二準聋I Λ心氣釦與一蝕刻 下平面上;一 # ώ ^ ^ ^ 、 Μ犧牲基板之 错由將一介電質材料嵌 形成之第二介電質。 /寻弟一朱溝令而 本發明之另一態樣提供一種 探針,包括··—類板狀介 ^犧牲基板形成之 溝係由-微,制η 及獲數個導體,其中的渠 风〜裂矛王與一飯刻制 於該等渠溝中,其中該等^ /中一傳導材料嵌 該介電質之該等上與下預定㈣ 之該等導體與在該下平面切/其Γ在該上平面上形成 /成之5亥寺導體平行。O: \ 89 \ 89662.DOC 200419159 Extension: To achieve the stated purpose, one aspect of the present invention provides a probe for testing planar and non-stateful probes. The display includes a plate-like dielectric parallel conductor. , And in the plane above and below the dielectric: two: the first-ditch of several soils; the complexes are fixed in a predetermined configuration; two: the electric medium. ¥ body in the introduction of this book is different-the form provides a test pin, the display field includes a plurality of unit contact components which are located and fixed below the film at a pre-empty interval, which is unfavorable. Wherein, a detection tip of the thin film device is composed of a nine-beam ancient member, and a pair thereof is located in a positive manner on one of the beam members, which is another energy sample of the present invention. Needle, the display is crying ^ to test the flat panel display #lJ Dagger sacrifice substrate; the use of a lithography process Ut. Process formed the first-Zhungou. Chatian ^ ... clothing and an etching room is located A first dielectric formed on the first trenches and other conductors on the sacrificial substrate; and a micro-fish one on the second quasi-deaf I Λ heart gas button formed on the process and an etched lower plane; a # ^ ^ ^ The fault of the sacrifice substrate is a second dielectric formed by embedding a dielectric material. / Xundi-Zhugou Ling and another aspect of the present invention provides a probe, which includes a plate-like medium. The groove formed by the sacrificial substrate is made of -micro, made η and obtained a number of conductors. Wind ~ Splinter King and Yifan are engraved in the trenches, where the ^ / medium-one conductive material is embedded in the upper and lower predetermined conductors of the dielectric and cut in the lower plane / Its Γ is formed / formed on the upper plane to be parallel to the 5Hai Temple.
O:\89\89662.DOC 200419159 ”本發明之另一態樣提供一種使用一單一犧牲基板形成之 探針,包括:一類板狀第一介電質;一堆疊之第二介電質, 其在—該第—介電質之上部形成一步階差;以一預定間隔 配置之複數個導體,以穿透該等第一與第二介電質;及一 藉由預疋私鍍方法堆疊一傳導材料於各該等導體之一平 面上之傳導層。 扣本發明之另-態樣提供—種使用—單—犧牲基板形成之 1木針’包括:-藉由堆疊-陶瓷板於-環氧化物之上與下 平面上而形成之介電質;以一預定間隔於該介電質之該等 上,下平面上形成之複數個導體;一藉由—預定電鍍方法 ^疊於二各該等導體之平面上之傳導層;及堆疊於該介電 貝之该寺上與下平面上之支撐組件,以固定該等導體之位 置。 。本&明之另—態樣提供-種使用—單―犧牲基板形成之 揀針二包括:一類板狀介電質;以一預定間隔於該介電質 之该等上與下平面上形叙魏個導體;—藉由—預定雨 錄t法㈣於各料導體之—平面上之料^及堆疊二 口亥"笔質之該等上盘下单 t ^ , 一下千面上之支撐組件,以固定該等導 體之位置。 本·^月之另一怨樣提供一種製一 示器之探針之方法,包括牛“-平面板顯 匕括步私·一於一介電質之上與下 面之至少一平面上形成第一 ★ 弟木溝之弟一渠溝形成步驟,藉 支樓組件於該介電質 ,·,、疋配置固定複數個導體於該介電質上;及一堆疊 之上平面或一下平面上之支撐組O: \ 89 \ 89662.DOC 200419159 "Another aspect of the present invention provides a probe formed using a single sacrificial substrate, including: a type of plate-shaped first dielectric; a stacked second dielectric, A step difference is formed on the -dielectric material; a plurality of conductors arranged at a predetermined interval to penetrate the first and second dielectric materials; and The conductive layer of a conductive material on one of the planes of each of these conductors. Another aspect of the present invention provides-a kind of use-a single-sacrificial substrate formed by 1 wooden pin 'includes:-by stacking-ceramic plates in-ring Dielectrics formed on and above the oxide; a plurality of conductors formed on the upper and lower planes of the dielectric at a predetermined interval; Conductive layers on the planes of these conductors; and supporting components stacked on the upper and lower planes of the temple in the dielectric shell to fix the positions of these conductors. This & Mingzhi-Provided in other ways-use —Single—The second pick pin formed by the sacrificial substrate includes: a type of plate-like dielectric; The conductors are shaped on the upper and lower planes of the dielectric at a predetermined interval;-by a predetermined rain record t method, on the conductors of each material-the material on the plane ^ and stacking two mouths & quot The pen-like order on the upper plate t ^, the supporting components on the thousand surfaces to fix the position of these conductors. Another problem of this month is to provide a method of making a probe for the indicator, Including the "planar board"-a step above a dielectric and forming a first on at least one plane below the dielectric ★ Dimugou's Diyigou formation step, borrowing branch components to the dielectric Mass, · ,, and 疋 are configured to fix a plurality of conductors on the dielectric; and a support group on a plane above or below the stack
O:\89\89662.DOC 200419159 件形成步驟,藉此固定該等導體於該介電質上之該等第 渠溝中。 ' -亡發明之另一態樣提供一種製造一用以測試一平面板顯 不器之探針之方法,包括:—導體形成步驟,其係利用— 微影製程與一傳導膜形成製程於一具一預定厚度之單一犧 牲基?之一上平面與一下平面之至少一平面上形成光阻圖 案’藉以形成導體;一介電質形成步驟,其係利用一微影 形成光阻圖案,俾開啟一各該等導體之中央部,並於各該 等導體之開啟中央部上形成—介電質;—渠溝形成步驟: 其係利用-微影與-_製程形成渠溝,俾露出各該等導 體之該下平面;—藉由喪人―支撐組件於該等渠溝中而形 成-支樓組件之支撐組件形成步驟;及—移除該犧牲基板 之完結步驟。 一亡%明之另一態樣提供一種製造一用以測試一平面板顯 示器之探針之方法,包括:一利用一微影製程及第一與第 二#刻製程形成具有歷經—圓化製程之底部之第—渠溝之 第-渠溝形成步驟;一導體形成步驟,其係利用一二 程開啟具該等第一渠溝之中央部,接著將一傳導材料嵌二 開啟區中,藉以形成導體;—利用—微影製程與—介電膜 形成製程於一各該等導體之上部上形成一介電質之介電質 形成步驟;及一移除該犧牲基板之完結製程。 本U之另1樣提供_種製造_用以測試—平面 ::之探:片之方法,包括步驟:於-犧牲基板上形成: 弟保4¾圖案,藉此界定形成複數個單元接觸組件之尖O: \ 89 \ 89662.DOC 200419159 piece forming step to fix the conductors in the trenches on the dielectric. '-Another aspect of the invention provides a method for manufacturing a probe for testing a flat panel display device, including:-a conductor forming step, which uses-a lithography process and a conductive film formation process in one A single sacrificial base of a predetermined thickness? A photoresist pattern is formed on at least one of an upper plane and a lower plane to form a conductor; a dielectric formation step is to form a photoresist pattern by using a lithography, and to open a central portion of each of these conductors, Dielectrics are formed on the open central part of each of these conductors;-Trench formation steps: It uses the -lithography and -_ process to form a trench, which exposes the lower plane of each of these conductors; The formation of the support assembly by the bereavement-support assembly in these trenches-the support assembly formation step of the branch assembly; and-the completion step of removing the sacrificial substrate. Another aspect is to provide a method for manufacturing a probe for testing a flat panel display, including: using a lithography process and the first and second # engraving processes to form a bottom with a history-rounding process The first-ditch-ditch formation step; a conductor formation step, which uses one or two passes to open the central portion of the first canals, and then embeds a conductive material in the two opening regions to form a conductor -Using a lithography process and-a dielectric film forming process to form a dielectric forming step on top of each of these conductors; and a finishing process of removing the sacrificial substrate. The other one of this U provides _ a kind of manufacturing_ for testing-plane :: exploration: a method of film, including steps: forming on a sacrificial substrate: Di Bao 4¾ pattern, thereby defining the formation of a plurality of unit contact components tip
O:\89\89662.DOC 200419159 知之區域;利用該第一保護膜圖案為_罩,藉由施卜 姓刻製程於該犧牲基板上形成渠溝;移 f:於賴第-保護膜處之該犧牲基板上形二= 4肤圖案,猎此界定形成複數個單元接觸組件之尖端之區 域;藉由在形成該第二保護膜圖案處之該犧牲基板上形成 -金屬膜而形成該單元接觸組件之光束構件;藉由移除該 第二保護臈圖案而開啟該單元接觸組件之該等光束構件. 以一預定尺寸將開啟該單元接觸組件之該等光束構件處之 =牲基板切方;將—具—職尺寸之薄膜η切方之犧 牲隸上,並附接與固定該單元接觸組件之該等光束構件 於該薄膜之該下部上·;^盤山#人 ,及猎由私除附接與固定該薄膜處之 該犧牲基板而開啟該單元接觸組件之該等尖沪 二:明之另-態樣提供一種製造一使用:二 之抹針之方法,包括··-利用—微影與一韻刻製程於該單 犧牲基板之上與下平面上形成第—渠溝之第—渠溝形成 步驟’其中該單—犧牲基板具—預定厚度,· _藉 傳導材料於該等第-渠溝中而形成導體之導體形成步驟; -利用-微影與製程於該等導體之下部上 :溝:::渠溝形成步驟;—藉由嵌入-傳導材料於該等 弟一朱溝中而形成介電質之介電質形成步驟一 介電質處之該犧牲基板之該等上與下平面之至少一平= 形成-支擇組件之支擇組件形成步驟;及—移除 板之完結步驟。 筑狂巷 本發明之另一態樣提供一種製造一使用一單一犧牲基板O: \ 89 \ 89662.DOC 200419159; use the first protective film pattern as a cover to form a trench on the sacrificial substrate by the Shi Bu engraving process; move f: at the Lai Di-protective film The shape of the second substrate = 4 skin pattern on the sacrificial substrate defines the area where the tip of the plurality of unit contact components is formed; the unit contact is formed by forming a metal film on the sacrificial substrate where the second protective film pattern is formed. The beam member of the module; opening the beam member of the unit contacting the module by removing the second protection pattern; opening the unit contacting the beam member of the module with a predetermined size = the substrate substrate; Place the sacrificial sacrifice of the film with the size of the job, and attach the beam members that are in contact with the unit to fix the unit on the lower part of the film; ^ 盘山 # 人, and hunting by private Connecting and fixing the sacrificial substrate at the film to open the sharpened parts of the unit contact assembly: The other way is to provide a method of manufacturing and using: the second method of wiping the needle, including ... Yi Yun Engraving Process on the Single Sacrifice The first channel-ditch formation step above and below the board forms the channel-ditch formation step where the single-sacrificial substrate has a predetermined thickness, and the conductor is formed by conducting materials in the first-ditch groove to form a conductor. Steps:-Utilize-lithography and process on the lower part of these conductors: trench ::: trench formation step;-forming a dielectric dielectric by embedding-conducting material in these brothers-Zhu Gully Forming step 1-at least one of the upper and lower planes of the sacrificial substrate at the dielectric = forming-selective-component-selective-component-forming step; and-finalizing step of removing the plate. Building a Mad Lane Another aspect of the present invention provides a method for manufacturing a single sacrificial substrate.
O:\89\89662.DOC 200419159 ▲朱針之方法,包括:一於該單一犧牲基板上形成一第一 保^之第—保護膜形成步驟,纟中該單-犧牲基板具一 :疋厚度’其中利用該第一保護膜圖案形成導體;一藉由 :入一傳導材料於該第一保護膜圖案中而形成上導體之上 …#形成步驟,一於形成該等導體處之該犧牲基板上形成 >第_保4膜之第1保護膜形成步驟,丨巾利用該第二保 又膜圖4成m件;_於該第二保護膜圖案中形成 一上支撐組件之上支撐形成步驟;一藉由嵌入一介電質材 料於該等渠溝中而形成-介電質之介電質形成步驟;及一 移除该犧牲基板之步驟。 ^發明之另-態樣提供—種製造—使用_單_犧牲基板 之& =之n包括:—於—該單—犧牲基板之預定部上 ^成第木溝之第一渠溝形成步驟,其中該單一犧牲基板 係由一預定材料製成,並歷經一拋光製程以具一預定厚 度’其中利用該等渠溝形成一介電質;一藉由嵌入一介; :料於該等第一渠溝中而形成該介電質之介電質形成: ‘,導體形成步驟,其係藉由在形成該介電處之該犧牲 基板之上與下平面上形成—保護膜圖t而形成導體,接著 嵌入-傳導材料於該保護膜圖案;及一移除該犧牲基板之 完結步驟。 本發明之另-態樣提供—種製造—使用—單—犧牲基板 之探:之方法,包括:一於一單一犧牲基板之—上平面之 一預定區上形成具預定深度之渠溝之渠溝形成步驟;一於 形成渠溝處之該犧牲基板上形成一第一保護膜圖案之第一O: \ 89 \ 89662.DOC 200419159 ▲ The method of Zhu needle includes: forming a first protective film-forming step on the single sacrificial substrate, wherein the single-sacrificial substrate has a thickness of: 'Where the first protective film pattern is used to form a conductor; a conductive material is formed on the first protective film pattern to form an upper conductor ... # forming step, a sacrificial substrate where the conductors are formed Forming the first protective film forming step of the fourth protective film, using the second protective film to form 4 pieces; and forming an upper supporting component on the second protective film pattern to support and form Step; a dielectric forming step of forming a dielectric by embedding a dielectric material in the trenches; and a step of removing the sacrificial substrate. ^ Another invention-provide-manufacturing-use_single_sacrifice substrate & = n includes: -on-the single-sacrificial substrate predetermined portion ^ forming a first trench formation step Wherein, the single sacrificial substrate is made of a predetermined material and undergoes a polishing process to have a predetermined thickness, wherein a dielectric is formed by using the trenches; one is embedded by a dielectric; it is expected that the first Dielectric formation of the dielectric in the trench: 'Conductor formation step, which forms a conductor by forming a protective film pattern t above and below the sacrificial substrate where the dielectric is formed , Then embedding-conducting material in the protective film pattern; and a finishing step of removing the sacrificial substrate. According to another aspect of the present invention, a method for manufacturing-using-single-sacrifice substrate is provided. The method includes: forming a trench with a predetermined depth on a predetermined area of an upper plane of a single sacrificial substrate. A trench forming step; a first forming a first protective film pattern on the sacrificial substrate where the trench is formed
O:\89\89662.DOC -12- 200419159 保護膜形成步驟,藉此開啟該等渠、、籌·一山 材料於該第-保護膜圖案開啟二=== 驟,其中藉由—㈣製程移除該等渠溝埋乂 :微影製程於該犧牲基板之上與下平面上形成—第二保= :之第二保護膜圖案形成步驟,#中利用該第二保護二 ^形成導體;—於該第二保護膜圖案所界定之特定位置〆 :成導體之導體形成步驟;一於形成該等導體處之: 基板之該等上與下平面上形成一第三保護膜圖案之 護膜圖案形成步驟,其中利用該第三保 去、 撑組件;-於該第三保護膜圖案所界定之特定位::形: 一支撐組件之支撐組件形成步驟;及一移除部分為該渠溝 埋入材料分隔之犧牲基板並接著移除該渠溝埋人材料之* 結步驟。 70 【實施方式】 在本發明中係指”探 在本發明之說明書中,注意,,探針,, 針結構π。 百先,在詳述依本發明之用以測試平面板顯示器之探針 之具體實施例前,先將描述探針之概念性構造。 如圖la至lc與圖2a至2c中所示,類板狀介電質1〇係由介 兒材料如陶瓷製成。介電質1 〇厚240微米較佳。此外,介電 貝10兩鳊具步階差外型或傾斜外型較佳。再者,由於介電 質1〇具有維持探針外型與絕緣功能,故介電質係由硬質材 料製成較佳。 由鎳(Ni)或鎳合金製成之導體2(^與2〇13具桿狀外型,其兩O: \ 89 \ 89662.DOC -12- 200419159 The protective film formation step is used to open the channels, chips, and mountains. The second protective film pattern is turned on. Remove the trenches: a lithography process is formed on the sacrificial substrate and on the lower plane-the second protection step: a second protection film pattern forming step, and the second protection layer is used to form a conductor in #; -At a specific position defined by the second protective film pattern: a step of forming a conductor into a conductor; one where the conductors are formed: a protective film with a third protective film pattern formed on the upper and lower planes of the substrate A pattern forming step in which the third retaining and supporting component is used;-at a specific position defined by the third protective film pattern :: shape: a supporting component forming step; and a removed portion is the trench The sacrificial substrate separated by the buried material is then buried in the trench. 70 [Embodiment] In the present invention means "probing in the description of the present invention, note that the probe, the pin structure π. Baixian, in detail the probe used to test the flat panel display according to the present invention Before the specific embodiment, the conceptual structure of the probe will be described first. As shown in FIGS. 1a to 1c and FIGS. 2a to 2c, the plate-like dielectric 10 is made of a dielectric material such as ceramic. 10 thickness 240 microns is preferred. In addition, the dielectric shell 10 has a stepped shape or a slanted shape. Furthermore, because the dielectric 10 has the function of maintaining the shape and insulation of the probe, the dielectric The electric substance is preferably made of a hard material. The conductor 2 (^ and 201) has a rod-like shape made of nickel (Ni) or a nickel alloy.
0:\89\89662.D〇C -13- 200419159 末端部具尖銳外型。 有不同的製造依本具體實施例之導體之方法。在第一具 體只知例中,導體插入處之渠溝係利用切方蘇齒製程开^ 成’具尖銳末端部之導體附接並固定於各渠溝中,藉以使 得導體位於介電質10上。 在第一具體實施例中,導體位置與大小係視微影製程而 疋,並以預定間隔位於介電質之上下平面之至少一平面上。 導體20a與20b分別與介電質10之上下平面相接。雖然兩 列導體係分別於介電質之上下平面上形成,但亦可使一列 導體位於介電質10内。 此外,在一列導體位於介電質内之情況下,形成單層探 針,示如圖2a至2c。 由於係自探針上部觀察探針,故置放導體2〇a與2〇b使得 在介電質10之上平面上之導體2〇a位於介電質1〇之下平面 之相鄰導體20b間。 此外,在介電質10之上平面上之各導體2〇a長度均與在介 電質10之下平面上之各導體鳥相同,自介電㈣向外突出 之導體20a與20b之左右突出部之長度均同。 /口圖lc所示,在介電質10之上平面上之導體施之末端部 較在介電質10之下平面上之導體鳥之末端部突出。特別古 之,導體遍與鳥之形成使得連結介電質10之上平面上之 導體20a之末端部與介電質 私貝之下千面上之導體20b之末端 部之線u相對於各導體表面具30。至60。夹角較佳。所採用之 導體20a與20b之製造厚度為60士5微米。0: \ 89 \ 89662.D〇C -13- 200419159 The tip has a sharp shape. There are different methods of manufacturing a conductor according to this embodiment. In the first specific example, the trenches at the conductor insertion points are formed using a tangent spur toothing process to form and attach the conductors with sharp ends to the trenches, so that the conductors are located in the dielectric 10 on. In the first specific embodiment, the position and size of the conductor are determined by the lithography process, and are located on at least one plane above and below the dielectric at predetermined intervals. The conductors 20a and 20b are in contact with the upper and lower planes of the dielectric 10, respectively. Although two rows of conductive systems are formed on the dielectric substrate above and below, respectively, a row of conductors may be located within the dielectric 10. In addition, a single-layer probe is formed when a row of conductors are located within the dielectric, as shown in Figures 2a to 2c. Since the probe is viewed from the top of the probe, the conductors 20a and 20b are placed so that the conductor 20a on the plane above the dielectric 10 is located adjacent to the conductor 20b on the plane below the dielectric 10. between. In addition, the length of each conductor 20a on the plane above the dielectric 10 is the same as that of each bird on the plane below the dielectric 10, and the conductors 20a and 20b protruding outward from the dielectric ridge protrude to the left and right. The lengths of the parts are the same. As shown in FIG. 1c, the terminal portion of the conductor on the plane above the dielectric 10 is more prominent than the terminal portion of the conductor bird on the plane below the dielectric 10. In particular, the formation of the conductor loop and the bird made the line u connecting the end portion of the conductor 20a on the plane above the dielectric 10 and the end portion of the conductor 20b on the thousandth plane below the dielectric layer relative to each conductor. Surface with 30. To 60. The included angle is better. The thickness of the conductors 20a and 20b used is 60 ± 5 microns.
O:\89\89662.DOC -14- 200419159 如後述,在製造具有在介電質1〇上之導體2〇a與2〇b之用 以測試平面板顯示器之探針之方法之主要具體實施例有 二。第一具體實施例係利用切方鋸齒製程製造探針之方 法,第二具體實施利澤係利用MEMS製程製造探針之方法。 在採用MEMS製程之情況下,可於導體2〇a與2仙表面上形 成V私率車又V體佳之薄導體材料4〇a與4〇b。傳導材料係以 鍍金層形成較佳。形成傳導材料4〇a與4〇b以改善各導體 傳導率。 ^ 此外’並具有以環氧化物、陶瓷板,或環氧化物與陶瓷 板之組成形成之支撐組件30a與3〇b。支撐組件與導體2〇a與 20b之上部相接,俾強化導體20a與20b支擇。 再者,本發明另揭示單層探針與雙層探針。如圖h與以 所不,單層探針包括具預定尺寸之類板狀介電質肋;以特 定間隔平行穿透介電質之複數個導體5〇 ;以及與介電質肋 之上下平面之一相接之類板狀支撐組件6〇。 在採用MEMS製程之情況下,可於單層探針中之各導體 5〇之一平面上形成具優良導電率之傳導材料。該傳導材料 為金,藉以形成鍍金層70較佳。 單層探針與雙層探針之部件相同,且部件之功能相同 因此,茲不贅述。 (第一具體實施例) 依第一具體實施例,利用切方鋸齒製程在由硬質材料製 程之矩形強化板上形成渠溝(縫)並將導體插 衣 ^ 丹固疋於該 等渠溝中而製造用以測試平面板顯示器之探 ^ 精以使得 O:\89\89662.DOC -15- 200419159 導體充作用以測試平面板顯示器之針。 現將參閱圖3至5描述第一具體實施例。 、,圖3a至3e係闡釋依本發明之第—具體實施例之用以測試 平面板顯示器之探針之透視圖’以及用以闡釋製造該探針 之方法之流程圖。 、在依本發明之用卩測試平面板顯示器之探針及其製造方 =中如®|3a所7F ’所製備之支撐板9()為矩形板狀。該支 撐板係由硬質材料如陶兗製成。由於中央槽93係在支樓板 平面之側至其相對側之縱向方向中形成,因此得 以於支推板90之上平面上形成彼此相對之第一突出區㈣ 第二突出區95。 ρχ, ▼ ^㈣a頌⑽%狀。 接著士圖3b所tf,利用切方鑛齒製程分別於支撐板 =一與第二突出區91與95之上表面上形成複數個針狀. 與9几。該等複數個渠溝97a與97b均連結於中央槽93 此外,分別於第一盥第—$ + p Q1 曰 盥·… ”弟-大出£91與95上形成之渠溝9: _均具相通間隔,俾使彼此相對,如圖〜所示 ==渠溝可“在第__突出區91上形成之渠溝97& Π:: — 95上形成一則她 特別σ之,就渠溝97a盘97b深声而a 土 渠溝與中央槽93水… §,較佳係所形成之 冰’俾得以視中央槽93平 天 導體之平坦度。 千度心在渠溝%物b中之O: \ 89 \ 89662.DOC -14- 200419159 As will be described later, the main specific implementation of the method for manufacturing a probe for testing a flat panel display having conductors 20a and 20b on a dielectric 10 There are two examples. The first embodiment is a method for manufacturing a probe using a tangential sawtooth process, and the second embodiment is a method for manufacturing a probe using a MEMS process. In the case of the MEMS process, the thin conductor materials 40a and 40b with good V-body ratio and good body can be formed on the surfaces of the conductors 20a and 2 cents. The conductive material is preferably formed by a gold plating layer. The conductive materials 40a and 40b are formed to improve the conductivity of each conductor. ^ In addition, it also has support members 30a and 30b formed of epoxide, ceramic plate, or a combination of epoxide and ceramic plate. The supporting components are connected to the upper portions of the conductors 20a and 20b, and the reinforced conductors 20a and 20b are selected. Furthermore, the present invention also discloses single-layer probes and double-layer probes. As shown in Figure h and above, a single-layer probe includes a plate-shaped dielectric rib having a predetermined size or the like; a plurality of conductors 50 which penetrate the dielectric in parallel at a specific interval; and the upper and lower planes of the dielectric rib One of the plate-like supporting components 60 is connected. In the case of the MEMS process, a conductive material with excellent conductivity can be formed on a plane of each conductor 50 in a single-layer probe. The conductive material is gold, so that the gold-plated layer 70 is preferably formed. The components of the single-layer probe and the double-layer probe are the same, and the functions of the components are the same. (First specific embodiment) According to the first specific embodiment, trenches (slots) are formed on a rectangular reinforced plate made of a hard material using a tangent sawtooth process, and a conductor is inserted into the trenches. The probe manufactured to test the flat panel display is refined so that the O: \ 89 \ 89662.DOC -15- 200419159 conductor is used to test the pin of the flat panel display. A first specific embodiment will now be described with reference to FIGS. 3 to 5. 3a to 3e are perspective views illustrating a probe for testing a flat panel display according to the first embodiment of the present invention, and a flowchart for explaining a method of manufacturing the probe. In the probe for testing a flat panel display and its manufacturing method according to the present invention, the support plate 9 () prepared by Zhongru® | 3a 7F 'is a rectangular plate. The support plate is made of a hard material such as pottery. Since the central groove 93 is formed in the longitudinal direction from the side of the plane of the supporting floor to its opposite side, a first projecting area ㈣ a second projecting area 95 opposite to each other is formed on the plane above the supporting plate 90. ρχ, ▼ ^ ㈣a⑽⑽% 状。 Following tf shown in Figure 3b, a plurality of needle-like shapes are formed on the upper surface of the support plate = one and the second protruding areas 91 and 95 using the tangent tooth process. The plurality of trenches 97a and 97b are connected to the central groove 93. In addition, the trenches formed on the first toilet— $ + p Q1 are called toilets… ”Brother-Da out £ 91 and 95 9: _ 均There are communication intervals, so that they are opposite to each other, as shown in the figure. == The trench can be formed on the __th protruding area 91. The trench 97 & 97a disk 97b deep sound while a earth canal and central groove 93 water ... §, it is better to form the ice '俾 to see the flatness of the central groove 93 flat sky conductor. Thousand degrees of heart in the trench
O:\89\89662.DOC -16- 200419159 而後如圖3d所示,具預定長度與預定直徑之導體98均具 大銳狀末端部,並分別位於在支撐板90之第一突出區91 與第二突出區95上形成之渠溝97a與97b中。 。體98均具自支撑板90向外突出之預定長度,使得各 導體之一末端部可充作接觸組件,以直接與平面板顯示器 之測試處相接,另一末端部則可充作連結組件。導體98係 由鎢或鎢合金製成。 如圖3e所示,於支撐板9〇上方用以插入針或導體(針)98 於第一與第二突出區91與95上形成之渠溝97a與97b中處施 加黏著劑,接著施加黏著劑如環氧化物並固化以附接於支 樓板上之導體上,藉以製造探針。 現將參閱圖4與5描述參閱圖3所述探針之製造方法之具 體實施例。 圖4a與仙係闡釋依本發明之另一具體實施例之用以測試 平面板顯示器之探針及其製造方法之透視圖。 在依本發明之具體實施例之用以測試平面板顯示器之探 針及其製造方法中,如圖4a所示,上方形成次級探針之另 一支撐板100係在第一具體實施例中之支撐板9〇上方。此處 之支撐板100與支樓板90之製造方法相同。 位於上部處之探針稱之為上探針,其與第一具體實施例 中稱之為下探針之探針製造方法相同。亦即在第一突出區 101上形成之渠溝107a連結於中央槽103,且位於渠溝1〇7a 中之導體108係以黏著劑如環氧化物1〇9附接與固定。此 外,另-渠溝係於第二突出區1〇5上形成,但圖乜中並未顯 O:\89\89662.DOC -17- 200419159 不 ο 接著如圖4b所示,利用黏著劑如環氧化物(未圖 下探針使之相互重疊。 α 所形成之上探針之導體⑽(而後有時稱之為上導體声下 棟針之導體98(而後有時稱之為下導體)交替配置。各上探針 之導體1〇8之一末端部較對應之各導體⑽之末端部向外突 出較多。上下導體之向外突出部總長相同,使得上下導體 具相同物理條件。各導體108與98之一末端部係充作直接與 平面板顯不器之測試處相接之接觸組件,另一末端部則充 作連結組件。 ° 、 雖然在具體實施例中所述係雙層探針,應知可依製造商 意向製造三或更多層探針。 此外,亦可依製造商意向選擇決定上下探針之附接處。 因此,可直接附接與固定上探針之支撐板1〇〇於下探針之支 撐板90上。 圖5a係闡釋依本發明之另一具體實施例之用以測試平面 板顯示器之探針及其製造方法之透視圖;圖^則係圖^之 剖面圖。 在依本發明之另一具體實施例之用以測試平面板顯示器 之探針及其製造方法中,如圖化與51)所示,於支撐板卯之 下平面上施行下列製成。亦即與第一具體實施例類似,形 成中央槽112、第一突出區11〇與第二突出區114之製程;形 成第知溝116a與第二渠溝(未示於圖5a)之製程;以及形成 牙透第一渠溝116a、第二渠溝(未圖示)與中央槽Η]之下導O: \ 89 \ 89662.DOC -16- 200419159 and then as shown in FIG. 3d, the conductors 98 having a predetermined length and a predetermined diameter have sharpened ends and are located in the first protruding areas 91 and 91 of the support plate 90, respectively. In the trenches 97a and 97b formed in the second protruding region 95. . The body 98 has a predetermined length protruding outward from the support plate 90, so that one end portion of each conductor can be used as a contact component to directly connect with the test portion of the flat panel display, and the other end portion can be used as a connection component. . The conductor 98 is made of tungsten or a tungsten alloy. As shown in FIG. 3e, a pin or a conductor (pin) 98 is inserted above the support plate 90, and an adhesive is applied to the middle of the trenches 97a and 97b formed on the first and second protruding areas 91 and 95, and then the adhesive is applied. Agents such as epoxide and cured to attach to conductors on the supporting floor, thereby making the probe. A specific embodiment of the method of manufacturing the probe described with reference to FIG. 3 will now be described with reference to FIGS. 4 and 5. Fig. 4a and the fairy are perspective views illustrating a probe for testing a flat panel display and a manufacturing method thereof according to another embodiment of the present invention. In a probe for testing a flat panel display and a manufacturing method thereof according to a specific embodiment of the present invention, as shown in FIG. 4a, another support plate 100 forming a secondary probe above is in the first specific embodiment. Above the support plate 90. Here, the manufacturing method of the supporting plate 100 and the supporting floor plate 90 is the same. The probe located at the upper part is called the upper probe, which is the same as the method for manufacturing the probe called the lower probe in the first embodiment. That is, the trench 107a formed on the first protruding region 101 is connected to the central groove 103, and the conductor 108 located in the trench 107a is attached and fixed with an adhesive such as epoxy 1009. In addition, another trench is formed on the second protruding area 105, but O: \ 89 \ 89662.DOC -17- 200419159 is not shown in the figure. Then, as shown in FIG. 4b, using an adhesive such as Epoxide (the probes are not shown in the figure, they overlap each other. Α is the conductor ⑽ of the upper probe (sometimes sometimes referred to as the upper conductor and the lower conductor 98 (and sometimes the lower conductor)) Alternately arranged. One end of the conductor 108 of each upper probe protrudes more outward than the end of the corresponding conductor ⑽. The total length of the outward protrusions of the upper and lower conductors is the same, so that the upper and lower conductors have the same physical conditions. One of the ends of the conductors 108 and 98 is used as a contact component directly connected to the test place of the flat panel display, and the other end is used as a connection component. °, Although described in the specific embodiment is a double layer Probes, it should be known that three or more layers of probes can be manufactured according to the manufacturer's intention. In addition, the attachment of the upper and lower probes can also be determined according to the manufacturer's intention. Therefore, the support of the probe can be directly attached and fixed. The plate 100 is on the support plate 90 of the lower probe. Figure 5a illustrates the invention A perspective view of a probe for testing a flat panel display and a manufacturing method thereof according to another embodiment; FIG. ^ Is a sectional view of FIG. ^. In another embodiment of the present invention, it is used to test a flat panel display. In the probe and its manufacturing method, as shown in Figure 51 and 51), the following fabrication is performed on the plane below the support plate 卯. That is, similar to the first embodiment, a central groove 112 and a first protruding region are formed. Process of forming 110 and the second protruding region 114; process of forming the first trench 116a and the second trench (not shown in FIG. 5a); and forming the first trench 116a and the second trench (not shown) And central stables]
O:\89\89662.DOC -18- 200419159 體118(具預定長度)之製程,藉以使得兩末端部向外突出, 二進v於支撐板之下平面上施行利用黏著劑如環氧化物 而為之附接與固定下導體丨18於支撐板9〇之下平面之製程。 所形成之在支撐板90之上平面上之導體98與在支撐板90 =下平面上之導體118呈鉛直交替。在支撐板之上平面上之 導體98之一末端部較在支撐板之下平面上之各導體118之 對應末端部更為向外突出。上導體98與下導體118之向外突 出部總長相同。 (第二具體實施例) ^弟二具體實施例係利用MEMS製程製造探針之方法。在 榣述衣y木針方法之特殊範例前,將先描述製造探針方法 中之共通步驟。 /犧牲基板製備步驟中’所製備之犧牲基板具有石夕(s] 曰日圓或由陶曼材料製成之 度為彻心〇㈣。 之犧牲基板較佳』 =在介電質形成步驟中’利用蝕刻製程於犧牲基… 下平面之預定區上形成渠溝。並 模於準、、叠由 — T "电貝插入或產 陶究二二Γ於犧牲基板上形成介電質。介電質… 是衣乳化物等。換言之,於渠溝中施、 在環氧化物固化前,將盘各m 士 …匕物’ i 相同之預製 附接於乐溝中,藉以形成介電 溝大小相同之箱制h > 、次者,可將與各! 舆陶宪板人’接著施加環氧化物於渠; 電質。U.、中’因而附接渠溝與陶竟板,藉以形成1O: \ 89 \ 89662.DOC -18- 200419159 Body 118 (with a predetermined length), so that the two end portions protrude outward. Binary v is performed on the plane below the support plate using an adhesive such as epoxy. The process of attaching and fixing the lower conductor 18 to the plane below the support plate 90. The conductors 98 formed on the plane above the support plate 90 and the conductors 118 on the plane below the support plate 90 alternate vertically. One end portion of the conductor 98 on the plane above the support plate projects more outwardly than the corresponding end portion of each conductor 118 on the plane below the support plate. The total length of the outward protrusions of the upper conductor 98 and the lower conductor 118 is the same. (Second Specific Embodiment) The second specific embodiment is a method for manufacturing a probe using a MEMS process. Before describing a special example of the clothing needle method, common steps in the method of manufacturing a probe will be described. / In the sacrificial substrate preparation step, the prepared sacrificial substrate has Shi Xi (s), said Yen or made of Taumann material. The sacrificial substrate is as thorough as possible. The sacrificial substrate is preferably "= in the dielectric formation step" An etching process is used to form a trench on a predetermined area on the sacrificial substrate ... and it is formed in a quasi-orthogonal shape—T " Electro-shell insertion or production of ceramics Γ to form a dielectric on the sacrificial substrate. Dielectric The quality ... is the emulsion of the clothes, etc. In other words, it is applied in the trench, and before the epoxide is solidified, the same pre-attachment is made in the trench to form the same dielectric trench. The box system h > and the second, can be combined with each other! You Taoxian Banren 'then apply epoxide to the channel; the electric mass. U., Zhong' thus attached the trench and the Tao Jingban to form 1
O:\89\89662.DOC -19- 200419159 雖然陶瓷板為矩形平行六面體,但其亦可為平行四邊形 或步階形,如圖21a與21b所示。 ’ 蝕刻犧牲基板之上下平面之預定部之製程包含切方製程 與乾钮刻製程,其中利用光阻形成之保護膜圖案敍刻= 基板。 此處在以陶究作為犧牲基板之情況下’由於犧牲基板本 身即係介電質,故於犧牲基板之上部上形成介電質之製程 可略之。 接著在導體形成步驟中,於犧牲基板之上下平面上形成 與導體外型相同之圖案,接著精確利用這些圖案於各處形 成導體。導體係由鎳(Ni)或鎳合金製成較佳。 首先’利用光阻於犧牲基板上之精確位置處(形成導體處) 形成與導體形狀相同之圖案。接著利料些圖帛,以電解 貝电鐘法开> 成導體。結果使得依本發明之探針在介電質之 上下平面上之上了導體之配置間㉟、位置與間距上具二優 良精確性與再造性,故與人卫施行接合製程之情況相較^ 得以降低產生故障率。 由於導體係以電鑛製程形成,故在電鑛製程前,需於犧 牲基板表面形成種層,以利施行電鍍製程。此處之種層可 利用濺鐘法形成。此外,種層係以鈦㈤與銅(cu)製^較 佳。鈦層具有提昇犧牲基板與銅層間黏著性之功能,銅層 則可充作後續電鍍製程中之電鍍種層用。 此外’導體係由鎳(Ni)或鎳合金製成。 在支撐組件形成步驟中,將支撑組件附接與鑄模於犧牲O: \ 89 \ 89662.DOC -19- 200419159 Although the ceramic plate is a rectangular parallelepiped, it can also be a parallelogram or step shape, as shown in Figures 21a and 21b. The process of etching the predetermined portion of the upper and lower planes of the sacrificial substrate includes a tangent process and a dry button engraving process, in which a protective film pattern formed using photoresist is etched = a substrate. In the case where ceramics is used as the sacrificial substrate here, since the sacrificial substrate itself is a dielectric, the process of forming a dielectric on the upper portion of the sacrificial substrate can be omitted. Next, in the conductor forming step, the same pattern as the shape of the conductor is formed on the upper and lower planes of the sacrificial substrate, and then these patterns are accurately used to form the conductor everywhere. The guide system is preferably made of nickel (Ni) or a nickel alloy. First, a photoresist is used to form a pattern having the same shape as the conductor at a precise position on the sacrificial substrate (where the conductor is formed). Then draw some pictures and use the electrolytic clock method to turn them into conductors. As a result, the probe according to the present invention has excellent accuracy and reproducibility in the arrangement, position, and spacing of the conductors on the dielectric substrate above and below the plane. Therefore, it is compared with the case where the bonding process is performed by human health ^ This reduces the failure rate. Since the guide system is formed by an electric ore process, a seed layer needs to be formed on the surface of the sacrificial substrate before the electric ore process to facilitate the electroplating process. Here, the seed layer can be formed by a sputtering method. In addition, the seed layer is preferably made of titanium hafnium and copper (cu) ^. The titanium layer has the function of improving the adhesion between the sacrificial substrate and the copper layer, and the copper layer can be used as a plating seed layer in the subsequent plating process. In addition, the guide system is made of nickel (Ni) or a nickel alloy. At the support assembly forming step, attach and mold the support assembly to the sacrificial
O:\89\89662.DOC -20- 基板上欲形成導體處。支標組件係 成。特別+夕+ „ 衣氧化物或陶瓷製 寺別巨之,在每氧化物固化前,預先施加環氧 於其上附接陶瓷板即可獲得較佳支撐組件。 換言之,利用光阻形成支撐組件 # Η ^ φ ^ ^ 茶亚接者於支撐組 件:案中把加支撐材料,藉以形成支撐組件。 ,ΓΓ ’ ί完結步驟中,利用難刻製程移除犧牲基板之 歹欠餘部,藉以得出探針。 =一方面而言’在利用硬質材料如陶t作為犧牲基板 ^月况下’製造探針之方法包括槽形成步驟,其係於介電 貝材料製之單一犧牲基板之上下平面之預定部形成具預定 殊度之槽,所形成之預定厚度係利用拋光製程為之;介電 質形成補充卫具形成步驟,其係藉由形成用以於犧牲基板 ^開啟槽之保護膜圖案並將金屬材料嵌人槽中而形成介電 貝幵/成補充工具中金屬材料係可利用濕蚀刻製程選擇 性移除之材料;導體形成步驟,其係於犧牲基板上形成與 導體外型㈣之保護膜㈣並接著㈣這翻案於精確位 置處形成導體而為之;支樓組件形成步驟,其係於犧牲基 板之上下平面上欲形成導體處形成支揮組件;以及將介電 質形成補充工具自犧牲基板移出之步驟。 此處之硬質材料包含陶瓷、玻璃等。 現將筝閱隧附圖式描述用以測試平面板顯示器之探針構 造及其製造方法。 (具體實施例2-1) 圖6a至6p係闡釋依另一具體實施例製造用以測試平面板O: \ 89 \ 89662.DOC -20- Where a conductor is to be formed on the substrate. The support component is made up. Special + evening + „Clothing oxide or ceramic temples are huge. Before each oxide is cured, epoxy is pre-applied to attach a ceramic plate to obtain a better support component. In other words, a photoresist is used to form a support component. # Η ^ φ ^ ^ Chaya connected to the supporting component: the supporting material was added in the case to form the supporting component., ΓΓ 'ί In the end step, use a difficult process to remove the remaining part of the sacrificial substrate to obtain Probe. = On the one hand, the method of manufacturing a probe 'in the case of using a hard material such as ceramic t as a sacrificial substrate ^ includes a groove forming step, which is formed on the upper and lower planes of a single sacrificial substrate made of dielectric shell material. The predetermined portion is formed with a groove having a predetermined degree, and the predetermined thickness is formed by a polishing process; the dielectric material is formed to supplement the guard formation step by forming a protective film pattern for opening the groove on the sacrificial substrate ^ and The metal material is embedded in the trench to form a dielectric shell. The metal material in the supplementary tool is a material that can be selectively removed by a wet etching process. The conductor forming step is performed on a sacrificial substrate to form a substrate. The protective film of the external type is then formed to form a conductor at a precise position; the step of forming a branch component is to form a branch component on the sacrificial substrate above and below the surface where the conductor is to be formed; and The step of removing the quality forming supplementary tool from the sacrificial substrate. The hard materials here include ceramics, glass, etc. The structure of the probe used to test the flat panel display and its manufacturing method will be described in the following drawings. (Specific embodiments 2-1) Figures 6a to 6p illustrate a test method for manufacturing a flat panel according to another embodiment.
O:\89\89662.DOC -21- 200419159 顯示器之探針之方法之剖面圖。 在依參閱圖6a至6p所述之具體實施例中之製造探針之方 法中,導體及對齊鍵係位於犧牲基板之上平面上,以利於 利用對齊鍵在其下平面上施行製程。如圖6a所示,在利用 沉積製程如濺鍍製程於矽等材料製之犧牲基板12〇上形成 之種層126具騎厚度,接著於種層126域佈充作保護膜 之具預定厚度之第一光阻丨28。 所建構之種層126具有厚500埃之鈦層122與厚5,〇〇〇埃之 銅層124。銅層124實質上係充作後續電鍍製程中之種層 126。鈦層122則係用以改善犧牲基板12〇與銅層124之黏著 性。 < 接著如圖6b所示,形成第一光阻圖案129以界定用以形成 導體之預定區,以及在後續製程中之對齊鍵。各導體均係 與所測試之平面板顯示器直接相接之接觸組件。 可利用其上設計有預定電路圖案之罩,藉由在犧牲基板 上形成之第一光阻128之曝光形成第一光阻圖案129,俾 形成導體與對齊鍵,接著顯影之。 、而後如圖6c所不’ w用電鑛製程沉積傳導材料如錄⑼) 或鎳合金(Nmw-Co)於犧牲基板12〇上有第一光阻圖 案129形成處而形成傳導膜131。接著利用平坦化製程使犧 牲基板120之上平面平坦化。 利用化學機械抛光(CMP)法及研磨法等施行平坦化製 程ϋ彡成傳導膜131之電”程期間’在種層126中之銅 層124係充作電鍍材料之來源。O: \ 89 \ 89662.DOC -21- 200419159 Sectional view of the method for the probe of the display. In the method for manufacturing a probe in the specific embodiment described with reference to Figs. 6a to 6p, the conductor and the alignment key are located on the plane above the sacrificial substrate, so as to facilitate the process on the lower plane using the alignment key. As shown in FIG. 6a, a seed layer 126 is formed on a sacrificial substrate 12 made of silicon or the like by a deposition process such as a sputtering process, and then the seed layer 126 is used as a protective film with a predetermined thickness. First photoresist 28. The seed layer 126 is constructed to have a titanium layer 122 having a thickness of 500 angstroms and a copper layer 124 having a thickness of 5,000 angstroms. The copper layer 124 is substantially used as a seed layer 126 in a subsequent electroplating process. The titanium layer 122 is used to improve the adhesion between the sacrificial substrate 120 and the copper layer 124. < As shown in FIG. 6b, a first photoresist pattern 129 is formed to define a predetermined area for forming a conductor, and an alignment key in a subsequent process. Each conductor is a contact component that is in direct contact with the flat panel display being tested. A first photoresist pattern 129 can be formed by exposing a first photoresist 128 formed on a sacrificial substrate by using a cover having a predetermined circuit pattern formed thereon, and forming a conductor and an alignment key, and then developing it. Then, as shown in FIG. 6c, a conductive material such as a recording material or a nickel alloy (Nmw-Co) is deposited on the sacrificial substrate 12 with a first photoresist pattern 129 on the sacrificial substrate 12 to form a conductive film 131 as shown in FIG. 6c. Then, a planarization process is used to planarize the plane above the sacrificial substrate 120. The copper layer 124 in the seed layer 126 is used as a source of the electroplating material during the electrical "process" of the conductive film 131 by the planarization process using a chemical mechanical polishing (CMP) method and a polishing method.
O:\89\89662.DOC -22- 200419159 特別言之,在用以形成傳導膜131之理想電鍍製程之進程 中,僅於第一光阻圖案129之開啟部内形成傳導膜131之情 況下,平坦化製程可略之。 此外,在利用除電鑛製程外之方法如物理汽相沉積(pvd) 與化學汽相沉積(CVD)形成傳導膜i 3丨之情況下,先前形成 種層126之製程可略之。 接著如圖6d所示,藉由移除第一光阻圖案129使得部分銅 層124曝光,藉以形成導體及對齊鍵132&與13孔。可以方法 如使用化學物之濕钱刻製程或乾钱刻製程移除第一光阻圖 案 129 〇 接著如圖6e所示,在使用化學物之濕蝕刻製程中,利用 導體130及對齊鍵132&與1321)為罩,藉由移除第一光阻圖案 129使得由鈦層122與銅層124構成之種層126曝光而移除 之,藉以使得導體130及對齊鍵132&與13213完全暴露在外。 接著如圖6f所示,塗佈一定數量之第二光阻134於犧牲基 板120上導體13〇及對齊鍵132&與1321)完全暴露在外處。 雖然在此係塗佈固接於旋轉吸盤上之犧牲基板12〇,但第 二光阻134係經一噴嘴喷灑於犧牲基板12〇上,故得以塗佈 一定數量之第二光阻134。 接著如圖6g所示,將具有預定電路圖案之罩置於犧牲基 板120上塗佈第二光阻134處,接著將之曝光與顯影,藉以 形成完全開啟之導體130之中央部與對齊鍵13。與13^之 第二光阻圖案136。 接著如圖6h所示,以介電材料如環氧化物封閉導體O: \ 89 \ 89662.DOC -22- 200419159 In particular, in the course of the ideal plating process for forming the conductive film 131, only when the conductive film 131 is formed in the opening portion of the first photoresist pattern 129, The planarization process can be omitted. In addition, in a case where the conductive film i 3 丨 is formed using a method other than a power ore process such as physical vapor deposition (pvd) and chemical vapor deposition (CVD), the previous process of forming the seed layer 126 can be omitted. Next, as shown in FIG. 6d, a portion of the copper layer 124 is exposed by removing the first photoresist pattern 129, thereby forming a conductor and alignment keys 132 & and 13 holes. The first photoresist pattern 129 can be removed by a method such as a wet money engraving process or a dry money engraving process using a chemical. Then, as shown in FIG. 6e, in the wet etching process using a chemical, the conductor 130 and the alignment key 132 are used. And 1321) as a cover, which is removed by exposing the first photoresist pattern 129 to expose the seed layer 126 composed of the titanium layer 122 and the copper layer 124, so that the conductor 130 and the alignment keys 132 & and 13213 are completely exposed. . Next, as shown in FIG. 6f, a certain amount of the second photoresist 134 is coated on the conductor 130 and the alignment keys 132 & and 1321) on the sacrificial substrate 120 to be completely exposed. Although the sacrificial substrate 120 is fixed and fixed on the rotary chuck here, the second photoresist 134 is sprayed on the sacrificial substrate 120 through a nozzle, so a certain amount of the second photoresist 134 can be applied. Next, as shown in FIG. 6g, a mask having a predetermined circuit pattern is placed on the sacrificial substrate 120 to apply a second photoresist 134, and then exposed and developed to form a fully opened conductor 130 and the alignment key 13 . And 13 ^ 的 第二 光阻 平面 136. Next, as shown in Figure 6h, the conductor is closed with a dielectric material such as an epoxide.
O:\89\89662.DOC -23- 200419159 之中央部(隨第二光阻圖案136而完全開啟)而形成支撐板 138 〇 在此可利用印刷法等形成充作支撐板138之環氧化物。 接著如圖6i所示,以研磨製程將犧牲基板之上平面中完 王為介電質材料如環氧化物製之支撐板138封閉之導體之 中央部平坦化。 在此施行研磨製程以利後續在犧牲基板12 0背平面上施 行之研磨製程。 接著如圖6j所示,犧牲基板12〇面朝下,並研磨犧牲基板 120之月平面至預定厚度,藉以調整在後續渠溝形成製程 中,犧牲基板120之蝕刻深度於低高度。 接著如圖6k所不,塗佈預定厚度之第三光阻14〇於被研磨 至預定厚度之犧牲基板120之背平面上。 ♦之第—光阻14〇塗佈法與第一及第二光阻128及I” 相同。 接著如Η 61所不,以上具特定電路圖案之罩將第三光阻 、4〇曝光亚接著顯影,藉此形成用以開啟犧牲基板之背 平面之中央部之第三光阻圖案142。 ”接著如圖6m所示,利用第三光阻圖案142為罩,施行蝕刻 製私’俾完全則種層126,藉以形成用以開啟犧牲基板120 之渠溝14 4。 此處之钮刻1程係使用具特定比例之sf6、c4m〇2之混 合氣體之乾蝕刻製程。 更特別言之,係㈣所謂的波許(Bosh)製㈣行姓刻製O: \ 89 \ 89662.DOC -23- 200419159 (supported completely with the second photoresist pattern 136) to form the support plate 138. Here, an epoxide used as the support plate 138 can be formed by printing or the like . Next, as shown in FIG. 6i, the central portion of the conductor closed by the dielectric plate such as the support plate 138 made of an epoxy material is flattened in the plane above the sacrificial substrate by a grinding process. A grinding process is performed here to facilitate subsequent grinding processes performed on the sacrificial substrate 120 back plane. Next, as shown in FIG. 6j, the sacrificial substrate 120 faces downward, and the moon plane of the sacrificial substrate 120 is polished to a predetermined thickness, so as to adjust the etching depth of the sacrificial substrate 120 to a low height in the subsequent trench formation process. Next, as shown in FIG. 6k, a third photoresist 14 of a predetermined thickness is coated on the back plane of the sacrificial substrate 120 which has been ground to a predetermined thickness. ♦ The first-photoresist 14 coating method is the same as the first and second photoresist 128 and I ". Then as shown in Η61, the mask with a specific circuit pattern above exposes the third photoresist and 40 to the next Development, thereby forming a third photoresist pattern 142 for opening the central portion of the back plane of the sacrificial substrate. ”Then, as shown in FIG. 6m, the third photoresist pattern 142 is used as a cover to perform etching. The seed layer 126 forms a trench 14 4 for opening the sacrificial substrate 120. The button engraving 1 here is a dry etching process using a mixed gas of sf6 and c4m02 with a specific ratio. More specifically, it is the so-called Bosh system.
O:\89\89662.DOC -24- 200419159 私/、係源自深渠溝钱刻法之反應離子钱刻(RIE)。 接著如圖6n所示,在犧牲基板12〇之背平面上形成之渠溝 144中施加一定數量之環氧化物黏著劑140,接著對以預定 寸之陶瓷板製成之支樓板i48加壓並將之插入渠溝丄 中,藉以將支撐板148嵌入並附接於渠溝144中。 接著如圖6〇所示,藉由移除圖6n之第二光阻圖案136與第 一光阻圖案142使得支撐板148、介電質板130與導體138暴 露在外。 此處之第二光阻圖案136與第三光阻圖案142之移除,係 以使用化學物之乾蝕刻製程或濕蝕刻製程為之。 最終如圖6p所示,藉由在犧牲基板12〇上施行使用化學物 之濕蝕刻製程,使得各導體138之末端部暴露在外。各導體 13 8之下平面之中央部與介電質板130絕緣,且各導體138之 上平面之中央部為支撐板148所支撐,藉以得出探針。 在此移除圖6〇中所示對齊鍵132a與132b及殘餘種層126。 (具體實施例2-2) 圖7a至7ι係闡釋依另一具體實施例製造用以測試平面板 顯示器之探針之方法之剖面圖。 在依本具體實施例之探針製造方法中,如圖7a所示,利 用/儿積I粒如錢鑛製程,於矽等材料製之犧牲基板2〇〇上形 成具預定厚度之種層206,接著於種層上塗佈具預定厚度之 充作保護膜之第一光阻2〇8。 種層206係由鈦層202與銅層204構成。銅層204實質充作 後續電鍍製程中之來源。所具鈦層2〇2係用以改善犧牲基板O: \ 89 \ 89662.DOC -24- 200419159 Private / Reactive ion money engraving (RIE) originated from the deep canal engraving method. Next, as shown in FIG. 6n, a certain amount of epoxy adhesive 140 is applied to the trenches 144 formed on the back plane of the sacrificial substrate 120, and then a branch floor i48 made of a predetermined inch ceramic plate is pressurized and It is inserted into the trench ditch to thereby embed and attach the support plate 148 in the trench 144. Then, as shown in FIG. 60, the support plate 148, the dielectric plate 130, and the conductor 138 are exposed by removing the second photoresist pattern 136 and the first photoresist pattern 142 of FIG. 6n. The second photoresist pattern 136 and the third photoresist pattern 142 are removed here by a dry etching process or a wet etching process using a chemical. Finally, as shown in FIG. 6P, a wet etching process using a chemical is performed on the sacrificial substrate 120, so that the end portion of each conductor 138 is exposed. The central portion of the lower plane of each conductor 138 is insulated from the dielectric plate 130, and the central portion of the upper plane of each conductor 138 is supported by the support plate 148, thereby obtaining a probe. The alignment keys 132a and 132b and the residual seed layer 126 shown in FIG. 60 are removed here. (Embodiment 2-2) FIGS. 7a to 7i are cross-sectional views illustrating a method of manufacturing a probe for testing a flat panel display according to another embodiment. In the method for manufacturing a probe according to this embodiment, as shown in FIG. 7a, a seed layer 206 having a predetermined thickness is formed on a sacrificial substrate 200 made of silicon and other materials by using a process of I / I product such as money ore. Then, a first photoresist 208 serving as a protective film having a predetermined thickness is coated on the seed layer. The seed layer 206 is composed of a titanium layer 202 and a copper layer 204. The copper layer 204 substantially serves as a source in the subsequent electroplating process. The titanium layer 20 is used to improve the sacrificial substrate
O:\89\89662.DOC -25 - 200419159 200與銅層204之黏著性。 接著如圖7b所示,形成第一光阻圖案21〇以界定用以於後 續製程中形成導體之預定區。 可將設計以形成導體之預定電路圖案之罩置於圖〜之犧 牲基板200上形成之第一光阻2〇8上,並接著將其曝光與顯 影’精以形成第一光阻圖案21〇。 而後如圖7c所示,利用電鍍製程沉積傳導材料如鎳 或鎳合金(Ni-Co、Ni-W-Co)於犧牲基板2〇〇上有第一光阻圖 案210形成處而形成充作接觸組件用之傳導膜212。接著利 用平坦化製程使犧牲基板200之上平面平坦化。 利用化學機械拋光(CMP)法及研磨法等施行平坦化製 程。在形成傳導膜212之電鍍製程期間,銅層2〇4係充作電 鍍材料之來源。特別言之,在用以形成傳導膜212之理想電 鍍製程之進程中,僅於第一光阻圖案21〇之開啟部内形 導膜212之情況下,平坦化製程可略之。此外,在利用除電 鍍製程外之方法如物理汽相沉積(PVD)與化學汽相沉積 (CVD)形成傳導膜212之情況下,先前形成種層2〇6之製程可 略之。 接著如圖7d所示,在移除第二光阻圖案21〇後,利用在圖 7c之第二光阻圖案210之開啟部中形成之傳導膜212作為自 行對齊罩而施行蝕刻製程,移除殘餘在圖九之第二光阻圖 案210之下部上之由鈦層202與銅層2〇4構成之種層2〇6。回 此處係利用濕蝕刻或乾蝕刻移除第二光阻圖案21〇,亦可 利用濕蝕刻或乾蝕刻移除種層2〇6。 O:\89\89662.DOC -26- 200419159 而後如圖7e所示,塗 疋數里之弟二光阻214於犧牲基 圖7C之第二光阻圖案被移除處。 此^係利用—般的光阻旋轉塗佈法等塗佈第三光阻214。 接者如圖7f所示,置放上具特定電路圖案之罩於犧牲基 #、 y 土佈有第二光阻214處,並接著將其曝光與顯影, 藉以形成用以開啟充作接觸組件之傳導膜212之令央部之 光阻圖案222。 而後=圖7g所不,施加一定數量之黏著劑216如環氧化物 於利用第—光阻圖案222開啟之開啟部中,接著將具預定尺 寸之介電質材料如陶莞製之支撐板218插入與附接於第三 光阻圖案222之開啟部中。 接著如圖7h所示,藉由移除圖%之第三光阻圖案π使得 由支撐板218與傳導膜212構成之導體暴露在外。 最終如圖7i所示,利用濕蝕刻製程等移除圖凡之犧牲基 板200中之支撐板218與傳導膜212暴露在外處,以及在傳導 膜212之下部上之種層206,藉以完成具傳導膜之探針。 在此以一系列使用不同化學物之濕蝕刻製程依序移除犧 牲基板200以及由銅層202與鈦層2〇4構成之種層2〇6較佳。 此外,並額外施行附接介電質材料如環氧化物於完成之 探針之傳導膜212之背平面上之製程。 (具體實施例2-3) 圖8a至8t係闡釋依另一具體實施例製造用以測試平面板 顯示器之探針之方法之剖面圖。 在依所述具體實施例之探針製造方法中,如圖8a所示, O:\89\89662.DOC -27- 200419159 塗佈第一光阻252於矽等材料製之犧牲基板252上。 此處係利用熟知之光阻旋轉塗佈法等塗佈第一光阻252。 接著如圖8b所示,於犧牲基板250施行後續製程,藉此形 成第一光阻圖案254以界定對齊鍵與塑造接觸組件。 在此藉由對齊一預定罩而於犧牲基板25〇上形成第一光 阻圖案254,接著將其曝光與顯影。 而後如圖8c所示,以犧牲基板25〇上之第一光阻圖案254 為罩,施行蝕刻製程,藉以形成第一渠溝25以與25仳及第 二渠溝258 ’俾用以形成犧牲基板250中之對齊鍵與接觸組 件。 在此係以使用反應性氣體之乾蝕刻製程施行形成第一渠 溝256a與256b及第二渠溝258之製程。 接著在移除在犧牲基板25〇上形成第一渠溝25以與25讣 及第二渠溝258處之第一光阻圖案254後,利用製程如濺鍍 製程形成具預定厚度之種層260。 種層260係由厚5〇〇埃之鈦層261與厚5,〇〇〇埃之銅層262 構成。銅層262實質上係充作後續電鍍製程中之種層26〇。 鈦層261則係用以改善犧牲基板25〇與銅層262之黏著性。 接著如圖8e所示,塗佈一定數量之第二光阻264於犧牲基 板250上形成種層260處。 在此可利用熟知之光阻旋轉塗佈法等塗佈第二光阻264。 一後士圖8f所示’將形成犧牲基板25〇處之第二光阻264 曝光與顯影,藉以形成第二光阻圖案265,俾界定形成第一 渠溝256a與256b及第二渠溝258之區域。O: \ 89 \ 89662.DOC -25-200419159 200 Adhesion to copper layer 204. As shown in FIG. 7b, a first photoresist pattern 21 is formed to define a predetermined area for forming a conductor in a subsequent process. A mask designed to form a predetermined circuit pattern of a conductor may be placed on the first photoresist 208 formed on the sacrificial substrate 200 of FIG. 1 and then exposed and developed to form the first photoresist pattern 21. . Then, as shown in FIG. 7c, a conductive material such as nickel or a nickel alloy (Ni-Co, Ni-W-Co) is deposited by an electroplating process on the sacrificial substrate 200 where the first photoresist pattern 210 is formed to form a full contact. The module uses a conductive film 212. Then, a planarization process is used to planarize the plane above the sacrificial substrate 200. The planarization process is performed by a chemical mechanical polishing (CMP) method and a polishing method. During the electroplating process of forming the conductive film 212, the copper layer 204 serves as a source of electroplating material. In particular, in the course of an ideal electroplating process for forming the conductive film 212, the planarization process can be omitted only in the case where the conductive film 212 is formed in the opening of the first photoresist pattern 21o. In addition, in the case where the conductive film 212 is formed by a method other than the electroplating process, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), the previous process of forming the seed layer 206 can be omitted. As shown in FIG. 7d, after the second photoresist pattern 21 is removed, the conductive film 212 formed in the opening portion of the second photoresist pattern 210 in FIG. 7c is used as a self-aligning mask to perform an etching process to remove A seed layer 206 composed of a titanium layer 202 and a copper layer 204 remaining on the lower portion of the second photoresist pattern 210 in FIG. 9 is formed. Here, the second photoresist pattern 21 is removed by wet or dry etching, and the seed layer 206 can also be removed by wet or dry etching. O: \ 89 \ 89662.DOC -26- 200419159 Then, as shown in Fig. 7e, the second photoresist 214 is applied to the sacrificial base. The second photoresist pattern in Fig. 7C is removed. Here, the third photoresist 214 is coated by a general photoresist spin coating method or the like. The connector is shown in FIG. 7f, and a mask with a specific circuit pattern is placed on the sacrificial base #, and the y soil cloth has a second photoresist 214, and then it is exposed and developed to form a contact component for opening. The photoresist pattern 222 of the central portion of the conductive film 212. Then, as shown in FIG. 7g, a certain amount of an adhesive 216 such as an epoxide is applied to the opening portion opened with the first photoresist pattern 222, and then a dielectric material having a predetermined size, such as a support plate 218 made of ceramics, is applied. Inserted and attached in the opening portion of the third photoresist pattern 222. Next, as shown in FIG. 7h, by removing the third photoresist pattern π of FIG.%, The conductor composed of the support plate 218 and the conductive film 212 is exposed. Finally, as shown in FIG. 7i, the supporting plate 218 and conductive film 212 in Tufan's sacrificial substrate 200 are exposed to the outside by a wet etching process or the like, and a seed layer 206 on the lower part of the conductive film 212 is completed to complete the conductive process. Membrane probe. It is preferable to sequentially remove the sacrificial substrate 200 and the seed layer 206 composed of the copper layer 202 and the titanium layer 204 by a series of wet etching processes using different chemicals. In addition, a process of attaching a dielectric material such as an epoxy on the back plane of the conductive film 212 of the completed probe is additionally performed. (Embodiment 2-3) FIGS. 8a to 8t are cross-sectional views illustrating a method of manufacturing a probe for testing a flat panel display according to another embodiment. In the probe manufacturing method according to the specific embodiment, as shown in FIG. 8a, O: \ 89 \ 89662.DOC -27- 200419159 coats the first photoresist 252 on the sacrificial substrate 252 made of silicon and other materials. Here, the first photoresist 252 is coated by a well-known photoresist spin coating method or the like. Then, as shown in FIG. 8b, a subsequent process is performed on the sacrificial substrate 250, thereby forming a first photoresist pattern 254 to define the alignment key and the shape of the contact element. Here, a first photoresist pattern 254 is formed on the sacrificial substrate 25 by aligning a predetermined mask, and then it is exposed and developed. Then, as shown in FIG. 8c, the first photoresist pattern 254 on the sacrificial substrate 25 is used as a cover, and an etching process is performed to form the first trench 25 and 25 仳 and the second trench 258 '俾 to form a sacrifice. Alignment keys and contact components in the substrate 250. This is a process of forming the first trenches 256a and 256b and the second trench 258 by a dry etching process using a reactive gas. After removing the first trench 25 formed on the sacrificial substrate 25 and the first photoresist pattern 254 at 25 讣 and the second trench 258, a seed layer 260 having a predetermined thickness is formed by a process such as a sputtering process. . The seed layer 260 is composed of a titanium layer 261 with a thickness of 500 angstroms and a copper layer 262 with a thickness of 5,000 angstroms. The copper layer 262 is substantially used as a seed layer 26 in the subsequent electroplating process. The titanium layer 261 is used to improve the adhesion between the sacrificial substrate 25 and the copper layer 262. Next, as shown in FIG. 8e, a certain number of second photoresists 264 are coated on the sacrificial substrate 250 to form a seed layer 260. Here, the second photoresist 264 can be applied by a known photoresist spin coating method or the like. As shown in FIG. 8f, the second photoresist 264 at the sacrifice substrate 25 is formed and exposed to develop a second photoresist pattern 265, and the first trenches 256a and 256b and the second trench 258 are defined. Area.
O:\89\89662.DOC -28 - 200419159 而後如圖8g所示,利用電鍍製程沉積傳導材料如鎳(Ν〇 或鎳合金(Ni-Co、Ni_W_co)於犧牲基板25〇上有第二光阻圖 案265形成處而形成傳導膜266。 此處在用以形成傳導膜266之電鍍製程期間,在種層26〇 中之銅層262係充作電鍍材料之來源。 接著如圖8h所示,將犧牲基板25〇之上平面上形成傳導膜 266處平坦化。犧牲基板25〇之上平面之平坦化製程係利用 化學機械拋光(CMP)法及研磨法等為之。 此外,在用以形成傳導膜266之理想電鍍製程之進程中, 僅於第二光阻圖案265之開啟部内形成傳導膜266之情況 下,平坦化製程可略之。 接著如圖8i所示,塗佈一定數量之第三光阻268於犧牲基 板250上完成平坦化製程處。 在此可利用熟知之光阻旋轉塗佈法等塗佈第三光阻268。 接著如圖8j所示,形成用以開啟在犧牲基板25〇上形成之 傳導膜266之中央部之第三光阻圖案27〇。 此處可藉由採用一罩之曝光製程與顯影製程形成第三光 阻圖案270。 接著如圖8k所示,藉由嵌入介電質材料如環氧化物於第 三光阻圖案270所開啟之開啟部中而形成介電質板272。 而後如圖81所示’將犧牲基板250之上平面上形成介電質 板272處平坦化。該平坦化係利用化學機械拋光(CMp)法及 研磨法等為之。 接著如圖8m所示,犧牲基板250面朝下,並研磨犧牲基板 O:\89\89662.DOC -29- 200419159 2^0之背平面至預定厚度,施行該研磨製程,以調整在後續 木溝形成製程中,犧牲基板25〇之蝕刻深度於低高度。 接著如圖8η所示,塗佈預定厚度之第四光阻274於被施行 研磨製程之犧牲基板250之背平面上。可利用熟知之光阻塗 佈法形成第四光阻274。 接著如圖8〇所示,將在犧牲基板25〇上形成之第四光阻 274曝光並接著顯影,藉此形成用以開啟犧牲基板之背 平面之中央邛(犧牲基板250之中央部)之第四光阻圖案276。 而後如圖8ρ所示,以第四光阻圖案276為罩施行蝕刻製 程。藉此於犧牲基板250之背平面上形成用以開啟傳導膜 266之第二渠溝278。此處之蝕刻製程係使用具特定比例之 SF6、CUF8與〇2之混合氣體之乾蝕刻製程。 更特別言之,係利用所謂的波許製程施行蝕刻製程,其 係一源自深渠溝钱刻法之反應離子蝕刻(RIE)。 接著如圖8q所示,在犧牲基板25〇之背平面上形成之第三 渠溝278中施加一定數量之環氧化物黏著劑28〇,接著對以 預定尺寸之陶瓷板製成之支撐板282加壓並將之插入渠溝 278中,藉以將支撐板282埋入並附接於第三渠溝278中。 接著如圖8r所示’以平坦化製程將犧牲基板250之背平面 上支撐板282埋入第三渠溝278處平坦化。 利用化學機械拋光(CMP)法或研磨法施行平坦化製程。 而後如圖8s所示,移除第三光阻圖案27〇、第四光阻圖案 276與種層260。 最終如圖8t所示,利用蝕刻製程移除犧牲基板25〇,藉此 O:\89\89662.DOC -30- 200419159 完成之探針具有附接於具黏著劑280之導體284之上部上之 支撐組件282以及位於導體284之下部上之介電質板272。 圖9係闡釋依另一具體實施例製造用以測試平面板顯示 器之探針之方法之透視圖。 在依本具體實施例之探針製造方法中,製備圖6〇之導體 130完全暴露在外之第一犧牲基板28〇與第二犧牲基板 282’或是製備圖8t之導體284完全暴露在外之第一犧牲基 板280與第二犧牲基板282。 此處之對齊鍵288、介電質板284及導體286向外暴露於第 一犧牲基板280與第二犧牲基板282上。 接著藉由相對於對齊鍵288或操作者眼睛之第一犧牲基 板280之導體284與第二犧牲基板282之導體284之匹配,將 第一犧牲基板280與第二犧牲基板282附接在一起,並接著 以黏著劑使之相互附接。 在第二犧牲基板282上形成之複數個導體286垂直配置於 在第一犧牲基板280上形成之複數個相鄰導體286間之間隙 空間中,藉以使得第二犧牲基板282之各導體286垂直配置 於第一犧牲基板280之相鄰導體286間,並且第二犧牲基板 282之各導體286之末端部較第一犧牲基板28〇之各導體286 之末端部水平突出為多(其中導體為多層結構)。 而後,以與前揭具體實施例相同之濕蝕刻製程移除第一 與第二犧牲基板280與282,藉以製造堆疊探針處之多層探 針。 雖然在本具體實施例中所述係雙層探針,應知可依製造 O:\89\89662.DOC -31- 200419159 者意向製造三或多層探針。 圖10 a係闡釋依另_ θ ^ , 释为具體貫施例之探針之透視圖丨圖l0b 係其剖面圖。 士圖l〇a與l〇b所不’依本發明之具體實施例之探針係由 雙層結構構成,其中利用黏著工具如黏著劑將在第一探針 300與第二探針训上形成之介電質板娜與316附接在一 起,藉此堆疊第一探針3〇〇與第二探針31〇。 在第k針300與第二探針31〇中,在陶竟等製之支撐板 308與3,18之下部上以預定間隔分別附接複數個導體3们與 312,並將介電質材料如環氧化物304與314製之介電質板 3〇6與316分別附接於導體302與312之下中央部上。、 更特別言之,第二探針310之各導體垂直配置於第一探針 300之相鄰導體3〇2間之間隙* — 、 Ί隙二間中,猎此得以將多層探針 之導體302與導體312之間隔調整至極短。 在》亥隹且、構中,第二探針31〇之各較 300之各導體如之末端部在水平方向突出。 針 此外,在另一具體實施例八 中刀別在弟一楝針300與第二 奴針310上形成之支撐板3〇8盥 接在一起,藉此得以製出堆:古^者具如黏者劑附 衣出堆璺有弟一探針3〇〇盥第一 31〇之雙層結構。 ,、弟一铋針 再者,在又一具體實施例 之介恭皙叔採針300或弟二探針310 屯、 A 6和第一探針300或第二探針31〇 板308與318間為黏著工呈*私— υ之支撐 ^ 具如黏著劑附接在一起,#此彳 製出堆疊有第—探針30㈣ 猎此钎以 一弟一奴針3 1〇之雙層結構。O: \ 89 \ 89662.DOC -28-200419159 and then as shown in FIG. 8g, a conductive material such as nickel (N0 or nickel alloy (Ni-Co, Ni_W_co)) is deposited on the sacrificial substrate 25 by a plating process. A conductive film 266 is formed where the resist pattern 265 is formed. Here, during the electroplating process used to form the conductive film 266, the copper layer 262 in the seed layer 26 is used as the source of the electroplating material. Next, as shown in FIG. 8h, The conductive film 266 is planarized on the plane above the sacrificial substrate 25. The planarization process of the plane above the sacrificial substrate 25 is performed by a chemical mechanical polishing (CMP) method or a polishing method. In the course of the ideal plating process of the conductive film 266, the planarization process can be omitted only when the conductive film 266 is formed in the opening portion of the second photoresist pattern 265. Then, as shown in FIG. The three photoresist 268 completes the planarization process on the sacrificial substrate 250. Here, the third photoresist 268 can be coated by a well-known photoresist spin coating method, etc. Then, as shown in FIG. Central portion of conductive film 266 formed on 25 The third photoresist pattern 27. Here, a third photoresist pattern 270 can be formed by using a mask exposure process and a development process. Then, as shown in FIG. 8k, a dielectric material such as an epoxide is embedded in the first photoresist pattern. A dielectric plate 272 is formed in the opening portion opened by the three photoresist patterns 270. Then, as shown in FIG. 81, the dielectric plate 272 is planarized on the plane above the sacrificial substrate 250. This planarization uses chemistry The mechanical polishing (CMp) method and polishing method are used. Then, as shown in FIG. 8m, the sacrificial substrate 250 faces downward, and the back surface of the sacrificial substrate O: \ 89 \ 89662.DOC -29- 200419159 2 ^ 0 is polished to The polishing process is performed at a predetermined thickness to adjust the etching depth of the sacrificial substrate 25 to a low height in the subsequent trench formation process. Next, as shown in FIG. 8η, a fourth photoresist 274 of a predetermined thickness is applied to be polished. On the back plane of the sacrificial substrate 250 in the manufacturing process, a fourth photoresist 274 can be formed by a well-known photoresist coating method. Next, as shown in FIG. 80, the fourth photoresist 274 formed on the sacrificial substrate 25 is exposed and exposed. It is then developed to form a substrate for opening the sacrificial substrate. A fourth photoresist pattern 276 in the center of the plane (the central portion of the sacrificial substrate 250). Then, as shown in FIG. 8ρ, an etching process is performed using the fourth photoresist pattern 276 as a cover. A second trench 278 is formed to open the conductive film 266. The etching process here is a dry etching process using a specific proportion of a mixed gas of SF6, CUF8, and O2. More specifically, it uses a so-called Bosch An etching process is performed in the process, which is a reactive ion etching (RIE) derived from the deep trench engraving method. Then, as shown in FIG. 8q, a certain amount is applied to the third trench 278 formed on the back plane of the sacrificial substrate 25. Quantity of epoxy adhesive 28, and then pressurizing the support plate 282 made of a ceramic plate of a predetermined size and inserting it into the trench 278, thereby burying and attaching the support plate 282 to the third trench 278. Next, as shown in FIG. 8r ', the support plate 282 on the back plane of the sacrificial substrate 250 is buried in the third trench 278 and planarized by a planarization process. The planarization process is performed by a chemical mechanical polishing (CMP) method or a polishing method. Then, as shown in FIG. 8s, the third photoresist pattern 270, the fourth photoresist pattern 276, and the seed layer 260 are removed. Finally, as shown in FIG. 8t, the sacrificial substrate 25 is removed by an etching process, so that the completed probe having O: \ 89 \ 89662.DOC -30-200419159 has an upper portion attached to a conductor 284 with an adhesive 280 The supporting component 282 and a dielectric plate 272 on the lower portion of the conductor 284. Fig. 9 is a perspective view illustrating a method of manufacturing a probe for testing a flat panel display according to another embodiment. In the probe manufacturing method according to this embodiment, the first sacrificial substrate 28o and the second sacrificial substrate 282 ′ where the conductor 130 of FIG. 60 is completely exposed or the conductor 284 of the FIG. 8t is completely exposed. A sacrificial substrate 280 and a second sacrificial substrate 282. Here, the alignment key 288, the dielectric plate 284, and the conductor 286 are exposed on the first sacrificial substrate 280 and the second sacrificial substrate 282 to the outside. Then, the first sacrificial substrate 280 and the second sacrificial substrate 282 are attached together by matching the conductor 284 of the first sacrificial substrate 280 and the conductor 284 of the second sacrificial substrate 282 with respect to the alignment key 288 or the eye of the operator. It is then attached to each other with an adhesive. The plurality of conductors 286 formed on the second sacrificial substrate 282 are vertically arranged in a gap space between a plurality of adjacent conductors 286 formed on the first sacrificial substrate 280, so that the conductors 286 of the second sacrificial substrate 282 are vertically arranged. Between adjacent conductors 286 of the first sacrificial substrate 280, and the ends of the conductors 286 of the second sacrificial substrate 282 protrude more horizontally than the ends of the conductors 286 of the first sacrificial substrate 28 (the conductors have a multilayer structure) ). Then, the first and second sacrificial substrates 280 and 282 are removed by the same wet etching process as the previous embodiment, so as to manufacture the multilayer probes at the stacked probes. Although the double-layer probe is described in this embodiment, it should be understood that three or more probes can be manufactured according to the intention of the manufacturer of O: \ 89 \ 89662.DOC -31- 200419159. Fig. 10a is a perspective view illustrating a probe according to another embodiment θθ ^, and Fig. 10b is a cross-sectional view thereof. The probes 10a and 10b do not according to the specific embodiment of the present invention are composed of a double-layer structure, wherein the first probe 300 and the second probe are trained with an adhesive tool such as an adhesive. The formed dielectric substrate is attached to 316, thereby stacking the first probe 300 and the second probe 31. In the k-th pin 300 and the second probe 31, a plurality of conductors 3 and 312 are attached to the lower portions of the support plates 308 and 3, 18 made of Tao Jing, etc. at predetermined intervals, and the dielectric material is For example, dielectric plates 306 and 316 made of epoxides 304 and 314 are attached to the central portions below the conductors 302 and 312, respectively. More specifically, the conductors of the second probe 310 are vertically arranged in the gap * 2 between the adjacent conductors 300 of the first probe 300, and the gap between the two conductors. The interval between 302 and the conductor 312 is adjusted to be extremely short. In the helium structure, the end portions of each of the second probes 31 and 300 are protruded in the horizontal direction from each of the conductors such as 300. In addition, in another eighth embodiment, the support plate 3008 formed by the knife on the first needle 300 and the second slave needle 310 is welded together, thereby making a pile: There is a double-layer structure of the first probe 300 and the first 31. In addition, in one specific embodiment, the brother-bismuth needle 300, or the brother-second probe 310, A 6 and the first probe 300 or the second probe 31, plates 308 and 318. The support for the adhesive is private — υ is attached ^ It is attached together as an adhesive, #this 彳 makes a stack of the first-probe 30 ㈣ hunting this drill with a younger and slave needle 3 1 10 double-layer structure.
O:\89\89662.DOC -32- 200419159 因此,第一探針300與第二探針31〇係位於堆疊結構中之 雙層採針併入探針組(未圖示)中,以確認經由一系列生產掣 程所得之平面板顯示裝置之正常性。 、 探針之各導體302與312之-末端部與平面板顯示器之一 測試處相接’亦即與塾電極相接,其另—末端部則連結至 與驅動晶片相連之捲帶式封裝(Tcp),藉此確認平面板顯示 器之正常性。 、’' (具體實施例2-4) 圖11係闡釋依另-具體實施例之用以測試平面板顯示器 之探針之透視圖。如圖11所示,探針具有各具桿狀光束構 件322之複數個單元導體32〇,而光束構件322之一端具有與 之整合之檢測尖端324a,光束構件322之另一端則具有與2 整合之檢測尖端324b。複數個單元導體32〇均以預定間隔配 置。 i 此處之光束構件322及尖端324a與32仆係由具優良傳導 率及延展性之金屬材料如(Ni)或鎳合金(Ni_c〇、 製成,各尖端324a與324b之末端部歷經圓化(r〇unding)製 矛王’以抑制微粒之產生。 此外,利用加壓製程與加熱製程將具預定大小並由可透 光材料如環氧化物或聚對二曱笨製成之可透光薄膜342附 接於複數個單元導體320上。 因此,將複數個單元導體320與薄膜342附接處之探針片 併入楝針組中,以確認經由一系列生產製成所得之平面板 顯示器之正常性。O: \ 89 \ 89662.DOC -32- 200419159 Therefore, the first and second probes 300 and 31 are double-layered needles located in a stacked structure and merged into the probe set (not shown) to confirm The normality of the flat panel display device obtained through a series of production processes. The ends of each of the conductors 302 and 312 of the probe are connected to one of the test points of the flat panel display, that is, connected to the rubidium electrode, and the other end is connected to a tape and reel package connected to the driving chip ( Tcp) to confirm the normality of the flat panel display. ('Embodiment 2-4) Fig. 11 is a perspective view illustrating a probe for testing a flat panel display according to another embodiment. As shown in FIG. 11, the probe has a plurality of unit conductors 32 each having a rod-shaped beam member 322, and one end of the beam member 322 has a detection tip 324a integrated therewith, and the other end of the beam member 322 has an integration with 2 Its detection tip 324b. The plurality of unit conductors 32 are arranged at predetermined intervals. i The beam member 322 and the tips 324a and 32 are made of a metal material with excellent conductivity and ductility, such as (Ni) or nickel alloy (Ni_c0,), and the ends of the tips 324a and 324b are rounded. (R〇unding) to make spear kings to suppress the generation of particles. In addition, a pressure-transmitting process and a heating process will be made of a light-transmissive material having a predetermined size and made of a light-transmissive material such as epoxide or polyparaben. The thin film 342 is attached to a plurality of unit conductors 320. Therefore, the probe pieces where the plurality of unit conductors 320 and the thin film 342 are attached are incorporated into a pin set to confirm a flat panel display made through a series of productions Normality.
O:\89\89662.DOC -33- 200419159 掩針片之連結尖端324b連結至與驅動晶片相連之捲帶式 封衣(TCP) ’棟針片之檢測尖端32乜重複與平面板顯示器之 測試處接觸,亦即與墊電極接觸,藉此確認平面板顯示器 之正常性。 此外,在另一具體實施例中,可不具各單元接觸組件之 光束構件322之連結尖端324b。不具連結尖端324b之各單元 導體320可經由非等向性傳導膜(ACF)連結至捲帶式封裝 (TCP) 〇 圖12a至12:係闡釋圖u所示之用以測試平面板顯示器之 探針之製造方法之剖面圖。 、現參閱圖12描述依本發明之用以測試平面板顯示器之製 仏方法。首先,於具特定方向性如(1,〇,〇)之矽製之犧牲基 板330上,形成在後續製程中用以形成第一渠溝33乜與第二 渠溝33 4b之光阻圖案332。 第光阻圖案332係由具高感光性之光阻構成。第一光阻 圖案332之形成,係利用旋轉塗佈厚約2微米之光阻於基板O: \ 89 \ 89662.DOC -33- 200419159 The connecting tip 324b of the mask is connected to the tape-type seal (TCP) connected to the driver chip. Contact everywhere, that is, contact with the pad electrode, thereby confirming the normality of the flat panel display. In addition, in another specific embodiment, the connection tip 324b of the light beam member 322 of each unit contact assembly may not be provided. Each unit conductor 320 without the connection tip 324b can be connected to a tape and reel package (TCP) via an anisotropic conductive film (ACF). Figures 12a to 12: Explain the test for flat panel displays shown in Figure u. Sectional view of needle manufacturing method. Now, a manufacturing method for testing a flat panel display according to the present invention will be described with reference to FIG. First, a photoresist pattern 332 is formed on a sacrificial substrate 330 made of silicon having a specific directivity such as (1, 0, 0) to form a first trench 33 乜 and a second trench 33 4b in a subsequent process. . The first photoresist pattern 332 is made of a photoresist with high sensitivity. The first photoresist pattern 332 is formed by spin coating a photoresist with a thickness of about 2 microns on the substrate.
330之前平面上之旋轉塗佈製程’接著施行曝光製程與: 製程為之。 ' P 接著如圖12 b所示 往暴板330上形成之第一、 阻圖案332為钱刻罩,施行第一颠刻製程,藉此分別形成; 一渠溝334a與第二渠溝334b(檢測尖端32乜與連結^ 324b係於其中形成)。 "大為 形成渠溝334a與334b之第一蝕刻製程可為採用以預定七 例混合之氳氧化鉀(KOH)與去離子水之化學 疋处 予切 < 濕蝕刻製 O:\89\89662.DOC -34- 200419159 程。以使用化學物之濕㈣製程非等向㈣具特定方向性 之犧牲基板,藉此形成截面角錐狀或截面圓錐狀之第一渠 溝334a與第二渠溝334b。 木 而後如圖12c所示,以第一光阻圖案爪為敍刻罩,施行 第二餘刻製程,藉此形成之截面角錐狀或截面圓錐狀之第 -渠溝334a與第二渠溝侧深度深,並使渠溝334&與渠溝 334b歷經圓化製程。 此處之蝕刻製程係使用具特定比例之SF<6、與〇2之混 合氣體之乾蝕刻製程。 & 更特別言之,係利用所謂的波許製程施行第二蝕刻製 耘,其係一源自深渠溝蝕刻法之反應離子蝕刻(RIE)。 接著先使截面角錐狀或截面圓錐狀之第一渠溝334a與第 二渠溝334b歷經第製程,使其深度為3G微米至微 米,並使渠溝334a與334b底部歷經圓化製程。 而後如圖12d所*,在利用濕韻刻製程移除圖α之第一 光阻圖案332後,於前已歷經第二#刻製程之犧牲基板咖 上形成在後續製程中充作種層336用之厚2,〇〇〇埃至3,㈧〇埃 之銅層。 、 此處可利用物理沉積法如濺鍍製程形成銅層。 接著如圖12e所示,形成第二光阻圖案338,俾開啟在後 續製程中欲形成光束構件332之區域。 利用旋轉塗布製程、曝光製程及顯影製程,形成且有盘 第一光阻圖案332類似之高感光性之光阻所構成之第二= 阻圖案338。The spin coating process on the plane before 330 'is followed by an exposure process and: 'P Next, as shown in FIG. 12b, the first and resist patterns 332 formed on the storm plate 330 are engraved masks, and the first inversion process is performed to form them separately; a trench 334a and a second trench 334b ( The detection tip 32 乜 and the connection ^ 324b are formed therein). " The first etching process for forming the trenches 334a and 334b can be carried out by using a chemical treatment of potassium hydroxide (KOH) and deionized water mixed in predetermined seven cases < wet etching O: \ 89 \ 89662.DOC -34- 200419159 process. A sacrificial substrate with a specific directivity is formed in a non-isotropic wet process using a chemical, thereby forming a first channel trench 334a and a second channel trench 334b with a pyramidal or conical cross section. Then, as shown in FIG. 12c, the first photoresist pattern claw is used as the engraving mask, and the second post-etching process is performed to form the first trench 334a and the second trench side of the pyramid-shaped or cross-sectional cone. The depth is deep, and the ditch 334 & and ditch 334b have undergone a rounding process. Here, the etching process is a dry etching process using a specific ratio of SF < 6, and a mixed gas with 02. & More specifically, a second etching process is performed using a so-called Bosch process, which is a reactive ion etching (RIE) derived from a deep trench etching method. Then, the first trenches 334a and the second trenches 334b having a pyramidal or conical section are subjected to a first process to a depth of 3 Gm to micrometers, and the bottoms of the trenches 334a and 334b are subjected to a rounding process. Then, as shown in FIG. 12D, after the first photoresist pattern 332 of FIG. Α is removed by the wet rhyme engraving process, a sacrificial substrate coffee that has previously undergone the second # engraving process is formed as a seed layer 336 in the subsequent process Use a copper layer with a thickness of 2,000 angstroms to 3,100 angstroms. Here, a copper layer can be formed by a physical deposition method such as a sputtering process. Next, as shown in FIG. 12e, a second photoresist pattern 338 is formed, and the region where the beam member 332 is to be formed in a subsequent process is opened. Using a spin coating process, an exposure process, and a development process, a second photoresist pattern 338, which is formed by a disk and has a photoresist similar to the first photoresist pattern 332, is formed.
O:\89\89662.DOC -35- 200419159 而後如圖12f所示,利用電鍍製程形成由具有優良傳導率 與延展性之金屬材料如鎳(Ni)或鎳合金(Ni_c〇、Ni_w_c〇) 之具預定厚度之金相,接著藉由化學機械拋光(cMp)法、 回蝕(etchback)法、研磨法等將犧牲基板33〇之上平面平坦 化而形成光束構件340。 但在先前施行製程中之電鍍製程中使用之種層⑽之形 成製程可略之,利用化學汽相沉積(CVD)法、物理汽相沉積 (PVD)法等形成由Ni、Ni_c〇、Ni_w_c〇等冑之具預定厚度 之金屬膜’藉以形成光束構件34〇。 此外S鈀行平坦化製耘後’施行附加清洗製程以移除 犧牲基板3 3 0上之有機材料與微粒較佳。 接著如圖12g所示,在以濕蝕刻製程移除圖之第二光 阻圖案338後,將犧牲基板33〇上移除第二光阻圖案338處切 方0 而後如圖12h所示,㉟由可彡光材料如環氧化物或聚對二 甲苯製之薄膜342至於切方之犧牲基板33〇上,接著利用加 壓製程與加熱製程,將薄膜342附接於在犧牲基板33〇上形 成之光束構件340之上平面上。 在此將藉由對薄膜342之加壓與加熱,在犧牲基板33〇上 形成由金屬膜構成之光束構件34〇之上部插入並附接於薄 膜342中。 、彳 最終如圖12i所示,以使用化學物之濕蝕刻製程移除犧牲 基板330,藉此完成具類桿狀光束構件34〇之探針片,而光 束構件340之兩端分具接處尖端324a與連結尖端32处。 O:\89\89662.DOC -36- 200419159 (具體實施例2-5) 在依本發明之用以測試平面板顯示器之探針製造方法之 第-具體實施例中’如圖13a所示,以兩面均經拋光之具預 定厚度之矽(Si)作為犧牲基板400。研磨製程或拋光製程後 之犧牲基板400厚約400至500微米。 接著如圖13a(b)所示,利用微影製程在犧牲基板4〇〇之兩 平面上形成與探針外型對應之第一光阻圖案4〇2&與4〇几。 在此由於係利用微影製程形成圖案402a與402b,故可於所 要位置精確形成之。因此,與人工操作相較,得以進一步 改善錯誤。亦即,可以相同間隔於犧牲基板4〇〇上形成相同 大小之複數個導體,特別言之,可於精確位置處交替形成 犧牲基板400之上平面a上之導體41仏及犧牲基板4〇〇之下 平面B上之導體412b。 因此,如圖13a(b)所示,在犧牲基板4〇〇之上下平面A與B 上形成之第一光阻圖案402a與402b係於稍後呈交替形式之 探針形成處之非對稱結構中形成。 而後如圖13a(c)所示,犧牲基板4〇〇之上平面a上之區域 係利用第一光阻圖案402a開啟,並利用非等向性乾蝕刻製 釭蝕刻之,藉以於犧牲基板4〇〇之上平面八上形成具探針外 型之槽404。 接著如圖13a(d)所示,亦利用與上平面相同之製程蝕刻犧 牲基板400之下平面B,藉以形成具探針外型之槽4〇6。此處 在犧牲基板400之上下平面A與B上形成之槽4〇4與406,呈 有槽404與406相互交替之非對稱結構。 O:\89\89662.DOC -37- 200419159 此外,分別於犧牲基板400之上下平面A與B上形成之槽 404與406之蝕刻深度範圍在70至100微米,此係針對後續平 坦化製程之移除深度所作考量,因此蝕刻深度相對較所得 導體深度(亦即60微米)深。 而後如圖13a(e)所示,以使用化學物溶劑之濕触刻製程將 歹成留在犧牲基板400之上下平面A與B上之第一光阻圖案 402a與402b移除。 接著如圖13a(f)所示,形成種層408a與408b,俾施行用以 形成犧牲基板400之兩平面上之導體之電鍍製程。此處之種 層係由厚500埃之鈦層及厚5,000埃之銅層構成。銅層係充 作後續電鍍製程中電鍍之種層用,鈦層則係用以提升犧牲 基板4 0 0與銅層間之黏著性。 而後如圖13a(g)所示,利用微影製程形成第二光阻圖案 410a與410b,以開啟犧牲基板4〇〇之兩平面入與8上之預定 部。 接耆如圖13b(h)所示,利用電解f電㈣程於犧牲基板 400之兩平面八與3上形成利用第二光阻圖案“Μ與41〇b開 啟之導體412a與412b。亦即以第二光阻圖案他與㈣為 杈’以電解夤電鍍法沉積傳導材料如鎳⑼)或鎳合金 (Ni Co Nl-W_Co)而在犧牲基板400上形成導體412a與 412b 〇 圖13b(i)至(p)闡釋縱向圖與橫向圖,冑清楚解釋本發明。 如圖1 3 (i)所示,將自笛_卜 弟一光阻圖案41〇a與410b及犧牲基 板400之兩平面A與B突ψ +如 出之4伤移除,藉以將犧牲基板4〇〇O: \ 89 \ 89662.DOC -35- 200419159 and then as shown in Figure 12f, the electroplating process is used to form a metal material with excellent conductivity and ductility such as nickel (Ni) or nickel alloy (Ni_c0, Ni_w_c〇). A metallographic film having a predetermined thickness is then used to planarize the plane above the sacrificial substrate 33 by a chemical mechanical polishing (cMp) method, an etchback method, a polishing method, or the like to form a beam member 340. However, the formation process of the seed layer used in the plating process in the previous implementation process can be omitted. The chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method, etc. are used to form Ni, Ni_c0, Ni_w_c. A metal film with a predetermined thickness is formed to form a beam member 34. In addition, after the S palladium line is flattened, an additional cleaning process is performed to remove organic materials and particles on the sacrificial substrate 3 3 0. Next, as shown in FIG. 12g, after the second photoresist pattern 338 in the figure is removed by a wet etching process, the square 0 of the second photoresist pattern 338 is removed from the sacrificial substrate 33 and then as shown in FIG. 12h, ㉟ A thin film 342 made of a light-emitting material such as epoxide or parylene is cut on the sacrificial substrate 33. Then, the thin film 342 is attached to the sacrificial substrate 33 using a pressure process and a heating process. The beam member 340 is on a plane. Here, the upper portion of the beam member 34o formed of a metal film on the sacrificial substrate 33o is inserted and attached to the thin film 342 by pressing and heating the thin film 342. Finally, as shown in FIG. 12i, the sacrificial substrate 330 is removed by a wet etching process using a chemical, thereby completing a probe sheet with a rod-like beam member 34o, and two ends of the beam member 340 are divided into joints. The tip 324a is connected to the tip 32. O: \ 89 \ 89662.DOC -36- 200419159 (specific embodiment 2-5) In the first-specific embodiment of the method for manufacturing a probe for testing a flat panel display according to the present invention, 'as shown in FIG. 13a, As the sacrificial substrate 400, silicon (Si) having a predetermined thickness polished on both sides is used. The sacrificial substrate 400 after the grinding process or the polishing process is about 400 to 500 microns thick. Next, as shown in FIG. 13a (b), a lithography process is used to form first photoresist patterns 402 & and 402 on the two planes of the sacrificial substrate 400 corresponding to the shape of the probe. Since the patterns 402a and 402b are formed here using a lithography process, they can be accurately formed at a desired position. Therefore, compared with manual operation, the error can be further improved. That is, a plurality of conductors of the same size can be formed on the sacrificial substrate 400 at the same interval. In particular, the conductor 41 仏 and the sacrificial substrate 400 on the plane a above the sacrificial substrate 400 can be alternately formed at precise positions. The conductor 412b on the lower plane B. Therefore, as shown in FIG. 13a (b), the first photoresist patterns 402a and 402b formed on the sacrificial substrate 400 above and below the planes A and B are asymmetric structures where the probes are alternately formed later. Middle formation. Then, as shown in FIG. 13a (c), the area on the plane a above the sacrificial substrate 400 is turned on by the first photoresist pattern 402a, and is etched by anisotropic dry etching to sacrifice the substrate 4 A groove 404 having a probe shape is formed on the upper surface of the upper surface. Next, as shown in Fig. 13a (d), the lower plane B of the sacrificial substrate 400 is also etched by the same process as the upper plane, so as to form a groove 4 06 with a probe shape. Here, the grooves 4004 and 406 formed on the upper and lower planes A and B of the sacrificial substrate 400 have an asymmetric structure in which the grooves 404 and 406 alternate with each other. O: \ 89 \ 89662.DOC -37- 200419159 In addition, the etching depths of the grooves 404 and 406 formed on the upper and lower planes A and B of the sacrificial substrate 400 are in the range of 70 to 100 microns, which is for the subsequent planarization process. The removal depth is taken into account, so the etch depth is relatively deeper than the resulting conductor depth (ie, 60 microns). Then, as shown in FIG. 13a (e), the first photoresist patterns 402a and 402b remaining on the lower and upper planes A and B of the sacrificial substrate 400 are removed by a wet-touch engraving process using a chemical solvent. Next, as shown in FIG. 13a (f), seed layers 408a and 408b are formed, and a plating process is performed to form conductors on two planes of the sacrificial substrate 400. The seed layer here is composed of a titanium layer with a thickness of 500 angstroms and a copper layer with a thickness of 5,000 angstroms. The copper layer is used as a seed layer for electroplating in the subsequent electroplating process, and the titanium layer is used to improve the adhesion between the sacrificial substrate 400 and the copper layer. Then, as shown in FIG. 13a (g), the second photoresist patterns 410a and 410b are formed by a lithography process to open predetermined portions on the two planes of the sacrificial substrate 400 and 8. Then, as shown in FIG. 13b (h), the conductors 412a and 412b opened with the second photoresist patterns "M and 41〇b" are formed on the two planes 8 and 3 of the sacrificial substrate 400 by the electrolytic f electric process. Using the second photoresist pattern as a base, a conductive material such as nickel 杈 is deposited by electrolytic 夤 plating method or nickel alloy (Ni Co Nl-W_Co) to form conductors 412a and 412b on the sacrificial substrate 400. FIG. 13b (i ) To (p) explain the longitudinal and lateral views, and clearly explain the present invention. As shown in FIG. 13 (i), the two planes of the photodiode pattern photoresist 41a and 410b and the sacrificial substrate 400 are shown. A and B sudden ψ + 4 wounds are removed in order to sacrifice the substrate 4〇〇
O:\89\89662.DOC •38- 200419159 之兩平面A與B平坦^匕。此處之平坦化製程係利用化學機械 扎光(CMP)法、研磨法、折疊〇叩_幻法及抛光法等施行。 但在用以形成導體412a與412b之理想電㈣程之進程中, 僅於具探針外型之槽4〇4與偏内形《導體41^與觀(利 用第二光阻圖案41〇a與410b開啟)之情況下,平坦化製程即 可略之。此外,在導體412&與41213平坦化之後,以鍍金製 程於其上平面上形成鍍金層,藉以改善導體傳導率。 此外在利用除黾鍵製程外之方法如物理汽相沉積(PVD) 與化學汽相沉積(CVD)形成導體412&與4121)之情況下,先前 形成種層408a與408b之製程即可略之。 接著如圖13b⑴所示,利用微影製程形成第三光阻圖案 414,以開啟犧牲基板4〇〇之上平面a上之中央部。 接著如圖13b(k)所示,以等向性乾蝕刻製程將利用第三光 阻圖案414開啟之區域蝕刻。在此蝕刻至包含導體412&形成 處在内之整體犧牲層的一半,藉以形成第一渠溝410。 接著如圖13c(l)所示,在將施加於第一渠溝416中充作介 電質用之環氧化物420熱塑化後,並在環氧化物42〇固化 前,將供支撐用之陶瓷板418黏著於其上部。由於陶瓷板418 係由硬質材料構成,故陶瓷板具有用以抵禦施加於探針上 之特定外力而避免探針形變之支撐組件功能,並可達成維 持探針外型之功能。 當完成形成環氧化物420與陶瓷板418之製程後,即完成 在犧牲板400之上平面a上之製程。 現將描述在犧牲基板400之下平面B上之其餘製程.。O: \ 89 \ 89662.DOC • 38- 200419159 The two planes A and B are flat. Here, the planarization process is performed by a chemical mechanical CMP method, a polishing method, a folding method, and a polishing method. However, in the process of forming an ideal electrical process for the conductors 412a and 412b, only the grooves with a probe shape 404 and the inward-shaped "conductor 41 ^ and view (using the second photoresist pattern 41〇a And 410b on), the planarization process can be omitted. In addition, after the conductors 412 & and 41213 are flattened, a gold plating layer is formed on the upper plane by a gold plating process to improve the conductivity of the conductors. In addition, in the case of using methods other than the ytterbium bonding process such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) to form the conductors 412 & and 4121), the previous process of forming the seed layers 408a and 408b can be omitted . Next, as shown in FIG. 13b (a), a third photoresist pattern 414 is formed by a lithography process to open the central portion on the plane a above the sacrificial substrate 400. Next, as shown in FIG. 13b (k), the area turned on by the third photoresist pattern 414 is etched by an isotropic dry etching process. Here, half of the entire sacrificial layer including the conductor 412 & formation is etched to form the first trench 410. Next, as shown in FIG. 13c (l), after the epoxide 420 applied to the first trench 416 as a dielectric is thermoplasticized, and before the epoxide 420 is cured, it will be used for support. A ceramic plate 418 is adhered to the upper portion. Since the ceramic plate 418 is made of a hard material, the ceramic plate has a function of a supporting component for resisting a specific external force applied to the probe and avoiding deformation of the probe, and can achieve the function of maintaining the appearance of the probe. After the process of forming the epoxide 420 and the ceramic plate 418 is completed, the process on the plane a above the sacrificial plate 400 is completed. The remaining processes on the plane B below the sacrificial substrate 400 will now be described.
O:\89\89662.DOC -39- 200419159 接著如圖13c(m)所示,利用微影製程形成第四光阻圖案 424,以開啟犧牲基板400之下平面B上之中央部。 、 接著如圖13c(n)所示,以等向性乾蝕刻製程將利用第四光 阻圖案424開啟之區域蝕刻。在此蝕刻至包含導體4丨㉛形成 處在内之整體犧牲層的一半,藉以形成用以露出環氧化物 420之第二渠溝426。O: \ 89 \ 89662.DOC -39- 200419159 Then, as shown in FIG. 13c (m), a fourth photoresist pattern 424 is formed by a lithography process to open the central portion on the plane B below the sacrificial substrate 400. Next, as shown in FIG. 13c (n), the area opened by the fourth photoresist pattern 424 is etched in an isotropic dry etching process. Here, half of the entire sacrificial layer including where the conductor 4 is formed is etched to form a second trench 426 for exposing the epoxide 420.
而後如圖13d(o)所示,將施加於第二渠溝426中充作介電 質用之環氧化物428熱塑化。接著如圖中所示,與上平面A 類似,亦將由硬質材料構成之陶瓷板附接於犧牲基板4〇〇之 下平面B中之環氧化物428之上部上。 此外,如圖13 d(p)所示,利用預定化學物同時移除犧牲基 板400之上下平面上之光阻圖案414與424,接著利用化學物 如氫氧化鉀(KOH)及四甲基氫氧化氨(TMAH)選擇性姓刻其 餘犧牲基板4 0 〇。 結果即可依MEMS製程完成上下導體412a與412b呈交替 配置之用以測試平面板顯示器之導體。 換言之,用以形成圖l3b(k)中所示渠溝416與426之等向性 乾蝕刻製程,係使用具特定比例之”6、c4F8與〇2之混合氣 體之乾蝕刻製程。更特別言之,係利用所謂的波許製程施 仃蝕刻製程,其係一源自深渠溝蝕刻法之反應離子蝕刻 (RIE) 〇 在完成在犧牲基板4〇〇之上下平面a與B上施行之所有製 程後’即切割犧牲基板4〇〇,俾將犧牲基板4〇〇之上平面上 形成之複數個導體分割為具預定數量導體之預定單元之探Then, as shown in Fig. 13d (o), an epoxide 428 applied to the second trench 426 as a dielectric is thermally plasticized. Then, as shown in the figure, similar to the upper plane A, a ceramic plate made of a hard material is also attached on the upper part of the epoxide 428 in the lower plane B of the sacrificial substrate 400. In addition, as shown in FIG. 13 d (p), the photoresist patterns 414 and 424 on the upper and lower planes of the sacrificial substrate 400 are simultaneously removed by using a predetermined chemical, and then using chemicals such as potassium hydroxide (KOH) and tetramethyl hydrogen Ammonia oxide (TMAH) is selectively engraved with the remaining sacrificial substrate 400. As a result, the upper and lower conductors 412a and 412b, which are alternately arranged according to the MEMS process, can be used to test the conductors of the flat panel display. In other words, the isotropic dry etching process used to form the trenches 416 and 426 shown in FIG. 13b (k) is a dry etching process using a specific ratio of “6, c4F8, and 0 2 mixed gas. More specifically In other words, the so-called Bosch process is used to apply the etching process, which is a reactive ion etching (RIE) derived from the deep trench etching method. All of the operations performed on the planes a and B above the sacrificial substrate 400 are completed. After the process, the process of cutting the sacrificial substrate 400 is performed, and a method of dividing a plurality of conductors formed on a plane above the sacrificial substrate 400 into predetermined units with a predetermined number of conductors
O:\89\89662.DOC 200419159 針群。 換σ之,如圖25所示,切割犧牲基板4〇〇使得各導體群均 具12個導體,接著即形成探針。 特別σ之,在上平面Α上形成之各導體較在下平面Β上形 成之各體之一末端部像外突出,1向外突出部長度均 ^ 口此以别揭方法製造之探針,因施加於上下探針之 壓力均等而有利於探針操作。 依前揭方法製造之探針外型示如圖14。 圖14係闡釋以圖13所示製程製造之具單—犧牲基板之探 針之透視圖。 如圖14所示,導體36〇a與36〇b分別以對應之預定間隔平 订配置於犧牲基板之上下平面上。導體3術與係利用 傳導材料之嵌入以微影製程與蝕刻製程於矽犧牲基板之上 下平面上形成之第一渠溝中而形成。此外,均係由導電率 較該等導體高之材料製之薄層之傳導層,位於各導體廳 人360b之平面上,以改善導體360a與360b之傳導率。 此外,亚於探針之上下部上形成介電質刊“與%^。介 電質362a與362b係藉由施加介電質材料於以儀刻製程形成 於犧牲基板之兩平面上之第二渠溝中而形成。在此之介電 質材料為環氧化物較佳。 最終,在探針中具支撐組件364。支撐組件364係於介電 質362a與362b之至少—外平面上形成。支撐組件364係由硬 質材料構成較佳。支撐組件係藉由附接一陶竟板於介電質 362a與362b上而形成較佳。O: \ 89 \ 89662.DOC 200419159 needle group. In other words, as shown in FIG. 25, the sacrificial substrate 400 is cut so that each conductor group has 12 conductors, and then a probe is formed. In particular, the conductors formed on the upper plane A protrude outward than one of the ends of the bodies formed on the lower plane B, and the lengths of the outward protrusions are all ^ This is a probe manufactured by a separate method, because The pressure applied to the upper and lower probes is equal to facilitate probe operation. The appearance of the probe manufactured according to the previous method is shown in Figure 14. FIG. 14 is a perspective view illustrating a probe with a single-sacrificial substrate manufactured by the process shown in FIG. As shown in FIG. 14, the conductors 36a and 36b are arranged on the upper and lower planes of the sacrificial substrate at a predetermined interval. The conductor 3 is formed by embedding a conductive material in a first trench formed on a lower and upper plane of a silicon sacrificial substrate by a lithography process and an etching process. In addition, they are thin conductive layers made of materials with higher conductivity than these conductors, which are located on the plane of each conductor hall 360b to improve the conductivity of the conductors 360a and 360b. In addition, a dielectric journal "and% ^" is formed on the upper and lower portions of the probe. The dielectrics 362a and 362b are formed by applying a dielectric material to the second plane formed on the two planes of the sacrificial substrate by an inscription process. It is formed in a trench. The dielectric material here is preferably an epoxide. Finally, a supporting member 364 is provided in the probe. The supporting member 364 is formed on at least the outer plane of the dielectrics 362a and 362b. The supporting component 364 is preferably made of a hard material. The supporting component is preferably formed by attaching a ceramic plate to the dielectrics 362a and 362b.
O:\89\89662.DOC -41 - 200419159 (具體實施例2 - 6 ) 如圖15a(a)所示,將兩平面均經拋光之平坦矽(以)晶圓製 備為犧牲基板450。利用研磨製程或拋光製程所得之犧牲基 板450深度為4〇〇至500微米。 而後如圖15a(b)所示,利用濺鍍製程於犧牲基板45〇之整 個上平面A上形成第一種層452。此處之第一種層牦2係由= 5〇〇埃之鈦層與厚5,〇〇〇埃之銅層構成。銅層實質上係充作 後續電鍍製程中之種層。鈦層則係用以改善犧牲基板45〇與 銅層之黏著性。 接著如圖15a(c)所示,利用微影製程形成第一光阻圖荦 454,㈣犧牲基板45〇之上平面a上開啟預定形成導體處木。 接著如圖15a(d)所示,以電解質電鍍法沉積傳導材料如鎳 (Ni)或鎳合金(Ni_Co、Ni_w_c〇)而形成第一導體#%。 接著如圖15a(e)所示,藉由移除第一導體456之上平面之 不均勻部而將其上平面平坦化。平坦化製程係利用化學機 械拋光(CMP)法、研磨法、折疊法、拋光法及研磨法等施行。 但在用以形成第一導體456之理想電鍍製程之進程中,僅 於利用第一光阻圖案454開啟處形成第一導體456之情況 下,平坦化製程即可略之。 此外,在利用除電鍍製程外之方法如物理汽相沉積 與化學汽相沉積(CVD)形成第一導體456之情況下’先前形 成第一種層452之製程即可略之。 而後如圖15a(e)所示,於第一導體456之上部上施行鍍金 製程,藉以形成第一鍍金層458。此製程之目的係在改善探O: \ 89 \ 89662.DOC -41-200419159 (Specific embodiments 2-6) As shown in Fig. 15a (a), a flat silicon wafer with both surfaces polished is prepared as a sacrificial substrate 450. The sacrificial substrate 450 obtained by a grinding process or a polishing process has a depth of 400 to 500 microns. Then, as shown in Fig. 15a (b), a first layer 452 is formed on the entire upper plane A of the sacrificial substrate 45 by a sputtering process. The first layer 牦 2 here is composed of a titanium layer = 500 Angstroms and a copper layer 5,000 Angstroms thick. The copper layer is essentially used as a seed layer in the subsequent electroplating process. The titanium layer is used to improve the adhesion between the sacrificial substrate 45 and the copper layer. Next, as shown in FIG. 15a (c), a first photoresist pattern 荦 454 is formed by using a lithography process, and a plane where a conductor is to be formed is opened on the plane a above the sacrificial substrate 45 °. Next, as shown in FIG. 15a (d), a conductive material such as nickel (Ni) or a nickel alloy (Ni_Co, Ni_w_co) is deposited by an electrolytic plating method to form a first conductor #%. Next, as shown in Fig. 15a (e), the upper plane of the first conductor 456 is flattened by removing uneven portions of the plane above the first conductor 456. The planarization process is performed using a chemical mechanical polishing (CMP) method, a polishing method, a folding method, a polishing method, and a polishing method. However, in the process of forming an ideal plating process for forming the first conductor 456, the planarization process may be omitted only in the case where the first conductor 456 is formed using the first photoresist pattern 454 turned on. In addition, in the case where the first conductor 456 is formed using a method other than the plating process such as physical vapor deposition and chemical vapor deposition (CVD), the process of forming the first layer 452 previously may be omitted. Then, as shown in Fig. 15a (e), a gold plating process is performed on the upper portion of the first conductor 456 to form a first gold plating layer 458. The purpose of this process is to improve exploration
O:\89\89662.DOC -42- 200419159 針之傳導率。 而後如圖15a⑴所示,利用濕姓刻製程移除第一光阻圖案 454。在此亦移除第一種層Μ?之外露部。 ’、 接著如®15a(g)所示,利賴影製程形成第二光阻圖宰 460,以開啟第一導體456之預定部。 木 接著如圖15a(h)所示,施加具黏著劑功能之熱塑性環氧化 物462於第-導體456上利用第二光阻圖案46〇開啟處。 而後如圖15b⑴所在環氧化物偏固化前,附接陶竟 板4 6 4於環氧化物4 6 2之上部上。 接著如圖15b⑴所示,利用研磨製程將陶瓷板牝4之上平 面平坦化。此處之平坦化製程與第一具體實施例相同。當 完成平坦化製程後,即完成在犧牲基板45〇之上平面A上之 製程。 現將描述在犧牲基板450之下平面b上之製程。 首先如圖15b(k)所示,犧牲基板45〇面朝下。 接著如圖15b(l)所示,利用研磨製程將犧牲基板45〇之下 平面B移除至犧牲基板450原始厚度的一半。因此,在研磨 製程後,所餘犧牲基板深度範圍約在240至250微米間。 接著如圖15b(m)所示,利用微影製程形成第三光阻圖案 466 ’以開啟犧牲基板450之下平面B上預定形成介電質處。 而後如圖15b(n)所示,利用非等向性乾蝕刻製程將利用第 三光阻圖案466開啟之犧牲基板450之預定部移除,藉以形 成渠溝467。同時間亦移除種層452。 而後如圖15b(o-l)所示,將充作介電質之熱塑性環氧化物 O:\89\89662.DOC -43- 200419159 468施加於渠溝467中。 利用研磨製程將環氧化物之上平 而後如圖15b(p-1)所示 面平坦化。 接著如圖15c(q-l)所示,以渴蝕列制 八,、、蚀刻製耘移除第二光阻圖案 460及第三光阻圖案466,並以採用k〇h之難刻製程移除 犧牲基板450之其餘部份,藉以完成依本發明之單層探針。 在此形成之導體可具有自陶奢拓 J ^板464申央向兩側突出之 等長部。 現將描述依本發明之雙層探針製造方法。 接著如圖15c(〇-2)所示,在完成圖⑽⑻之製程之狀態 下,在將充作介電質與黏著劑之環氧化物47〇加入渠溝w 中後’並在環氧化物470固化前,附接陶瓷板472。雖鈇所 附接之陶·與渠溝467外型類似為矩形平行六面體,Μ 亦可為平行四邊形陶竟板81〇,其中兩端811與8ΐ2傾斜如圖 2U所示;或可為步階形陶究板82〇,其兩端821與μ]為步 階形,如圖21b所示。結果在所製探針中,導體之向外突出 邛等長,故在板針操作期間,施加於所有探針針部處之壓 力相同。 接者如圖15c(p-2)所示,利用研磨製程將陶瓷板上平 面平坦化。此處之平坦化製程可與第一具體實施例相同。 而後如圖15d(q-2)所示,在犧牲基板45〇之下平面B平坦化 =,於犧牲基板450之整個下平面6上形成供導體形成電鍍 製程用之第二種層474。此處之第二種層474係由厚5〇〇埃之 鈦層及厚5,0〇〇埃之銅層似。銅層實質充作後續電錢製程O: \ 89 \ 89662.DOC -42- 200419159 Needle conductivity. Then, as shown in FIG. 15a (a), the first photoresist pattern 454 is removed by a wet last engraving process. The exposed part of the first layer M? Is also removed here. Then, as shown in ®15a (g), the Lee Lai film process forms a second photoresist pattern 460 to open a predetermined portion of the first conductor 456. Next, as shown in Fig. 15a (h), a thermoplastic epoxide 462 having an adhesive function is applied to the first conductor 456 with a second photoresist pattern 46o opened. Then, as shown in Fig. 15b, before the epoxide is partially cured, a ceramic plate 4 6 4 is attached on the upper part of the epoxide 4 6 2. Next, as shown in FIG. 15b (a), the planar surface on the ceramic plate (4) is planarized by a grinding process. The planarization process here is the same as the first embodiment. When the planarization process is completed, the process on the plane A above the sacrificial substrate 45 is completed. The process on the plane b below the sacrificial substrate 450 will now be described. First, as shown in FIG. 15b (k), the sacrificial substrate 45 is faced down. Next, as shown in FIG. 15b (l), the plane B below the sacrificial substrate 45 is removed to half of the original thickness of the sacrificial substrate 450 by a polishing process. Therefore, after the grinding process, the remaining sacrificial substrate depth range is about 240 to 250 microns. Next, as shown in FIG. 15b (m), a third photoresist pattern 466 'is formed by a photolithography process to open a predetermined dielectric portion on the plane B below the sacrificial substrate 450. Then, as shown in FIG. 15b (n), a predetermined portion of the sacrificial substrate 450 opened by the third photoresist pattern 466 is removed by using an anisotropic dry etching process to form a trench 467. The seed layer 452 is also removed at the same time. Then, as shown in FIG. 15b (o-1), a thermoplastic epoxy O: \ 89 \ 89662.DOC-43-200419159 468 as a dielectric is applied to the trench 467. The top surface of the epoxide is planarized by a polishing process, and then the surface is planarized as shown in Fig. 15b (p-1). Next, as shown in FIG. 15c (ql), the second photoresist pattern 460 and the third photoresist pattern 466 are removed by etching, and the etching process is performed to remove the second photoresist pattern 460 and the third photoresist pattern 466. The rest of the substrate 450 is sacrificed to complete the single-layer probe according to the present invention. The conductor formed here may have an equal length portion protruding from both sides of Tao Shetuo J ^ Plate 464 Shenyang. A method for manufacturing a double-layered probe according to the present invention will now be described. Next, as shown in FIG. 15c (〇-2), in the state of completing the process of FIG. 1, after adding epoxide 47, which is a dielectric and an adhesive, to the trench w ′, and then the epoxide Before 470 is cured, ceramic plate 472 is attached. Although the attached pottery is similar to a rectangular parallelepiped in appearance to the trench 467, M can also be a parallelogram pottery plate 81 °, in which both ends 811 and 8ΐ2 are inclined as shown in Figure 2U; or A step-shaped ceramic research board 82, the ends 821 and μ] of which are step-shaped, as shown in FIG. 21b. As a result, in the produced probes, the conductors protrude outwards and are of equal length. Therefore, during the pin operation, the pressure applied to all probe pins is the same. As shown in Fig. 15c (p-2), the flat surface of the ceramic plate is flattened by a polishing process. The planarization process here may be the same as that in the first embodiment. Then, as shown in FIG. 15d (q-2), the plane B is flattened under the sacrificial substrate 450, and a second layer 474 for forming a conductor is formed on the entire lower plane 6 of the sacrificial substrate 450. The second layer 474 here is similar to a titanium layer having a thickness of 500 angstroms and a copper layer having a thickness of 5,000 angstroms. The copper layer is essentially used as a subsequent electricity money process
O:\89\89662.DOC -44- 200419159 中之種層。鈦層則係心改善犧牲基板45g與銅層之黏著 性。 接著如圖15d(q-2)所示,在形成第二種層474時,利用微 影製程形成第四光阻圖案476,以開啟犧牲基板45〇之下平 面B上預定形成導體處。 利用電解質電鍍法沉積傳導材料 Ni-W-Co)而形成第二導體478。 接著如圖15d(r-2)所示 如鎳(Ni)或鎳合金(Ni_c〇 接著如圖15d(S_2)所示,藉由移除第二導體478上平面之 不均句部而將其上平面平坦化。此處施行之平坦化製程鱼 第-具體實施例採用之方法相同。但在用以形成第二導體 谓之理想電鑛製程之進程中,僅於第四光阻圖案μ之開 啟部内形成導體之情況下,平坦化製程可略之。 此外,在利用除電鍍製程外之方法如物理汽相沉積(pvD) 與化學汽相沉積(CVD)形成第二導體478之情況下,由於無 需前述種層,故形成第二種層474之製程即可略之。而後: 第二導體478之上部上施行鑛金製程,藉以形成第二鑛金層 480。此製程之目的在改善探針之傳導率。 而後如圖15d(t-2)所示,利用濕钮刻製程移除第四光阻圖 案467。同時間亦將自導體478向外突出之第二種層μ移 除。接著利用微影製程形成第五光阻圖案482,以開啟第二 導體478中預定形成支撐組件處。 接著如圖15d(U-2)所示,將熱塑性環氧化物484施加於利 用第五光阻圖案482開啟之部分第二導體478上。 而後如圖15e(v-2)所示,利用研磨製程將所施加之環氧化 O:\89\89662.DOC -45- 2UU419159 之上平面平坦化。此處之平坦化製程與第一具體實施 例相同。 而後如目15e(w_2)所示,利用濕颠刻製程移除第五與第二 光阻圖案482與460。 取〜’而後如圖15e(x-2)所示,以使用K〇H之濕餘刻製程 移除矽犧牲基板450之殘餘部分。 依前述方法製造之探針外型示如圖16。 圖16係闡釋以圖15所示製程,利用單—犧牲基板製造之 探針結構。 依圖15中之製程製造之探針包括在中央部之介電質 、不如圖16。藉由附接環氧化物370a與陶瓷板370b而形 成戒私貝370。換言之,利用蝕刻製程於犧牲基板之預訂部 上形成渠溝,將環氧化物37〇a施加於渠溝中,並在環氧化 物固化前,插入與附接陶:是板3·,藉以形成介電質37〇。 此處之環氧化物37〇a係充作黏著劑之用。 此外,以預定間隔將導體372a與372b平行配置於介電質 570之上下平面上。利用微影製程於犧牲基板之上下平面上 之預:部上形成第一保護膜圖案,接著將傳導材料沉積於 利用第保達膜圖案開啟之區域,藉以形成導體372a與 372b。此處,在以電解質電鍍法形成傳導材料之情況下,、 預先於犧牲基板之上下平面上形成種層。 此外,由導電率較導體372&與37孔高之材料製成之傳導 層374a與374b,係位於導體372a與37孔之一平面上,以改 善導體傳導率。此處之傳導材料為金(Au)較佳。O: \ 89 \ 89662.DOC -44- 200419159 seed layer. The titanium layer is designed to improve the adhesion between the sacrificial substrate 45g and the copper layer. Next, as shown in FIG. 15d (q-2), when the second layer 474 is formed, a fourth photoresist pattern 476 is formed by a lithography process to open a predetermined conductor on the plane B below the sacrificial substrate 45 °. A second conductive material 478 is formed by depositing a conductive material (Ni-W-Co) using an electrolytic plating method. Next, as shown in FIG. 15d (r-2), as shown in nickel (Ni) or a nickel alloy (Ni_c〇), as shown in FIG. 15d (S_2), the second conductor 478 is removed by removing uneven portions on the plane of the second conductor 478. The upper plane is flattened. The flattening process performed here is the same as that used in the specific embodiment. However, in the process of forming the ideal electric mine process for forming the second conductor, only the fourth photoresist pattern μ is used. In the case where a conductor is formed in the opening portion, the planarization process may be omitted. In addition, in a case where the second conductor 478 is formed using a method other than the plating process such as physical vapor deposition (pvD) and chemical vapor deposition (CVD), Since the aforementioned layers are not required, the process of forming the second layer 474 can be omitted. Then: A gold mining process is performed on the upper part of the second conductor 478 to form the second gold layer 480. The purpose of this process is to improve the exploration. The conductivity of the needle is then removed, as shown in FIG. 15d (t-2), using a wet button process to remove the fourth photoresist pattern 467. At the same time, the second layer μ protruding outward from the conductor 478 is also removed. Then, a fifth photoresist pattern 482 is formed by a photolithography process to turn on the second conductor 478. A support component is scheduled to be formed. Next, as shown in FIG. 15d (U-2), a thermoplastic epoxide 484 is applied to a portion of the second conductor 478 opened by the fifth photoresist pattern 482. Then, as shown in FIG. 15e (v-2 As shown in the figure, the applied epoxidized O: \ 89 \ 89662.DOC -45-2UU419159 is planarized by a grinding process. The planarization process here is the same as that of the first embodiment. Then, as shown in head 15e ( As shown in w_2), the fifth and second photoresist patterns 482 and 460 are removed by a wet inversion process. Take ~ 'and then use FIG. 15e (x-2) to use the wet residual etching process shift. The remaining part of the silicon sacrificial substrate 450 is removed. The appearance of the probe manufactured according to the aforementioned method is shown in Figure 16. Figure 16 illustrates the structure of a probe manufactured using a single-sacrificial substrate using the process shown in Figure 15. According to Figure 15 The probe manufactured by the manufacturing process includes a dielectric in the central part, not as shown in Figure 16. An anti-corrosive shell 370 is formed by attaching an epoxy 370a and a ceramic plate 370b. In other words, an etching process is used to form a predetermined portion on a sacrificial substrate. Trench, applying epoxide 37〇a to the trench, and before the epoxy solidifies, Entry and attachment ceramics: It is plate 3 ·, so as to form the dielectric 37 °. Here, the epoxide 37〇a is used as an adhesive. In addition, the conductors 372a and 372b are arranged in parallel at a predetermined interval in the dielectric. Capacitor 570 on the upper and lower planes. A lithography process is used to form a first protective film pattern on the upper and lower planes of the sacrificial substrate, and then a conductive material is deposited on the area opened with the first film pattern to form a conductor. 372a and 372b. Here, when a conductive material is formed by an electrolytic plating method, a seed layer is formed in advance on the upper and lower planes of the sacrificial substrate. In addition, the conductive layers 374a and 374b made of a material having higher conductivity than the conductors 372 & and 37 holes are located on one of the planes of the conductors 372a and 37 to improve the conductivity of the conductors. The conductive material here is preferably gold (Au).
O:\89\89662.DOC -46- 200419159 最終’於介電質之上下平面上形成支撐組件37以與 376b,俾保護與固定導體372a與372b。支撐組件376a與376b 係由環氧化物或以環氧化物附接與固定之陶瓷構成較佳。 以代號3 7 8表示支撐板。 (具體實施例2-7) 如圖17a(a)所示,將矽晶圓之兩平面拋光,以製備為犧牲 基板550。利用研磨製程或拋光製程製成之犧牲基板55〇厚 400至500微米。 而後如圖17a(b)所示,利用微影製程形成第一光阻圖案 5 52 ’已開啟犧牲基板55〇之預定形成介電質處。 而後如圖17a(c)所示,利用第一光阻圖案552蝕刻犧牲基 板550之上平面a至預定深度,以形成渠溝551。此處之蝕刻 深度範圍在240至250微米,較欲形成之介電質之厚度24〇微 米略深。 接著如圖圖17a(d)所示,在將充作介電質與黏著劑用之環 =化物554施加於渠溝551中之後,並在環氧化物551固化 前,附接陶竟板556。雖然所附接之陶質板之外型與渠溝551 類似為矩形平行六面體,但陶瓷板82〇亦可為兩端Μ〗與M2 傾斜如圖2U所示之平行四邊形,或者陶究板82〇可為兩端 821與822為步階狀之步階形。結果在所製探針中,導體向 外突出部長度相同,使得探針操作期間施加於所有探針針 部之壓力均等。 而後如圖17a⑷所示,利用研磨製程將陶究板⑽之上平 面平坦化。此處之平坦化製程與第—具體實施例相同。在O: \ 89 \ 89662.DOC -46- 200419159 Finally, a support assembly 37 is formed on the upper and lower planes of the dielectric to protect and fix the conductors 372a and 372b. The support components 376a and 376b are preferably made of epoxide or ceramics attached and fixed with epoxide. The support plate is denoted by the code 3 7 8. (Specific embodiment 2-7) As shown in Fig. 17a (a), two planes of a silicon wafer are polished to prepare a sacrificial substrate 550. The sacrificial substrate 55 manufactured by a grinding process or a polishing process is 400 to 500 microns thick. Then, as shown in FIG. 17a (b), a first photoresist pattern 5 52 'is formed by a photolithography process, and a predetermined dielectric portion where the sacrificial substrate 55 is turned on is formed. Then, as shown in Fig. 17a (c), the first photoresist pattern 552 is used to etch the plane a above the sacrificial substrate 550 to a predetermined depth to form a trench 551. The etching depth here ranges from 240 to 250 microns, which is slightly deeper than the thickness of the dielectric to be formed, which is 240 microns. Next, as shown in FIG. 17a (d), after applying the ring = 554, which is used as a dielectric and an adhesive, in the trench 551, and before the epoxy 551 is cured, a ceramic plate 556 is attached. . Although the attached ceramic plate has a rectangular parallelepiped shape similar to the trench 551, the ceramic plate 82 can also be a parallelogram inclined at both ends M and M2 as shown in Figure 2U, or ceramic The plate 820 may have a step shape with both ends 821 and 822 stepped. As a result, in the manufactured probe, the length of the outwardly protruding portion of the conductor is the same, so that the pressure applied to all the probe pins during the probe operation is equal. Then, as shown in FIG. 17a (a), the planar surface above the ceramic plate (⑽) is flattened by a grinding process. The planarization process here is the same as the first embodiment. in
O:\89\89662.DOC -47- 200419159 將陶究板556之上平面平坦化時,利用_製程於犧牲基板 550的整個上平面A形成供導體形成電鍍製程用之第声 558。 9 此處之第一種層558係由厚500埃之鈦層與厚5,〇〇〇埃之 銅層構成。銅層實質上係充作後續電鍍製程中之種層。'鈦 層則係用以改善犧牲基板550與銅層之黏著性。 接著如圖17a(f)所示,利用微影製程形成第二光阻圖案 560,以則羲牲基板550之上平面a上開啟預定形成導體處: 接著如圖17a(g)所示,以電解質電鍍法沉積傳導材料如鎳 (Ni)或鎳合金(Ni-Co、Ni_w_c〇)而形成第一導體%〕。 接著如圖17a(h)所示,藉由移除第一導體562之上平面之 不均勻部或過量形成部而將其上平面平坦化。此處之平坦 化製程與第一具體實施力所揭方法相同。 但在用以形成第一導體之理想電鍍製程之進程中,僅 於利用第二光阻圖案560開啟處形成導體之情況下,平坦化 製程即可略之。 此外在利用除電鐘製程外之方法如物理汽相沉積 與化學汽相沉積(CVD)形成第一導體562之情況下,形成第 一種層558之製程即可略之。 而後如圖17b(i)所示,於第一導體562之上部上施行鍍金 製程,藉以形成第一鍍金層564。此製程之目的係在改善探 針之傳導率。 而後如圖17b⑴所示,形成第一保護膜566以保護在犧牲 基板55〇之上平面A上形成之第一導體562,以及第一鍍金層O: \ 89 \ 89662.DOC -47- 200419159 When flattening the upper surface of the ceramic plate 556, the entire upper plane A of the sacrificial substrate 550 is used to form the sound 558 for the conductor forming plating process. 9 The first layer 558 here is composed of a titanium layer with a thickness of 500 angstroms and a copper layer with a thickness of 5,000 angstroms. The copper layer is essentially used as a seed layer in the subsequent electroplating process. 'The titanium layer is used to improve the adhesion between the sacrificial substrate 550 and the copper layer. Next, as shown in FIG. 17a (f), a second photoresist pattern 560 is formed by a lithography process, so that a predetermined conductor is opened on the plane a above the substrate 550: Next, as shown in FIG. The electrolytic plating method deposits a conductive material such as nickel (Ni) or a nickel alloy (Ni-Co, Ni_w_c0) to form a first conductor%]. Next, as shown in Fig. 17a (h), the upper plane of the first conductor 562 is flattened by removing uneven portions or excessively formed portions of the plane above the first conductor 562. The planarization process here is the same as the method disclosed in the first embodiment. However, in the course of the ideal plating process for forming the first conductor, the planarization process can be omitted only in the case where the conductor is formed by using the opening of the second photoresist pattern 560. In addition, in the case where the first conductor 562 is formed using a method other than the clock process such as physical vapor deposition and chemical vapor deposition (CVD), the process of forming the first layer 558 may be omitted. Then, as shown in FIG. 17b (i), a gold plating process is performed on the upper portion of the first conductor 562 to form a first gold plating layer 564. The purpose of this process is to improve the conductivity of the probe. Then, as shown in FIG. 17 (b), a first protective film 566 is formed to protect the first conductor 562 formed on the plane A above the sacrificial substrate 55 and the first gold plating layer.
O:\89\89662.DOC -48- 200419159 564。在此係以膠帶或光阻充作保護膜。 結果即已完成犧牲基板550之上平面A上之製程,接著開 始在其下平面B上之製程。 首先如圖17b(k)所示,犧牲基板55〇面朝下,並利用研磨 或拋光法研磨犧牲基板550之下平面B。將犧牲基板550研磨 至得以露出陶瓷板556之厚度。 接著如圖17b(l)所示,於犧牲基板55〇之整個下平面b上形 成供導體形成電鍍製程用之第二種層568。而後利用微影製 程形成第三光阻圖案570,以開啟犧牲基板55〇之下平面b 上預定形成導體部。 而後如圖17b(m)所示,於利用第三光阻圖案570開啟處上 形成第二導體572。 接著如圖17b(n)所示,若第二導體572之上平面不均勻, 則於其上平面上施行平坦化製程。在此之平坦化製程與第 一具體實施力所揭方法相同。 但在用以形成第二導體572之理想電鐘製程之進程中,僅 於第二光阻圖案570之開啟部内形成第二導體572之情況 下,平坦化製程可略之。 此外’在利用除電鍍製程外之方法如物理汽相沉積(PVD) 與化學汽相沉積(CVD)形成第二導體572之情況下,先前形 成第二種層568之製程可略之。 而後如圖17b(o)所示,於第二導體572之上平面上施行鍍 金製程’藉以形成第二鍍金層574。此製程之目的在改善探 針傳導率。而後利用濕蝕刻製程將在犧牲基板550之上平面O: \ 89 \ 89662.DOC -48- 200419159 564. Here is a protective film with tape or photoresist. As a result, the process on the plane A above the sacrificial substrate 550 has been completed, and then the process on the plane B below it has begun. First, as shown in FIG. 17b (k), the sacrificial substrate 55 is faced downward, and the plane B below the sacrificial substrate 550 is polished by grinding or polishing. The sacrificial substrate 550 is polished to a thickness where the ceramic plate 556 is exposed. Next, as shown in Fig. 17b (l), a second layer 568 is formed on the entire lower plane b of the sacrificial substrate 55 for the conductor forming plating process. Then, a third photoresist pattern 570 is formed by a lithography process to turn on the conductor portion that is scheduled to be formed on the plane b below the sacrificial substrate 55. Then, as shown in FIG. 17b (m), a second conductor 572 is formed on the place where the third photoresist pattern 570 is opened. Next, as shown in FIG. 17b (n), if the plane above the second conductor 572 is not uniform, a planarization process is performed on the upper plane. The planarization process here is the same as the method disclosed in the first implementation. However, in the process of forming an ideal electric clock for forming the second conductor 572, only in the case where the second conductor 572 is formed in the opening portion of the second photoresist pattern 570, the planarization process can be omitted. In addition, in the case where the second conductor 572 is formed using a method other than the electroplating process, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), the previous process of forming the second layer 568 can be omitted. Then, as shown in Fig. 17b (o), a gold plating process is performed on the plane above the second conductor 572 to form a second gold plating layer 574. The purpose of this process is to improve probe conductivity. Then, the wet etching process will be used to planarize the substrate 550.
O:\89\89662.DOC -49- 200419159 A上形成之第-保護膜移除,並同時移除第二與第三光阻圖 案560與570。在此亦移除第二種層568之外露部。 第四光阻圖案578,以開啟第二導體572上預㈣成支樓組 件處。 而後如圖17C⑻所示,於犧牲基板㈣之上平面A上形成 第二保護膜576,以保護上平面a。接著利用微影製程形成 接著而後如圖i7c⑷所示,將熱塑性環氧化物58〇施加於 利用第四光阻圖案578開啟處。 而後如圖17c(r)所示,利用研磨製程將環氧化物58〇之上 平面平坦化。平坦化製程與第一具體實施例相同。 而後如圖17c(s)所示,將犧牲基板55〇之上平面a上之第 二保護膜576移除。接著形成第五光阻圖案582,以開啟第 一導體562之預定形成支撐組件處。 接著如圖17c(t)所示,施加熱塑性環氧化物5料於利用第 五光阻圖案582開啟處,接著利用研磨製程將環氧化物π* 之上平面平坦化。 最終如圖17c(u)所示,以濕蝕刻製程同時移除第四與第五 光阻圖案578與582,並以使用K0N之濕蝕刻製程選擇性移 除第一與第二導體562與572間之犧牲基板55〇殘餘部分。 在移除犧牲基板550後,即完成本發明之探針。 (具體實施例2-8) 如圖18a所示,將兩平面被拋光之矽晶圓製備為犧牲基板 ,以研磨製程或拋光製程製備之犧牲基板65〇厚24〇微 米0O: \ 89 \ 89662.DOC -49- 200419159 A The first protective film formed on A is removed, and the second and third photoresist patterns 560 and 570 are removed at the same time. The exposed part of the second layer 568 is also removed here. The fourth photoresist pattern 578 is used to turn on the second conductor 572 to form a branch component. Then, as shown in FIG. 17C (a), a second protective film 576 is formed on the plane A above the sacrificial substrate ㈣ to protect the upper plane a. Next, it is formed by a lithography process. Then, as shown in FIG. I7c⑷, a thermoplastic epoxide 58 is applied to a place where the fourth photoresist pattern 578 is opened. Then, as shown in FIG. 17c (r), a plane above the epoxide 58 is planarized by a polishing process. The planarization process is the same as the first embodiment. Then, as shown in Fig. 17c (s), the second protective film 576 on the plane a above the sacrificial substrate 55 is removed. Then, a fifth photoresist pattern 582 is formed to turn on the first conductive support 562 at a predetermined formation supporting component. Next, as shown in FIG. 17c (t), a thermoplastic epoxide material 5 is applied to the place where the fifth photoresist pattern 582 is opened, and then a plane above the epoxide π * is planarized by a grinding process. Finally, as shown in FIG. 17c (u), the fourth and fifth photoresist patterns 578 and 582 are simultaneously removed by a wet etching process, and the first and second conductors 562 and 572 are selectively removed by a wet etching process using KON. The remaining portion of the sacrificial substrate 55 is left in between. After the sacrificial substrate 550 is removed, the probe of the present invention is completed. (Specific embodiment 2-8) As shown in FIG. 18a, a silicon wafer whose two planes are polished is prepared as a sacrificial substrate, and a sacrificial substrate prepared by a grinding process or a polishing process is 65 mm thick and 24 mm thick.
O:\89\89662.DOC -50- 200419159 接著如圖18a(b)所示,將犧牲基板65〇之下平面6附接— 膠帶以避免污染,或者塗佈一塗佈材料652如光阻於其上。 接著如圖18a(c)所示,利用切方製程以預定外型沿切割部 653切割犧牲基板650之中央部。 接著如圖1 8a(d)所示,將以切方製程產生具預定尺寸之犧 牲基板區塊654,亦即中央矽區塊,自犧牲基板65〇移除。 結果即在犧牲基板650之中央部上形成渠溝655。 接著如圖18a(e)所示,將充作介電質用之陶瓷板656插入 渠溝655中,接著施加環氧化物658,將之嵌入陶瓷板656與 犧牲基板650間之間隙中。此處之環氧化物具有附接陶瓷板 565與犧牲基板650之功能。 接著如圖18a(f)所示’將犧牲基板650之上平面a平坦化。 接著如圖18a(g)所示,將在犧牲基板650之下平面b上形 成之塗佈材料652移除,並與犧牲基板650之上平面a類似, 將下平面B平坦化。 接著如圖18a(h)所示,於犧牲基板650之整個下平面b上 形成供導體形成電鑛製程用之第一種層660與662。 此處之第一種層660與662係由厚500埃之鈦層及厚5,〇〇〇 埃之銅層構成。銅層係充作後續電鍍製程中電鍍之種層 用’鈦層則係用以改善犧牲基板650與銅層間之黏著性。 接著如圖18a(i)所示,於犧牲基板650之下平面B上形成用 以保護種層662之第一保護膜667,並利用微影製程於犧牲 基板650之上平面a上形成第一光阻圖案664,以開啟犧牲基 板650之預定導體形成處。O: \ 89 \ 89662.DOC -50- 200419159 Next, as shown in Fig. 18a (b), attach the flat surface 6 below the sacrificial substrate 65 °-tape to avoid contamination, or apply a coating material 652 such as photoresist On it. Next, as shown in FIG. 18a (c), the center portion of the sacrificial substrate 650 is cut along the cutting portion 653 with a predetermined shape by a tangent process. Then, as shown in FIG. 18a (d), a sacrifice process is used to generate a sacrificial substrate block 654 with a predetermined size, that is, a central silicon block, and removed from the sacrificial substrate 65. As a result, a trench 655 is formed in the central portion of the sacrificial substrate 650. Next, as shown in Fig. 18a (e), a ceramic plate 656 serving as a dielectric is inserted into the trench 655, and then an epoxide 658 is applied and embedded in the gap between the ceramic plate 656 and the sacrificial substrate 650. The epoxide here has a function of attaching the ceramic plate 565 and the sacrificial substrate 650. Next, as shown in Fig. 18a (f), the plane a above the sacrificial substrate 650 is flattened. Next, as shown in FIG. 18a (g), the coating material 652 formed on the plane b below the sacrificial substrate 650 is removed, and similar to the plane a above the sacrificial substrate 650, the lower plane B is planarized. Next, as shown in FIG. 18a (h), the first layers 660 and 662 for forming a conductor for the electroless process are formed on the entire lower plane b of the sacrificial substrate 650. The first layers 660 and 662 here are composed of a titanium layer with a thickness of 500 angstroms and a copper layer with a thickness of 5,000 angstroms. The copper layer is used as a seed layer for electroplating in the subsequent electroplating process. The titanium layer is used to improve the adhesion between the sacrificial substrate 650 and the copper layer. Next, as shown in FIG. 18a (i), a first protective film 667 for protecting the seed layer 662 is formed on the plane B below the sacrificial substrate 650, and a first process is formed on the plane a above the sacrificial substrate 650 by a lithography process. The photoresist pattern 664 opens a predetermined conductor formation portion of the sacrificial substrate 650.
O:\89\89662.DOC -51 - 200419159 而後如圖18a⑴所示,於利用第一光阻圖案_開啟處上 形成第一導體666。此處之第一導體666係藉由電解質電鍍 法沉積傳導材料如鎳(Ni)或鎳合金(Ni_c〇、Ni_w_c…而形 成。 接著如圖18b(k)所示,藉由移除第一導體666之上平面之 不均勻處而將第一導體666之上平面平坦化。在此之平坦化 製程與第一具體實施例所揭方法相同。 但在用以形成第一導體666之理想電鍍製程之進程中,僅 於第一光阻圖案664之開啟部内形成第一導體666之情況 下,平坦化製程即可略之。 而後於第一導體666之整個上部上施行鍍金製程,藉以形 成一第一鍵金層668。 此外,在利用除電鍍製程外之方法如物理汽相沉積 與化學汽相沉積(CVD)形成第一導體666之情況下,由於無 舄種層,故先鈾形成弟一種層660之製程可略之。 接著如圖18b(l)所示,利用膠帶或光阻於形成第一導體 666處形成用以保護犧牲基板65〇之上平面A之第二保護膜 670。在完成第二保護膜670之形成後,即完成在犧牲基板 650之上平面A上之第一製程。而後將犧牲基板朝下,接著 移除用以保護犧牲基板650之下平面之保護膜a?。 現將描述犧牲基板650之下平面b上之製程。 接著如圖18b(m)所示,利用微影製程形成第二光阻圖案 672,以開啟犧牲基板650之下平面B上預定形成導體處。 接著如圖18b(n)所示,於利用第二光阻圖案672開啟部上 O:\89\89662.DOC -52- 200419159 形成第二導體674。此處係利用電鍍製程沉積傳導材料如鎳 (Ni)或錄合金(Ni_Co、Ni|C〇)而形成第二導體⑺。 接著如圖18b⑷所示,藉由移除第二導體㈣之上平面之 不均勻處,將其上平面平坦化。此處之平坦化製程與第一 具體貫施例所揭方法相同。在平坦化製程完成後,於第二 導體674之整個上部上施行鍍金製程,藉以形成第二鍍金層 676。 9 但在用以形成第二導體674之理想電路製程之進程中,僅 於利用第二光阻圖案672開啟處内形成導體之情況下,平坦 化製程即可略之。 此外,在利用除電錢製程外之方法如物理汽相沉積(ρ, 與化學汽相沉積(CVD)形成第二導體674之情況下,先前形 成種層662之製程可略之。 接著如圖18b(P)所示,利用濕敍刻製程移除第二光阻圖宰 672。在此亦移除第二種層奶之外露部。此外,可同時移 除受第二保護膜670保護之第一光阻圖案664。 接著如圖18b(q)所示,㈣微影製程形成第三光阻圖案 678 ’以開啟第二導體674中預定形成支撐組件處。 •接著如圖18c⑴所示’利用第三光阻圖案678為模,施加 壞氧化物680於第二導體674之開啟部。 接著如圖18c(s)所示’利用研磨製程將環氧化物68〇之上 平面平坦化。 接著如圖18C⑴所*,移除在犧牲基板650之上平面a上形 成之第二保護膜67〇。接著利用濕蚀刻製程移除第一光阻圖O: \ 89 \ 89662.DOC -51-200419159 Then as shown in Fig. 18a⑴, a first conductor 666 is formed on the place where the first photoresist pattern _ is opened. Here, the first conductor 666 is formed by depositing a conductive material such as nickel (Ni) or a nickel alloy (Ni_co, Ni_w_c, etc.) by an electrolytic plating method. Then, as shown in FIG. 18b (k), the first conductor is removed The unevenness of the plane above 666 planarizes the plane above the first conductor 666. The planarization process here is the same as the method disclosed in the first embodiment. However, the ideal plating process used to form the first conductor 666 In the process, only in the case where the first conductor 666 is formed in the opening portion of the first photoresist pattern 664, the planarization process can be omitted. Then, a gold plating process is performed on the entire upper portion of the first conductor 666 to form a first A bond gold layer 668. In addition, in the case where the first conductor 666 is formed by a method other than the electroplating process such as physical vapor deposition and chemical vapor deposition (CVD), since there is no plutonium seed layer, uranium is first formed. The manufacturing process of the layer 660 can be omitted. Next, as shown in FIG. 18b (l), a second protective film 670 is formed on the first conductor 666 to protect the plane A on the sacrificial substrate 65 by using tape or photoresist. Complete the formation of the second protective film 670 That is, the first process on the plane A above the sacrificial substrate 650 is completed. Then, the sacrificial substrate is directed downward, and then the protective film a? For protecting the plane below the sacrificial substrate 650 is removed. The process on the plane b. Next, as shown in FIG. 18b (m), a second photoresist pattern 672 is formed by a photolithography process to open a predetermined conductor formed on the plane B under the sacrificial substrate 650. Then, as shown in FIG. 18b (n) As shown, the second conductor 674 is formed on O: \ 89 \ 89662.DOC -52- 200419159 on the opening portion of the second photoresist pattern 672. Here, a conductive material such as nickel (Ni) or an alloy ( Ni_Co, Ni | C〇) to form the second conductor ⑺. Then, as shown in FIG. 18b ,, the upper plane of the second conductor 移除 is removed to flatten the upper plane. The planarization process here The method is the same as that disclosed in the first embodiment. After the planarization process is completed, a gold plating process is performed on the entire upper portion of the second conductor 674 to form a second gold plating layer 676. 9 However, it is used to form the second conductor 674 In the process of the ideal circuit process, only the second In the case where a conductor is formed in the opening of the resist pattern 672, the planarization process can be omitted. In addition, a method other than the electricity process such as physical vapor deposition (ρ, and chemical vapor deposition (CVD) is used to form a second conductor). In the case of 674, the previous process of forming the seed layer 662 can be omitted. Then, as shown in FIG. 18b (P), the second photoresist pattern 672 is removed by the wet engraving process. The second layer is also removed here The exposed part of the milk. In addition, the first photoresist pattern 664 protected by the second protective film 670 can be removed at the same time. Then, as shown in FIG. 18b (q), a third photoresist pattern 678 'is formed to turn on The second conductor 674 is intended to form a support assembly. • Next, as shown in FIG. 18c ', using the third photoresist pattern 678 as a mold, a bad oxide 680 is applied to the opening of the second conductor 674. Next, as shown in FIG. 18c (s), the plane above the epoxide 68 is flattened by a polishing process. Next, as shown in FIG. 18C, the second protective film 67 formed on the plane a above the sacrificial substrate 650 is removed. The first photoresist is then removed using a wet etching process
O:\89\89662.DOC -53- 200419159 水664,且一併移除種層660之外露部。 接著如圖18e(U)所示’利用微影製程形成第四光阻圖案 以開啟第一導體666中預定形成支樓組件處。而後利 用第四光阻圖案682施加環氧化物684於導體_之開啟部 上。接著利用研磨製程將環氧化物684之上平面平坦化。 接著如圖18c⑺所示,利用濕姓刻製程同時移除第三盘第 四光阻圖案678與682,且一併以使用職之濕姑刻製程移 除犧牲基板650之殘餘部分。 接著如圖18c(w)所示,在移除環氧化物658後,即完成本 發明之探針。 (具體貫施例2 - 9) 如圖19a(a)所示,將兩平面經均拋光之陶究板製備為犧牲 基板750。經過研磨製程或拋光製程後之犧牲基板75〇厚· 至5 0 0微米。 接著如圖19a⑻所*,利用切方製程於犧牲基板750之上 平面A上之預定部上形成兩渠溝752。 甚接著如圖19a(C)所示,於犧牲基板75〇之上平面a上形成 渠溝752處形成供銅電鍍結構形成電鐘製程用之第一種層 754 ’並形成渠溝’其中以鋼電鑛結構作為渠溝埋入材料。 此處之第一種層754係由鈦層與銅層構成。 接著如圖19a⑷所示,利用微影製程形成第—光阻圖案 756’^啟犧牲基板75()之上平^上預定形成渠溝752處。 接著如® 19a⑷所示,利用電鑛製程在為第—光阻圖案 756開啟之渠溝上形成作為渠溝埋入材料用之鍍鋼結構O: \ 89 \ 89662.DOC -53- 200419159 water 664, and the exposed part of the seed layer 660 is also removed. Next, as shown in FIG. 18e (U) ', a fourth photoresist pattern is formed by using a lithography process to open the first conductor 666 where a branch component is to be formed. Then, the fourth photoresist pattern 682 is used to apply an epoxide 684 on the opening of the conductor. Then, a planarization process is performed on the top surface of the epoxide 684 by a polishing process. Next, as shown in FIG. 18c (a), the fourth photoresist pattern 678 and 682 on the third disk are simultaneously removed by the wet last engraving process, and the remaining portion of the sacrificial substrate 650 is removed by the wet wet engraving process. Then, as shown in Fig. 18c (w), after the epoxide 658 is removed, the probe of the present invention is completed. (Specifically, Examples 2 to 9) As shown in FIG. 19a (a), a ceramic plate having both surfaces polished is prepared as a sacrificial substrate 750. The sacrificial substrate after the grinding process or the polishing process is 75 mm thick to 500 μm. Next, as shown in FIG. 19a, two trenches 752 are formed on a predetermined portion on the plane A above the sacrificial substrate 750 by a tangent process. Then, as shown in FIG. 19a (C), a trench 752 is formed on the plane a above the sacrificial substrate 750 to form a first layer 754 'for the copper plating structure to form a clock process and a trench is formed. Steel ore structure is used as trench and buried material. The first layer 754 here is composed of a titanium layer and a copper layer. Next, as shown in FIG. 19a, a photoresist pattern 756 'is used to form a first photoresist pattern 756' on the sacrificial substrate 75 () to form trenches 752 at a predetermined level. Then, as shown in ® 19a ,, a galvanized structure is formed on the trench opened for the first photoresist pattern 756 as a trench buried material by the electric mining process.
O:\89\89662.DOC -54- 200419159 758 〇 接著如圖19a(f)所示,移除第一光阻圖案756以及自犧牲 基板750向上突出之部分鍍銅結構758,藉以將犧牲基板75〇 之上平面Α平坦化。施行平坦化製程直到犧牲基板75〇之上 平面A表面與鍍銅結構758相互毗鄰為止。 接著如圖19a(g)所示,於犧牲基板75〇之上平面a上形成 供導體形成電鍍製程用之第二種層76〇。此處之第二種層 760係由厚500埃之鈦層及厚5,〇〇〇埃之銅層構成。銅層實質 上係充作後續電鍍製程中電鍍之種層用,鈦層則係用以提 升犧牲基板750與銅層間之黏著性。 接著如圖19b(h)所示,利用微影製程形成第二光阻圖案 762,以開啟犧牲基板75〇上預定形成導體處。 接著如圖19b⑴所示,在利用第二光阻圖案762開啟處上 形成第一導體764。在此係以電解質電鍍法沉積傳導材料如 鎳(Ni)或鎳合金(Ni-Co、Ni_w_c〇)而形成第一導體7料。 接著如圖19b⑴所示,藉由移除第一導體764之上平面之 不均勻處而將其上平面平坦化。此處之平坦化製程與第一 具體實施例所揭方法相同。 但在用以形成第一導體764之理想電鍍製程之進程中,僅 於第二光阻圖案762之開啟部内形成導體之情況下,平坦化 製程即可略之。 此外,在利用除電鑛製程外之方法如物理汽相沉積 與化學汽相沉積(CVD)形成第一導體764之情況下,先前形 成第二種層760之製程即可略之。O: \ 89 \ 89662.DOC -54- 200419159 758 〇 Next, as shown in FIG. 19a (f), the first photoresist pattern 756 and a portion of the copper-plated structure 758 protruding upward from the sacrificial substrate 750 are removed, so that the sacrificial substrate is removed. The plane A above 75 ° is flattened. The planarization process is performed until the surface A of the plane A and the copper-plated structure 758 above the sacrificial substrate 75 are adjacent to each other. Next, as shown in Fig. 19a (g), a second layer 76o for forming a conductor is formed on the plane a above the sacrificial substrate 75o. The second layer 760 here is composed of a titanium layer with a thickness of 500 angstroms and a copper layer with a thickness of 5,000 angstroms. The copper layer is essentially used as a seed layer for electroplating in the subsequent electroplating process, and the titanium layer is used to improve the adhesion between the sacrificial substrate 750 and the copper layer. Next, as shown in FIG. 19b (h), a second photoresist pattern 762 is formed by a lithography process to open a predetermined conductor formed on the sacrificial substrate 75o. Next, as shown in FIG. 19b (a), a first conductor 764 is formed on the place where the second photoresist pattern 762 is turned on. Here, a first conductive material is formed by depositing a conductive material such as nickel (Ni) or a nickel alloy (Ni-Co, Ni_w_co) by an electrolytic plating method. Next, as shown in FIG. 19b (a), the upper plane of the first conductor 764 is flattened by removing unevenness in the plane above the first conductor 764. The planarization process here is the same as the method disclosed in the first embodiment. However, in the course of an ideal plating process for forming the first conductor 764, the planarization process may be omitted only in the case where a conductor is formed in the opening portion of the second photoresist pattern 762. In addition, in the case where the first conductor 764 is formed by using a method other than a power ore process such as physical vapor deposition and chemical vapor deposition (CVD), the previous process of forming the second layer 760 may be omitted.
O:\89\89662.DOC -55- 200419159 接著如圖19b(k)所示,於第一導體764之整個上部上施行 鑛金製程,藉以形成第一鍍金層766。 接著如圖19b(l)所示’在犧牲基板750之上平面a上形成用 以保護第一導體764之保護膜768,並形成第一鍍金層766, 在前述製程完成前即已完成在犧牲基板75〇之上平面a上 之製程。 現將描述在犧牲基板750之下平面b上之製程。 首先如圖19b(m)所示,以研磨製程研模犧牲基板75〇到直 得以路出犧牲基板750之下平面B與鑛銅結構758之下平面 之程度。 接著如圖19b(n)所示,於犧牲基板75〇之整個下平面上形 成供導體形成電鍍製程用之第三種層77〇。此處之第三種層 770係由厚500埃之鈦層及厚5,〇〇〇埃之銅層構成。銅層實質 上係充作後續電鍍製程中電鍍之種層用,鈦層則係用以改 善犧牲基板750與銅層間之黏著性。接著利用微影製程形成 第三光阻圖案772,以開啟犧牲基板75〇之上平面上預定形 成導體處。 接著如圖19c(o)所不,於利用第三光阻圖案772開啟處上 形成第二導體774。在此係以電解質電鐘法沉積傳導材料如 鎳(Ni)或錄合金(Ni_c。、Ni_w_c。)而形成第三導體π。 接著如圖BWp)所示,藉由移除第三導體774之上平面之 不均勻處,將其上平面平坦化。此處之平坦化製程與第一 具體實施例中所揭方法相同。在完成平坦化製程後,於第 二導體774之整個上部上施行鍍金製程,藉以形成第二鍍金O: \ 89 \ 89662.DOC -55- 200419159 Then, as shown in FIG. 19b (k), a gold-mine process is performed on the entire upper portion of the first conductor 764 to form a first gold plating layer 766. Next, as shown in FIG. 19b (l), a protective film 768 for protecting the first conductor 764 is formed on the plane a above the sacrificial substrate 750, and a first gold-plated layer 766 is formed. Process on the plane a above the substrate 75. The process on the plane b below the sacrificial substrate 750 will now be described. First, as shown in FIG. 19b (m), the sacrificial substrate 75 is mold-molded in a grinding process until the plane B below the sacrificial substrate 750 and the plane below the mineral copper structure 758 are exited. Next, as shown in Fig. 19b (n), a third layer 770 for forming a conductor for electroplating is formed on the entire lower plane of the sacrificial substrate 75o. The third layer 770 here is composed of a titanium layer with a thickness of 500 angstroms and a copper layer with a thickness of 5,000 angstroms. The copper layer is essentially used as a seed layer for electroplating in the subsequent plating process, and the titanium layer is used to improve the adhesion between the sacrificial substrate 750 and the copper layer. Then, a third photoresist pattern 772 is formed by a lithography process to open a predetermined conductor formed on the plane above the sacrificial substrate 75 °. Next, as shown in FIG. 19c (o), a second conductor 774 is formed on the place where the third photoresist pattern 772 is opened. Here, a conductive material such as nickel (Ni) or an alloy (Ni_c., Ni_w_c.) Is deposited by an electrolytic clock method to form a third conductor π. Then as shown in Figure BWp), the upper plane of the third conductor 774 is flattened by removing the unevenness of the plane above the third conductor 774. The planarization process here is the same as the method disclosed in the first embodiment. After the planarization process is completed, a gold plating process is performed on the entire upper portion of the second conductor 774 to form a second gold plating process.
O:\89\89662.DOC -56- 200419159 層 776 〇 於 製 但在用以形成第三導體774之理想電鑛製程之進程中,僅 第三光阻圖案772之開啟部内形成導體之情況下,平μ 程即可略之。 此外,在利用除電鍍製程外之方法如物理汽相沉積 與化學汽相沉積(CVD)形成第三導體774之情況下,先前形 成第三種層770之製程即可略之。 、,接著如圖19c⑷所示’利用濕飯刻製程移除保護臈768, 亚同時移除第二與第三光阻圖案762與772。此處,也會移 除第二種層760及第三種層77〇。 曰 接著如圖19d(r)所示,利用微影製程形成第四與第五光阻 圖案778與780,以開啟第一與第二導體764與π#中預定形 成支樓組件處。 接著如圖19d(s)所示,於利用第四光阻圖案778開啟之部 分第一導體774上施加熱塑性環氧化物。 接著如圖19d(t)所示,利用研磨製程將環氧化物782之上 平面平坦化。 接著如圖19d(u)所示,利用相同製程於犧牲基板75〇之上 平面上形成環氧化物層784。接著如圖19d(v)所示,利用研 磨製程將環氧化物784之上平面平坦化。 接著如圖19d(w)所示,利用濕蝕刻製程同時將殘留在犧 牲基板750之上下平面上之第四與第五光阻圖案778與78〇 移除。 最終藉由施加外力於殘餘犧牲基板750上而移除犧牲基 O:\89\89662.DOC -57- 200419159 板750,並且藉由選擇性姓刻製程來移除渠溝埋入材料 75 8,藉以完成本發明之探針。 換言之’圖20闡釋依圖17、邮以所示方法製造之探針 結構。 圖20係闡釋藉由使用根據本發明實施例製造之犧性基板 所形成之探針的剖視圖。 如圖20所示,介電質38〇位於探針之中 3似分別以敎間隔位於介電f政上下平面上。此夕^ 支撐組件384a與384b分別附接於介電質38〇之上下平面上 導體382a與382b所在處。此外,由導電率較導體382&與3咖 之材料構成之薄層386a與386b分別位於導體382a與382]3之 外平面上。 供形成介電質用之渠溝係於犧牲基板之預定部上形成, 2著將介電質材料嵌入渠溝中,藉以形成介電質38〇。介電 貝材料為陶瓷較佳。介電質兩端之剖面可具步階差外型或 傾斜外型。利用微影製程於介電質380之兩平面上形成第一 保護膜,並接著於利用第一保護膜開啟之區域上沉積傳導 材料而形成導體382&與3821)。此外,利用微影製程於犧牲 基板之兩平面上形成導體382a與382b處形成第二保護膜, 亚接著將支撐材料嵌入利用第二保護膜開啟之區域中,藉 以形成支撐組件384a與3 84b。 此外’依具體實施例2_6製造之使用單一犧牲基板之探針 、、心構與圖25相同。因此,探針結構之細部描述略之。 圖21 a係闡釋本發明中使用之陶瓷板之透視圖與剖面O: \ 89 \ 89662.DOC -56- 200419159 Layer 776 〇 In the process of forming an ideal electric mine process for forming the third conductor 774, only the case where a conductor is formed in the opening of the third photoresist pattern 772 , Can be omitted for level μ. In addition, in the case where the third conductor 774 is formed by a method other than the electroplating process such as physical vapor deposition and chemical vapor deposition (CVD), the previous process of forming the third layer 770 may be omitted. Then, as shown in FIG. 19c (a), the protection pad 768 is removed by a wet rice engraving process, and the second and third photoresist patterns 762 and 772 are removed at the same time. Here, the second layer 760 and the third layer 770 are also removed. Next, as shown in FIG. 19d (r), fourth and fifth photoresist patterns 778 and 780 are formed by a lithography process to turn on the first and second conductors 764 and π # to form the branch component. Next, as shown in FIG. 19d (s), a thermoplastic epoxide is applied to a portion of the first conductor 774 that is turned on by the fourth photoresist pattern 778. Next, as shown in FIG. 19d (t), a plane above the epoxide 782 is planarized by a polishing process. Next, as shown in FIG. 19d (u), an epoxide layer 784 is formed on the plane above the sacrificial substrate 75 by the same process. Next, as shown in FIG. 19d (v), a plane above the epoxide 784 is planarized by a grinding process. Next, as shown in FIG. 19d (w), the fourth and fifth photoresist patterns 778 and 78o remaining on the upper and lower planes of the sacrificial substrate 750 are simultaneously removed by a wet etching process. Finally, the sacrificial substrate O: \ 89 \ 89662.DOC -57- 200419159 plate 750 is removed by applying an external force on the residual sacrificial substrate 750, and the trench buried material 75 8 is removed by a selective surname process. This completes the probe of the present invention. In other words, 'FIG. 20 illustrates the structure of a probe manufactured by the method shown in FIG. FIG. 20 is a cross-sectional view illustrating a probe formed by using a sacrificial substrate manufactured according to an embodiment of the present invention. As shown in FIG. 20, the dielectric 38 is located in the probe 3, and it seems to be located on the upper and lower planes of the dielectric f at intervals of 敎. At this time, the supporting components 384a and 384b are respectively attached to the conductors 382a and 382b on the upper and lower planes of the dielectric 38. In addition, the thin layers 386a and 386b made of a material having higher conductivity than the conductors 382 & and 3c are located on the outer planes of the conductors 382a and 382] 3, respectively. The trench for forming the dielectric is formed on a predetermined portion of the sacrificial substrate, and the dielectric material is embedded in the trench to form the dielectric 38. The dielectric shell material is preferably ceramic. The profile at both ends of the dielectric can have a stepped profile or an inclined profile. A lithography process is used to form a first protective film on both planes of the dielectric 380, and then a conductive material is deposited on the area opened by the first protective film to form the conductors 382 & and 3821). In addition, a lithography process is used to form the second protective film on the conductors 382a and 382b on the two planes of the sacrificial substrate. Subsequently, the support material is embedded in the area opened by the second protective film to form support components 384a and 384b. In addition, the probe using the single sacrificial substrate manufactured in accordance with the specific embodiment 2-6, and the heart structure are the same as those shown in FIG. Therefore, the detailed description of the probe structure is omitted. Figure 21a is a perspective view and a cross-section illustrating a ceramic plate used in the present invention
O:\89\89662.DOC -58- 200419159 圖,其中剖面係平行四邊形;圖21b係闡釋本發明中使用之 陶瓷板之透視圖與剖面圖。這些外型適用於依本發明之所 有具體貫施例。 (探針組之第一具體實施例) 圖22a係闡釋具有依本發明之用以測試平面板顯示器之 板針之第一探針組之透視圖;圖22b係其剖面圖。此處將不 費述前述探針片之特殊架構及其製造方法。 苓閱圖22a與22b,在依本發明之第依具體實施例之探針 組中,其中有複數個單元結構附接與固定於一可透光模9〇ι 上之探針,係固定於探針區塊9〇4之下部上。在此,各單元 結構均包括具檢測尖端902與連結尖端(未圖示)之光束構件 900 〇 利用雙面膠帶或黏著劑使探針與探針區塊9〇4相互附接 並固定。捸針區塊9〇4係由可透光材料如丙烯酸製成,以確 保其透光性。 此外,第一介面板908位於探針區塊904上方,相互間並 為I田閂904之嚙合而固定。第二介面板91〇與探針固持器Μ] 依序位於第一介面板9〇8上方,且相互間為錨閂914之嚙合 而固定。 此外,第一與第二介面板908與91〇為固定栓9〇7嚙合在一 起,以進一步增加其間之嚙合力。第二介面板910與探針固 持為912間亦為固定栓911所响合,俾進一步增加其間之嗜 合力。 位於探針片之光束構件900之一末端部處之連結尖端(未O: \ 89 \ 89662.DOC -58- 200419159, wherein the cross section is a parallelogram; Fig. 21b illustrates a perspective view and a cross-sectional view of a ceramic plate used in the present invention. These shapes are suitable for all specific embodiments according to the invention. (First specific embodiment of the probe set) Fig. 22a is a perspective view illustrating a first probe set having a pin for testing a flat panel display according to the present invention; and Fig. 22b is a sectional view thereof. The special structure of the aforementioned probe sheet and its manufacturing method will not be described here. See Figure 22a and 22b. In the probe set according to the first embodiment of the present invention, a plurality of unit structures are attached and fixed to a light-transmitting mold 90m, which are fixed to The lower part of the probe block 904. Here, each unit structure includes a beam member 900 having a detection tip 902 and a connection tip (not shown). The probe and the probe block 904 are attached and fixed to each other with a double-sided tape or an adhesive. The needle block 904 is made of a light-transmissive material such as acrylic to ensure its light-transmittance. In addition, the first interface panel 908 is located above the probe block 904 and is fixed to each other and for the engagement of the latch 904. The second interface panel 910 and the probe holder M] are sequentially located above the first interface panel 908, and are fixed to each other by the engagement of the anchor 914. In addition, the first and second interface panels 908 and 91 are engaged with the fixing bolt 907 to further increase the engaging force therebetween. The second interface panel 910 and the probe are held by 912 and are also resonated by the fixing bolt 911, which further increases the affinity between them. A connecting tip (not shown) at one end of the beam member 900 of the probe sheet
O:\89\89662.DOC -59- 200419159 圖示)經導引膜930連結至位於捲帶式封裝(TCp)932上之圖 更特別言之,該結構係藉由配置探針(形成連結尖端處) 於第一介面板980之下部上,並接著藉由固定組件922與錨 閃924喷合採針與第一介面板而構成。 更特別§之,將由絕緣陶瓷材料構成之上封閉黏著組件 926及下封閉黏著組件928分別插入探針與第一介面板8 間及TCP 932與固定組件922間。此外,探針之連結尖端9〇2b 與TCP 932經由上下封閉黏著組件926與928間之導引膜93() 相互連結。 此外,壓縮錨閂929進一步位於固定組件922之下部,使 得探針之連結尖端9〇2b與TCP 932得以在錨閂929之轉動壓 、、、佰下’經由導引膜932而更強烈連結在一起。 再者,以錨閂920將探針固持器912與操縱器916嚙合在一 起。在測試製程期間,可以物理力卩將連結至操縱器9丨6之 探針固持器912上下移動。 更特別言之,探針固持器912之一側與操縱器916之一側 為導引軌918嚙合在一起,使得第一介面板9〇8、連結至探 針固持裔912之第二介面板91〇,以及探針區塊9〇4得以於測 忒衣私期間,為上下物理力F上下移動。 斗寸別5之’具預定彈力之彈簧92丨位於連結探針固持器 912與操縱器916之固定組件92〇周圍,使得在測試製程期 間為上下物理力F上下移動之第一介面板9〇8、連結至探 針固持裔912之第二介面板91〇以及探針區塊9〇4得以藉由O: \ 89 \ 89662.DOC -59- 200419159 (pictured) is connected to the tape-and-reel package (TCp) 932 via the guide film 930. More specifically, the structure is formed by the configuration of a probe (connection At the tip) on the lower part of the first interface panel 980, and then is formed by the fixing assembly 922 and the anchor flash 924 spraying the needle and the first interface panel. More specifically, the upper closed adhesive component 926 and the lower closed adhesive component 928 made of an insulating ceramic material are inserted between the probe and the first interface panel 8 and between the TCP 932 and the fixed component 922, respectively. In addition, the connection tip 902b of the probe and the TCP 932 are connected to each other via a guide film 93 () between the upper and lower closed adhesive components 926 and 928. In addition, the compression anchor 929 is further located below the fixed component 922, so that the connection tip 902b of the probe and the TCP 932 can be strongly connected to each other through the guide film 932 during the rotation of the anchor 929. together. Further, the probe holder 912 and the manipulator 916 are engaged with each other by the anchor 920. During the test process, the probe holder 912 connected to the manipulators 9 and 6 can be moved up and down by physical force. More specifically, one side of the probe holder 912 and one side of the manipulator 916 mesh with the guide rail 918 so that the first interface panel 908 and the second interface panel connected to the probe holder 912 are engaged. 91 °, and the probe block 904 was able to move up and down for the up and down physical force F during the measurement of private clothing. The spring 92 with a predetermined elasticity of the bucket inch 5 is located around the fixed component 92o that connects the probe holder 912 and the manipulator 916, so that the first interface panel 9 that moves up and down during the test process is the physical force F. 8. The second interface panel 91 and the probe block 904 connected to the probe holder 912 can be obtained by
O:\89\89662.DOC -60- 200419159 彈簧921之彈力恢復至其初始位置。 在另一具體實施例中,如圖23所示,前述位於第一解面 板908之下部上之固定組件可略之。此外,不具連結尖端與 TCP 932之探針光束構件位於非等向性傳導膜(acF)935 上’並利用壓縮製程與加熱製程相互連結。 因此,將以一系列製造平面板顯示器之製程獲得之平面 板顯不裔固接於一探測儀器上,並藉由移動裝置之移動探 針區塊904以及預定物理力之施加於平面板顯示器之電極 塾上。於平面板顯示器上施行電氣測試製程。 此日守’位於探針區塊904下部之檢測尖端9〇2與平面板顯 不器之電極墊接觸。輸入至探測儀器之電氣信號即經由τ c p 932、探針光束構件與檢測尖端9〇2施加於平面板顯示器之 電極墊。 G朱針組之第二具體實施例) 圖24a係闡釋具有依本發明之用以測試平面板顯示器之 振針之第二探針組之透視圖;圖24b係其剖面圖。將不贅述 4述探針架構及其製造方法。 茶閱圖24a與24b,在依本發明之第二具體實施例之第二 ^針組中,以由金屬如不鏽鋼製成之高彈性金屬板936取代 =第一探針組中位於第一介面板9〇8下部處之可透光材料 製探針區塊。金屬板936經錨閂9〇3固定於第一介面板9〇8之 下部處,並以黏著劑經由高彈性橡膠938固定探針於金屬板 936下部。 藉由施加預定物理力F於平面板顯示器之電極墊上而施O: \ 89 \ 89662.DOC -60- 200419159 The spring force of the spring 921 returns to its initial position. In another specific embodiment, as shown in FIG. 23, the aforementioned fixing components on the lower portion of the first solution panel 908 can be omitted. In addition, the probe beam member without the connection tip and TCP 932 is located on the anisotropic conductive film (acF) 935 'and is connected to each other by a compression process and a heating process. Therefore, the flat panel display obtained through a series of processes for manufacturing the flat panel display is fixed to a detection instrument, and the mobile probe block 904 and a predetermined physical force are applied to the flat panel display. Electrode 塾. Perform an electrical test process on a flat panel display. The detection tip 902 located at the bottom of the probe block 904 is in contact with the electrode pad of the flat panel display. The electrical signal input to the detection instrument is applied to the electrode pad of the flat panel display via τ c p 932, the probe beam member and the detection tip 902. G Zhu Needle Group Second Specific Embodiment) Fig. 24a is a perspective view illustrating a second probe set having a vibrating needle for testing a flat panel display according to the present invention; and Fig. 24b is a sectional view thereof. The details of the probe architecture and its manufacturing method will not be repeated. See Figures 24a and 24b. In the second pin set according to the second embodiment of the present invention, a high elastic metal plate 936 made of metal such as stainless steel is used to replace = the first probe set is located at the first A light-transmissive probe block at the lower part of the panel 908. The metal plate 936 is fixed to the lower portion of the first interface plate 908 through the anchor 903, and the probe is fixed to the lower portion of the metal plate 936 with an adhesive through a highly elastic rubber 938. By applying a predetermined physical force F to the electrode pad of the flat panel display
O:\89\89662.DOC -61 - 200419159 行電氣測試製程時,“第二探針組中具有位於第-介面 板908下部處之彈性金屬板936與橡膠938,故可增加彈性。 (探針組之第三體實施例) 圖25係闡釋具有依本發明之探針之探針組之透視圖;圖 26則係其剖面圖。 參閱圖25舆26,在依本發明之第三具體實施例之探針組 :’多㈣針係在-堆疊結構中。如上述,多層探針包括 乂曰隹且但不相互重璺之上探針之導體與下探針之導 體950。上探針之各導體96〇之一末端部較各導體更為向 卜大出且上下導體之外露部等長,俾具相同電氣與物理 性質及傳導性。 利用附接-固定工具如錨閂將堆疊結構中之探針相互固 定於探針區塊955之傾斜平面上。探針區塊955可由可透光 材料如丙烯酸製成,以確保其透光性。 此外,第一介面板965位於探針區塊955上方。探針固持 态970位於第一介面板965上方,且為錨閂967之嚙合固定在 一起。 第一介面板965與探針固持器970為固定栓967所嚙合,以 進一步增加其間的嚙合力。 此外’第二介面板975亦藉由固定栓967之嚙合而固定於 第一介面板965之下平面上之探針區塊955背側。TCP 972 附接並固定於第二介面板975之下平面上。 就附接並固定於探針區塊955之傾斜平面上之TCP 972與 多層探針之導體950與960之連結而言,多層探針之各導體 O:\89\89662.DOC -62- 200419159 950與960之一端在一在導引膜974上形成之孔(未標示代號) 之導引下,連結至位於TCP 972上之對應圖案。 此外,以錨閂982將探針固持器970與操縱器980嚙合在一 起。在測試製程期間,可以上下物理力F將連結至操縱器980 之探針固持器970上下移動。 更特別言之,探針固持器970之一側與操縱器980之一側 為導引執984嚙合在一起,使得連結至探針固持器970之第 一介面板965及探針區塊955得以於測試製程期間,為上下 物理力F上下移動。 特別言之,具預定彈力之彈簧986位於連結探針固持器 970與操縱器980之固定組件982周圍,使得在測試製程期 間,為上下物理力F上下移動之連結至探針固持器970之第 一介面板965及探針區塊955得以藉由彈簧986之彈力恢復 至其初始位置。 因此,將以一系列製造平面板顯示器之製程獲得之平面 板顯示器固接於一探測儀器上,並藉由移動裝置之移動探 針區塊955以及預定物理力之施加於平面板顯示器之電極 墊上。於平面板顯示器上施行電氣測試製程。 此時,位於探針區塊955下部之多層探針之針部950與960 與平面板顯示器之電極墊接觸。輸入至探測儀器之電氣信 號即經由TCP 972、探針光束構件與探針之針部950及960 施加於平面板顯示器之電極塾。 工業應用性 依本發明,易於利用切方鋸齒製程以及附接針狀導體之 O:\89\89662.DOC -63- 200419159 製程,在由硬質材料構成 叉嫁板上製造探針, 於得以縮減製造探針之製裎日士 Η 故饭點在 L L 衣私知間,並因而增加生產率。 此外,依本發明,可去& 〆 、,除以%氧化物黏著複數個導體之 Λ T ^ ^ a °〇避免在先前技藝中因熱膨脹係 數及人工刼作至異造成之探 精確度對齊探針之優點。 ^故其具有可以較高 ,依本發明可採用單一 ’並可因製程之減少與 在於可降低探針生產價 此外,與先前技藝中之製程不同 犧牲基板’減少差異極大之製程數 精確度之改善而提昇良率,故優點 袼,並可改善製程良率與生產率。 雖已詳述本發明及其優點 施例及隨附圖式為限,熟悉 申請專利範圍所界定之本發 改變、取代及替換。 ,應知本發明不以前述具體實 此技藝者應知在不悖離隨附之 明之精神與範疇下,可作各種 【圖式簡單說明】 自下列較佳具體實施例之描述暨隨附圖式,將可瞭解本 發明之上述及其他目的、優點與特徵,其中·· …圖u係闡釋依本發明—具體實施例之用以測試平面板顯 示器之探針及其製造方法之透視圖;圖lb#wia之縱向剖 面圖;圖lc係圖^之橫向剖面圖; 圖2a與2b係闡釋依圖^至卜製造之用以測試平面板顯示 為之板針之另一具體實施例之製程之透視圖;圖孔係圖h 之縱向剖面圖;圖2C係圖2a之橫向剖面圖; 圖3a至3e係闡釋依圖2a至2c製造之用以測試平面板顯示O: \ 89 \ 89662.DOC -61-200419159 During the electrical test process, "the second probe set has an elastic metal plate 936 and a rubber 938 located at the lower portion of the first interface plate 908, so the elasticity can be increased. Third Embodiment of Needle Set) FIG. 25 is a perspective view illustrating a probe set having a probe according to the present invention; FIG. 26 is a sectional view thereof. Referring to FIG. The probe set of the embodiment: 'multiple pins are in a stacked structure. As mentioned above, the multilayer probe includes the conductor of the upper probe and the conductor 950 of the lower probe, but does not overlap each other. One of the ends of each of the conductors of the needle 96 is larger than each conductor, and the exposed portions of the upper and lower conductors are equal in length and have the same electrical and physical properties and conductivity. The attachment-fixation tools such as anchors are used to stack The probes in the structure are fixed to the inclined plane of the probe block 955. The probe block 955 can be made of a light-transmissive material such as acrylic to ensure its light-transmittance. In addition, the first interface panel 965 is located on the probe. Above block 955. The probe holding state 970 is located above the first interface panel 965 and is an anchor 9 The engagement of 67 is fixed together. The first interface panel 965 and the probe holder 970 are engaged by the fixing bolt 967 to further increase the engagement force therebetween. In addition, the 'second interface panel 975 is also fixed by the engagement of the fixing bolt 967 On the back of the probe block 955 on the plane below the first interface panel 965. TCP 972 is attached and fixed on the plane below the second interface panel 975. It is attached and fixed on the inclined plane of the probe block 955 As for the connection between the TCP 972 and the conductors 950 and 960 of the multilayer probe, each conductor of the multilayer probe O: \ 89 \ 89662.DOC -62- 200419159 One of 950 and 960 is formed on the guide film 974 Under the guidance of the hole (not marked with the code), it is connected to the corresponding pattern on TCP 972. In addition, the probe holder 970 and the manipulator 980 are engaged with each other by the anchor 982. During the test process, the physics can be up and down The force F moves the probe holder 970 connected to the manipulator 980 up and down. More specifically, one side of the probe holder 970 and one side of the manipulator 980 are engaged with each other as a guide 984, so that the connection to the probe First interface panel 965 and probe block 955 of the needle holder 970 During the test process, the upper and lower physical forces F move up and down. In particular, a spring 986 with a predetermined elasticity is located around the fixed component 982 that connects the probe holder 970 and the manipulator 980, so that during the test process, the upper and lower physical forces F The first interface panel 965 and the probe block 955 connected to the probe holder 970 up and down by the force F can be restored to their initial positions by the spring force of the spring 986. Therefore, it will be obtained by a series of processes for manufacturing a flat panel display. The flat panel display is fixed on a detection instrument, and is applied to the electrode pad of the flat panel display by a moving probe block 955 of a mobile device and a predetermined physical force. Perform an electrical test process on a flat panel display. At this time, the needle portions 950 and 960 of the multilayer probe located under the probe block 955 are in contact with the electrode pads of the flat panel display. The electrical signal input to the detection instrument is applied to the electrode 塾 of the flat panel display via TCP 972, the probe beam member and the needle portions 950 and 960 of the probe. Industrial Applicability According to the present invention, it is easy to use the tangent sawtooth process and the O: \ 89 \ 89662.DOC -63- 200419159 process for attaching needle conductors to manufacture probes on a cross-linked board made of hard material, which can be reduced. The system for making probes is made in Japan, so meals are served in LL clothing, and thus productivity is increased. In addition, according to the present invention, it is possible to divide & 〆, and divide by Λ T ^ ^ a ° of a number of oxides to adhere to a plurality of conductors to avoid the alignment of the probe accuracy caused by the thermal expansion coefficient and manual operation in the prior art Advantages of the probe. ^ Therefore, it can be high, according to the present invention, a single 'can be used and can reduce the production cost of the probe due to the reduction of the manufacturing process and in addition, can sacrifice the substrate different from the process in the prior art' to reduce the difference in manufacturing process accuracy. The improvement improves the yield, so the advantages are not good, and the process yield and productivity can be improved. Although the present invention and its advantages are limited to the detailed embodiments and accompanying drawings, the present invention is familiar with the changes, substitutions and replacements defined by the scope of patent application. It should be understood that the present invention is not embodied in the foregoing. Those skilled in the art should know that without departing from the spirit and scope of the attached invention, various illustrations can be made. [Simple illustration of the drawings] From the description of the following preferred embodiments and accompanying drawings The above-mentioned and other objects, advantages and features of the present invention will be understood, in which ... FIG. U is a perspective view illustrating a probe for testing a flat panel display and a manufacturing method thereof according to the present invention-specific embodiment; Fig. Lb # wia is a longitudinal sectional view; Fig. Lc is a transverse sectional view of Fig. ^; Figs. 2a and 2b illustrate the manufacturing process of another specific embodiment of the test pin shown in Figs. A perspective view; a picture hole is a longitudinal cross-sectional view of FIG. H; FIG. 2C is a transverse cross-sectional view of FIG. 2a; and FIGS. 3a to 3e illustrate a flat panel display manufactured according to FIGS. 2a to 2c for testing.
O:\89\89662.DOC -64- 200419159 裔之探針之另一具體實施例之製程之透視圖; 圖^與仙係闡釋依本發明之MEMS製程製造之用以測試 平面板顯示器之雙層探針之透視圖; 圖5a係闡釋依本發明之MEMS製程製造之用以測試平面 板顯不器之單層探針之透視圖;圖5b係圖兄之縱向剖面圖; 圖6a至6p係闡釋依另一具體實施例製造用以測試平面板 顯示器之探針之方法之剖面圖; 圖7a至7ι係闡釋依另一具體實施例製造用以測試平面板 顯示器之探針之方法之剖面圖; 圖8a至8t係闡釋依另一具體實施例製造用以測試平面板 顯示器之探針之方法之剖面圖; 圖9係闡釋依另一具體實施例製造用以測試平面板顯示 态之探針之方法之透視圖;O: \ 89 \ 89662.DOC -64- 200419159 perspective view of the manufacturing process of another specific embodiment of the probe; Figure ^ and the legend illustrate the dual test of the flat panel display manufactured according to the MEMS process of the present invention Perspective view of a single-layer probe; Figure 5a is a perspective view illustrating a single-layer probe for testing a flat panel display manufactured according to the MEMS process of the present invention; Figure 5b is a longitudinal sectional view of a figure; Figures 6a to 6p A cross-sectional view illustrating a method of manufacturing a probe for testing a flat panel display according to another embodiment; FIGS. 7a to 7i are cross-sectional views illustrating a method of manufacturing a probe for testing a flat panel display according to another specific embodiment; 8a to 8t are cross-sectional views illustrating a method of manufacturing a probe for testing a flat panel display according to another embodiment; FIG. 9 is a view illustrating a probe for testing a display state of a flat panel according to another embodiment Perspective view of the needle method;
1 〇b係其剖面圖;1 〇b is a sectional view;
之探針之透視圖;Perspective view of the probe;
板顯示器之探針之方法之各製 具體實施例製造用以測試平面 製程之剖面圖;Sections of the method for the probe of the panel display
0:\89\89662.D〇C -65- 200419159 囷16係依圖15a至15e所示方法製造之探針之透視圖; 圖17a至17c係闡釋依另一具體實施例製造用以測試平面 板顯示器之探針之方法之各製程之剖面圖; 圖18a至18c係闡釋依另一具體實施例製造用以測試平面 板顯示器之探針之方法之各製程之剖面圖; 圖19a至19d係闡釋依另一具體實施例製造用以測試平面 板顯示器之探針之方法之各製程之剖面圖; 圖20係依圖1以至17(1所示方法製造之探針之透視圖; 圖21a係闡釋本發明中使用之陶瓷板之透視圖與剖面 圖’其中剖面係平行四邊形;圖21b係闡釋本發明中使用之 陶瓷板之透視圖與剖面圖,其中剖面係步階形; 圖22福闡釋具有依本發明之用以測試平面板顯示器之 探針之第一探針組之透視圖;圖22b係其剖面圖; 圖23係闡釋圖22與24中所示捲帶式封裝(Tcp)與單元導 體組件間之連結圖; 圖24a係闡釋具有依本發明之用以測試平面板顯示器之 探針之第二探針組之透視圖;圖2仆係其剖面圖,· 圖25係闡釋具有依本發明之探針之探針組之透視圖,·及 圖26係闡釋具有依本發明之探針之探針組之剖面圖。 【圖式代表符號說明】 類板狀介電質 線 導體 10,80 11 2〇a ’ 20b,50,284,286,302,312,360a 360b,372a,372b,412a,412b,950,9600: \ 89 \ 89662.D〇C -65- 200419159 囷 16 is a perspective view of a probe manufactured according to the method shown in Figs. 15a to 15e; Figs. 17a to 17c illustrate another embodiment for testing a flat surface. Cross-sectional views of the various processes of the method of the probe of the panel display; FIGS. 18a to 18c are cross-sectional views of the processes of the method of manufacturing the probe for testing the flat-panel display according to another embodiment; FIGS. 19a to 19d are A cross-sectional view illustrating each process of a method for manufacturing a probe for testing a flat panel display according to another embodiment; FIG. 20 is a perspective view of a probe manufactured according to the method shown in FIGS. 1 to 17 (1); Explanation of perspective and cross-sectional views of a ceramic plate used in the present invention, where the cross-section is a parallelogram; FIG. 21b is a perspective and cross-sectional view of a ceramic plate used in the present invention, where the cross-section is a step shape; FIG. 22 illustrates A perspective view of a first probe set having a probe for testing a flat panel display according to the present invention; FIG. 22b is a cross-sectional view thereof; FIG. 23 is a diagram illustrating a tape and reel package (Tcp) shown in FIGS. 22 and 24 and Connection diagram between unit conductor components; Figure 24a is A perspective view of a second probe set having a probe for testing a flat panel display according to the present invention is shown; FIG. 2 is a cross-sectional view thereof, and FIG. 25 is a view illustrating a probe set having a probe according to the present invention. A perspective view, and FIG. 26 are cross-sectional views illustrating a probe set having a probe according to the present invention. [Description of Representative Symbols of the Drawings] Similar Plate-shaped Dielectric Wire Conductors 10, 80 11 2aa 20b, 50 , 284, 286, 302, 312, 360a 360b, 372a, 372b, 412a, 412b, 950, 960
O:\89\89662.DOC -66 - 200419159 30a,30b,282,364,376a,376b 40 40a , 40b 60 70 90 , 100 , 218 , 308 , 318 9卜10卜110 93 , 103 , 112 95 , 105 , 114 97a,97b,107a,144,467,551,655, 752 98 108 , 118 109,304,314,370a,370b,420,428, 462,470,484,554,580,658,684, 782 , 784 116a,256a,256b,334a,416 120,200,250,330,400,450,550, 650 , 750 122 , 202 , 261 124,204,262 126 , 206 , 260 , 336 , 408a , 408b 128,,208,252 129,210,254,332,402a,402b,454, 支撐組件 傳導材料 薄傳導材料 類板狀支撐組件 鍍金層 支撐板 第一突出區 中央槽 第二突出區 渠溝 下導體 上導體 環氧化物 第一渠溝 犧牲基板 鈦層 銅層 種層 第一光阻 第一光阻圖案 O:\89\89662.DOC -67- 200419159 552 , 664 , 756 130 , 272 , 306 , 316 131 , 212 , 266 132a , 132b , 288 134 , 264 136,210,265,338,410a,410b,460, 560 , 762 138 , 148 , 282 , 378 140 , 214 142,222,270,414,560,570,678, 762 , 772 146 , 280 258 , 334b , 426 274 276 , 424 , 476 , 578 , 682 278 280 282 300 310 320 322 324a 324b 介電質板 傳導膜 對齊鍵 第二光阻 第二光阻圖案 支撐板 第三光阻 第三光阻圖案 黏著劑 第二渠溝 第四光阻 第四光阻圖案 第三渠溝 第一犧牲基板 第二犧牲基板 第一探針 第二探針 單元導體 光束構件 檢測尖端 連結尖端 O:\89\89662.DOC -68- 200419159 342 薄膜 370a,370b,418,472,556,656,810, 陶瓷板 820 362a,362b,370 介電質 374a , 374b 傳導層 386a , 386b 薄層 404 槽 452 , 558 , 660 , 662 , 754 第一種層 456 , 562 , 666 , 764 第一導體 458 , 564 , 668 , 766 第一鍍金層 474 , 568 , 760 第二種層 478 , 572 , 674 , 774 第二導體 480 , 676 , 776 第二鍍金層 482 , 578 , 582 第五光阻圖案 566 第一保護膜 576 , 670 第二保護膜 652 塗佈材料 653 切割部 654 犧牲基板區塊 667 , 768 保護膜 758 鍍銅結構 770 第三種層 774 第三導體 821 , 822 端 O:\89\89662.DOC -69- 200419159 900 902 904 , 955 907 , 911 , 967 908 , 965 910 , 975 912 , 970 914,924,982 916 , 980 918 , 984 921 , 986 922 , 982 926 928 929 930 , 974 932 , 972 935 936 938 光束構件 檢測尖端 探針區塊 固定栓 第一介面板 第二介面板 探針固持器 錨閂 操縱器 導引執 彈簧 固定組件 上封閉黏著組件 下封閉黏著組件 壓縮錨閂 導引膜 捲帶式封裝 非等向性傳導膜 金屬板 高彈性橡膠 O:\89\89662.DOC -70-O: \ 89 \ 89662.DOC -66-200419159 30a, 30b, 282, 364, 376a, 376b 40 40a, 40b 60 70 90, 100, 218, 308, 318 9 10 10 110 110 93, 103, 112 95, 105, 114 97a, 97b, 107a, 144, 467, 551, 655, 752 98 108, 118 109, 304, 314, 370a, 370b, 420, 428, 462, 470, 484, 554, 580, 658, 684, 782, 784 116a, 256a, 256b, 334a, 416 120, 200, 250, 330, 400, 450, 550, 650, 750 122, 202, 261 124, 204, 262 126, 206, 260, 336, 408a, 408b 128, 208, 252 129, 210, 254, 332, 402a, 402b, 454, support component conductive material, thin conductive material, plate-shaped support component, gold-plated support plate, first protruding area, central groove, second protruding area, trench under conductor Upper conductor epoxide first trench sacrificial substrate titanium layer copper layer seed layer first photoresist first photoresist pattern O: \ 89 \ 89662.DOC -67- 200419159 552, 664, 756 130, 272, 306, 316 131, 212, 266 132a, 132b, 288 134, 264 136, 210, 265, 338, 410a, 410b, 460, 560 762 138, 148, 282, 378 140, 214 142, 222, 270, 414, 560, 570, 678, 762, 772, 146, 280, 258, 334b, 426, 274 276, 424, 476, 578, 682 278 280 282 300 310 320 322 324a 324b Dielectric plate conductive film alignment key second photoresist second photoresist pattern support plate third photoresist third photoresist pattern adhesive second trench fourth photoresist fourth photoresist pattern third Trench first sacrificial substrate second sacrificial substrate first probe second probe unit conductor beam member detection tip connection tip O: \ 89 \ 89662.DOC -68- 200419159 342 film 370a, 370b, 418, 472, 556, 656, 810, ceramic plate 820 362a, 362b, 370 dielectric 374a, 374b conductive layer 386a, 386b thin layer 404 slot 452, 558, 660, 662, 754 first layer 456, 562, 666, 764 first conductor 458, 564, 668, 766 First gold plating layer 474, 568, 760 Second layer 478, 572, 674, 774 Second conductor 480, 676, 776 Second gold plating layer 482, 578, 582 Fifth photoresist pattern 566 First protection 576, 670 Second protective film 652 Coating material 653 Cutting section 654 Sacrificial substrate block 667, 768 Protective film 758 Copper-plated structure 770 Third layer 774 Third conductor 821, 822 Terminal O: \ 89 \ 89662.DOC- 69- 200419159 900 902 904, 955 907, 911, 967 908, 965 910, 975 912, 970 914, 924, 982 916, 980 918, 984 921, 986 922, 982 926 928 929 930, 974 932, 972 935 936 938 Beam member detection Tip probe block fixing bolt First interface panel Second interface panel probe holder Anchor manipulator Guidance holder Spring fixed component Closed adhesive component Lower closed adhesive component Compression anchor Guide film tape type Encapsulated non-isotropic conductive film metal plate high elastic rubber O: \ 89 \ 89662.DOC -70-
Claims (1)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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KR10-2002-0072990A KR100474420B1 (en) | 2002-11-22 | 2002-11-22 | Probe sheet for testing flat pannel display, method thereby, probe assembly having it |
KR10-2002-0082273A KR100450310B1 (en) | 2002-12-23 | 2002-12-23 | Method for manufacturing probe for testing flat pannel display, probe thereby, probe assembly having it |
KR10-2003-0007654A KR100517729B1 (en) | 2003-02-07 | 2003-02-07 | Probe for manufacturing probe for testing flat pannel display, probe thereby, probe assembly having its |
KR1020030065988A KR100554180B1 (en) | 2003-09-23 | 2003-09-23 | Manufacturing method of probe for testing flat panel display and probe thereby |
Publications (2)
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TW200419159A true TW200419159A (en) | 2004-10-01 |
TWI242647B TWI242647B (en) | 2005-11-01 |
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TW92132733A TWI242647B (en) | 2002-11-22 | 2003-11-21 | Probe for testing flat panel display and manufacturing method thereof |
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JP (1) | JP4430621B2 (en) |
AU (1) | AU2003282421A1 (en) |
TW (1) | TWI242647B (en) |
WO (1) | WO2004049429A1 (en) |
Cited By (3)
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TWI403739B (en) * | 2006-10-09 | 2013-08-01 | Samsung Display Co Ltd | Panel inspection apparatus and method |
TWI468697B (en) * | 2010-11-29 | 2015-01-11 | Seiken Co | Contact fixture for inspection |
TWI613450B (en) * | 2012-12-04 | 2018-02-01 | Japan Electronic Mat Corporation | Electrical contact |
Families Citing this family (9)
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JP4789686B2 (en) * | 2006-04-05 | 2011-10-12 | 株式会社ユニオンアロー・テクノロジー | Microprobe unit using microprobe guide and staggered microprobe unit |
KR100773732B1 (en) * | 2006-05-09 | 2007-11-09 | 주식회사 파이컴 | Probe unit and probe apparatus having the same |
KR101152182B1 (en) * | 2010-05-04 | 2012-06-15 | 주식회사디아이 | Probe film used probe block and method for manufacturing thereof |
JP2012047674A (en) * | 2010-08-30 | 2012-03-08 | Advantest Corp | Dicing substrate for test, probe, and semiconductor wafer testing apparatus |
KR101582956B1 (en) * | 2013-12-30 | 2016-01-06 | 주식회사 이노글로벌 | Semiconductor test socket and manufacturing method thereof |
CN105093574B (en) * | 2015-06-05 | 2018-06-08 | 京东方科技集团股份有限公司 | Display panel monitor station |
KR101757617B1 (en) * | 2016-01-21 | 2017-07-27 | 주식회사 이노글로벌 | By-directional electrically conductive pattern module and semiconductor test socket using the same, method for manufacturing by-directional electrically conductive pattern module |
KR102280651B1 (en) * | 2018-12-26 | 2021-07-23 | 주식회사 아이에스시 | Connector for electrical connection and manufacturing method thereof |
CN113295893B (en) * | 2021-05-26 | 2022-08-02 | 深圳市索麦科技有限公司 | Touch screen sensitivity detection device for tablet computer |
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JP3095807B2 (en) * | 1991-05-22 | 2000-10-10 | 東京エレクトロン株式会社 | Inspection equipment for semiconductor devices |
JPH05215814A (en) * | 1991-05-24 | 1993-08-27 | Tokyo Electron Yamanashi Kk | Semiconductor device inspecting device |
JPH06213928A (en) * | 1993-01-18 | 1994-08-05 | Tokyo Electron Ltd | Manufacture of probe head |
US6499216B1 (en) * | 1994-07-07 | 2002-12-31 | Tessera, Inc. | Methods and structures for electronic probing arrays |
JPH08211099A (en) * | 1995-01-31 | 1996-08-20 | Aica Kogyo Co Ltd | Electrode holder and electrode unit for electric signal measurement, and their manufacture |
DE19538792C2 (en) * | 1995-10-18 | 2000-08-03 | Ibm | Contact probe arrangement for electrically connecting a test device to the circular connection surfaces of a test object |
JP3592441B2 (en) * | 1996-05-10 | 2004-11-24 | 日本電子材料株式会社 | Vertical probe card |
US5869974A (en) * | 1996-04-01 | 1999-02-09 | Micron Technology, Inc. | Micromachined probe card having compliant contact members for testing semiconductor wafers |
KR100471341B1 (en) * | 1996-05-23 | 2005-07-21 | 제네시스 테크놀로지 가부시키가이샤 | Contact Probe and Probe Device with It |
SG108210A1 (en) * | 1998-06-19 | 2005-01-28 | Advantest Corp | Probe contactor formed by photolithography process |
-
2003
- 2003-11-21 AU AU2003282421A patent/AU2003282421A1/en not_active Abandoned
- 2003-11-21 JP JP2005510296A patent/JP4430621B2/en not_active Expired - Fee Related
- 2003-11-21 TW TW92132733A patent/TWI242647B/en not_active IP Right Cessation
- 2003-11-21 WO PCT/KR2003/002524 patent/WO2004049429A1/en active Application Filing
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI403739B (en) * | 2006-10-09 | 2013-08-01 | Samsung Display Co Ltd | Panel inspection apparatus and method |
TWI468697B (en) * | 2010-11-29 | 2015-01-11 | Seiken Co | Contact fixture for inspection |
TWI613450B (en) * | 2012-12-04 | 2018-02-01 | Japan Electronic Mat Corporation | Electrical contact |
Also Published As
Publication number | Publication date |
---|---|
WO2004049429A1 (en) | 2004-06-10 |
TWI242647B (en) | 2005-11-01 |
JP2006507512A (en) | 2006-03-02 |
JP4430621B2 (en) | 2010-03-10 |
AU2003282421A1 (en) | 2004-06-18 |
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