TWI231529B - Method of forming nanocrystals in a memory device - Google Patents
Method of forming nanocrystals in a memory device Download PDFInfo
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- TWI231529B TWI231529B TW092115688A TW92115688A TWI231529B TW I231529 B TWI231529 B TW I231529B TW 092115688 A TW092115688 A TW 092115688A TW 92115688 A TW92115688 A TW 92115688A TW I231529 B TWI231529 B TW I231529B
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- 239000002159 nanocrystal Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims description 27
- 239000002243 precursor Substances 0.000 claims abstract description 47
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000012545 processing Methods 0.000 claims abstract description 21
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910000077 silane Inorganic materials 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 claims description 4
- OTMSDBZUPAUEDD-UHFFFAOYSA-N Ethane Chemical compound CC OTMSDBZUPAUEDD-UHFFFAOYSA-N 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- 239000012071 phase Substances 0.000 claims 10
- 239000000126 substance Substances 0.000 claims 8
- 238000000151 deposition Methods 0.000 claims 5
- 230000008021 deposition Effects 0.000 claims 5
- 238000001947 vapour-phase growth Methods 0.000 claims 3
- 238000007740 vapor deposition Methods 0.000 claims 2
- 239000012808 vapor phase Substances 0.000 claims 2
- 238000009825 accumulation Methods 0.000 claims 1
- 239000000443 aerosol Substances 0.000 claims 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 abstract description 9
- 230000006911 nucleation Effects 0.000 description 21
- 238000010899 nucleation Methods 0.000 description 21
- 239000007789 gas Substances 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 230000012010 growth Effects 0.000 description 17
- 230000005641 tunneling Effects 0.000 description 17
- 239000010703 silicon Substances 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000013500 data storage Methods 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 238000003795 desorption Methods 0.000 description 2
- 238000010574 gas phase reaction Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052778 Plutonium Inorganic materials 0.000 description 1
- 229910007264 Si2H6 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000003698 anagen phase Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- KCWYOFZQRFCIIE-UHFFFAOYSA-N ethylsilane Chemical compound CC[SiH3] KCWYOFZQRFCIIE-UHFFFAOYSA-N 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003446 memory effect Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 229910052762 osmium Inorganic materials 0.000 description 1
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- OYEHPCDNVJXUIW-UHFFFAOYSA-N plutonium atom Chemical compound [Pu] OYEHPCDNVJXUIW-UHFFFAOYSA-N 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 150000004756 silanes Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/24—Deposition of silicon only
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
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- Non-Volatile Memory (AREA)
- Chemical Vapour Deposition (AREA)
Description
1231529 玖、發明說明: 【發明所屬之技術領域】 本申請案於2002年8月30曰提出美國專利申請,案號為 10/23 1,556 〇 本發明一般係關於半導體領域,更明確言之,係關於記 憶體裝置。 【先前技術】 電性可抹除可程式化唯讀記憶體(ElectricaUy erasaMe programmable read only memory ; EEPROM)結構常用於積 體電路供非揮發性資料儲存。EEPROM裝置結構常包括形 成於穿隧介電質上之多晶矽浮動閘以儲存電荷,而該介電 質係形成於半導體基板上。隨著裝置尺寸及電源供應電壓 減小’為防止資料保持故障,該穿隧介電質之厚度不能相 應減小。EEPROM裝置使用絕緣矽奈米晶體作為該浮動閘 之替代’並不具有該穿隧介電質中絕緣缺陷相同之易損性 ’因而可不以資料保持作折衷,而允許穿隧介電質及該運 作電壓之縮放。 為了具有藉EEPROM裝置之臨限電壓偏移測量之顯著的 記憶體效應,必需有一高密度矽奈米晶體,大約每平方釐 米1E12個奈米晶體。實現此種奈米晶體密度之一方法係使 用利用乙矽烷(Si2H6)之超高真空化學汽相沈積(uitra high vacuum chemical vapor deposition ; UHVCVD)製造奈米晶雔 。然而,每個晶圓之處理時間長度大於丨〇分鐘,從而導致 不合需要地增加之週期時間及製造費用。在穿隧介電質上 85658 !231529 形成奈米晶體之其他方法,導致產生明顯小於所需的密度( 如每平方釐米5E11個奈米晶體)。因此,必須在不增加製造 週期時間或費用之前提下,形成所需密度之奈米晶體。 【發明内容】 兩Μ #又方法係用於在電晶體中的一介電層上形成奈米 叢集,如奈米晶體,該電晶體使用於一具體實施例如一資 料儲存裝置。第一階段,即成核階段使用之一第一先驅物 與其下介電層(如穿隧介電質)之黏附係數高於第二階段,即 生長階段中使用之第二先驅物。此外,第二先驅物與用以 形成奈米晶體之材料的黏附係數高於其與其下介電層之係 數在項較佳具體貫施例中,第一先驅物係乙石夕院(氣體 ),且第二先驅物係矽烷(氣體)。此外,在此項較佳具體實 施例中,同樣之處理條件(溫度、壓力及合流氣體)係用於第 一階段及第二階段。在一項具體實施例中,兩階段方法期 間形成之奈米晶體係圖1所示之記憶體裝置的一部分。 【實施方式】 圖1說明一記憶體裝置1〇,其具有一半導體基板12、一源 極延伸13、一深源極區域14、一汲極延伸15、一深汲極區 域16' —穿隧介電質18、奈米晶體2〇、一控制介電質。、 一控制電極24及間隔物26。由於該記憶體裝置1〇所有部分 之形成,除奈米晶體20之形成以外,可使用傳統方法形成 ,該記憶體裝置10部分之形成將作簡要說明。該半導體基 板可能係矽、矽鍺、砷化鎵、絕緣體上矽(silie〇n_〇n_insuiat二 ’ SOI)等’或以上之組合。彳電層,如二氧化石夕係藉由熱 85658 1231529 生長、化學 A相沈積(chemical vapor deposition ; CVD)等, 或以上之組合形成於該半導體基板上,以用作穿隧介電質 1 8。该等奈米晶體係形成於介電層之上,此將參照圖2更詳 細地說明,且其在一項具體實施例中係該記憶體裝置1〇之 浮動閘。一含氮之鈍化層(未顯示)可視需要形成於該等奈米 晶體20之上。一控制介電質22 ,如二氧化矽、氧化铪、氧 化鋁等,及以上之組合,係沈積於該等奈米晶體2〇之上。 形成該控制介電質22之後,一導電材料,如多晶矽,以沈 積形成控制電極24。為了在將會被形成源極延伸13、深源 極區域14、汲極延伸15及汲極區域16之半導體基板12的區 域移除部分材料,蝕刻該控制電極24、控制介電質22、奈 米晶體20及穿隧介電質18。 蝕刻該等層後,藉由淺離子植入形成該源極延伸13及該 汲極延伸15。在形成該等延伸13及15後,在半導體基板上 沈積一介電層,如氮化矽,且對其異向性蝕刻,以形成與 控制電極24、控制介電質22、奈米晶體2〇及穿隧介電質18 相鄰之間隔物26。深離子植入期間,使用間隔物26及控制 電極24作為光罩,形成該深源極區域14及深汲極區域1 6。 所得之圮憶體裝置1〇作為在具有(嵌入式NVM裝置)或不具 有(如獨立NVM裝置)邏輯電晶體之半導體基板上形成的非 揮么性δ己j思體(non-volatile memory ; NVM)裝置尤其有用。 此外,該記憶體裝置丨〇係一資料儲存裝置。 4等奈米晶體20可如圖2所示使用奈米晶體製程3 〇形成 ,以實現大約每平方釐米1E12個奈米晶體之所需密度。在 85658 1231529 半導體基板12上形成介電層(圖1中穿隧介電質ι8)後,在該 奈米晶體製程30之步驟32中提供有具有介電層之半導體基 板12。然後在步驟34中將該半導體基板12放置於化學汽相 沈積(chemical vapor deposition ; CVD)室内。該 CVD 室最好 係一寒壁快速熱化學汽相沈積(rapid thermal chemical vapor deposition ; RTCVD)室,因為其最小化遠離半導體基 板12之氣相反應及成核,此為額外雜訊因數,且在接近半 導體基板12表面處促進有益之氣相反應。然而,該cvd室 可能係一超咼真空化學汽相沈積(ultra high vacuum chemical vapor deposition ; UHVCVD)室、一低壓化學汽相 沈積(low-pressure chemical vapor deposition ; LPCVD)室或 類似室。 在該CVD室中放置半導體基板12之後,如步驟36所示, 在第一預定處理條件下流入一第一先驅物氣體以成核奈米 晶體’遠等條件在一第一時間週期存在於該化學汽相沈積 室中,該步驟係圖2之第一階段(即奈米晶體形成之成核階 段)。在一項較佳具體實施例中,該等奈米晶體2〇係矽,因 而使用一含矽先驅物。矽烷(SiH4)及乙矽烷(ShH6)均係合適 之含矽先驅物。然而,乙矽烷在二氧化矽上之黏附係數高 於在矽上之黏附係數,其為用作穿隧介電層丨8較佳之材料 。矽烧在二氧化矽上之黏附係數低於在矽上之黏附係數。 由於對於奈米晶體形成之第一階段,需要形成許多成核位 置,該等先驅物相對於該穿隧介電質(如二氧化矽)及相對於 形成材料(如矽)之黏附係數,決定了所使用之先驅物。因而 85658 -9 - 1231529 .:所述之該具體實施例中乙矽烷應用於矽烷之上,其中 '牙随」包貝包括二氧化石夕,及形成之奈米晶體包括石夕。 '、料或不同先驅物之黏附係數的相對值,可由所觀察 之::時間獲得’該潛伏時間定義為成核之前的滯後時間。 當流入乙矽烷時,乙矽烷中的矽附著自身於穿隧介電質 18上已存在之石夕原子及穿隨介電質18自身上,由於乙石夕燒 與石夕及二氧化石夕之黏附係數,從而產生了新的成核位置。 此外,,乙石夕燒最好置於石夕烧上’因為乙石夕烧分離之溫度較 之石夕说更低,由於其不飽和焊接,形成與二氧化石夕及石夕表 面!!具有Γ單位黏附係數之亞w基。此將允許使用更低 狐度第預定處理條件包括大約4〇〇至6〇〇攝氏度,更 月確°之450至530攝氏度之基板溫度,及大約10至200 mTorr或更|父佳之1()至⑽mT。"之乙梦炫分壓。大約至 530度之溫度範圍最為合意,因為在低於450度之溫度下, 氫從表面脫附極慢,其阻止乙石夕院與穿随介電質Η反應以 形成成核位置,因而減小該等奈米晶體之密度。超過530攝 氏度之溫度則為不合意,係因二氧化石夕之脫附移除了石夕增 原子(即存在於穿隧介電質18表面上之矽原子)。藉由在低』 力且低溫T形成成核位置’且延伸成核時間’從而增加控 制成核此力’以防止形成過多成核位置,且隨後聚集為一 連續層或極大之奈米晶體。 為防止形成連續層,及在製造期間獲取較快之週期時間 ’也應控㈣方法之時間。較佳之時間應少於5〇秒,或更 佳應小於25秒,或最佳應在5與1〇秒之間。在另一具體實施 85658 1231529 ’該時間係在約30秒與150秒之間。惰性氣體(如氮、 气等)之口 ",L氣體,可在流入第一先驅物氣體時流入,以輔 助輪送第一先驅物氣體至半導體基板12上。最好不要使用 =為合流氣體,因為一旦乙矽烷分離,纟面反應物副產 7虱之脫附會由合流氣體中之氫阻止。應注意在其他CVD 知作中之所以t遍使用氫與料—起作為合流氣體,係因 為其有助於防切烧氣相分解為較氫。然而,低分壓結 己低概可抑制该氣相分解。同樣地,其他惰性氣體也可用 乍a々丨L氣,而不用關心氣相分解。由於在一項具體實施 :丨中合流氣體及第一先驅物氣體之存在,奈米晶體形成的 第一階段期間之總壓力約為18 T〇rr。 在一項具體實施例中形成成核位置之後,終止或結束一 項具體實施例中第一先驅物之流動。在一時間週期(在一項 具體實施例中約為〇至20秒)後,如步驟38所示,流入第二 且不同之先驅物氣體,以在第二預定處理條件下生長奈米 曰曰體’ 4等條件於第二時間週期存在於該化學汽相沈積室 内,該第二時間週期為圖3中奈米晶體形成之第二階段(即 生長階段)。在另一項具體實施例中,流入第一先驅物時流 入第二先驅物。最好在生長階段期間有一較慢之生長率, 從而可控制生長方法。如圖3所示在一既定溫度下,矽烷之 生長率係小於乙矽烷之生長率,因而第二先驅物最好係矽 烷。例如,圖3中在450攝氏度時,矽烷之生長率約為每秒 iE-6埃,然而,乙矽烷之生長率約為每秒1E_2埃。 成核位置之生長藉由附著於成核位置之矽烷中的石夕及沿 85658 1231529 半導體基板12表面之矽擴散。藉由在此生長階段降低溫度 ’矽需花費更長時間在生長期間擴散至成核位置,因而增 加生長階段之控制。 若第二先驅物與穿隧介電層18反 應則不合需要,其可導致奈米晶體之尺寸分佈過多變化。 因此’第二先驅物應與穿隧介電層18(即形成奈米晶體之曝 露層)較之其與奈米晶體自身具有更低之黏附係數。因而, 對於矽奈米晶體形成及二氧化矽穿隧介電層丨8,最好使用 石夕烧’因為其與;5夕之黏附係數約高於與二氧化石夕之黏附係 數四個等級。由於矽烷具有與矽比與二氧化矽更高之黏附 係數,矽烷將與現有之成核位置反應,而不與二氧化矽反 應並形成額外之成核位置,以放大或生長此成核位置為奈 米晶體。僅根據黏附係數乙矽烷係合乎需要的,但業已說 明由於其相對於石夕院更高之生長率而不合需要。此外,由 於乙石夕院較昂貴,最好使乙石夕烧之使用減至最小。 步驟38之第二預定處理條件可與步驟刊之第一處理條件 相同或等同。#第—及第二預定處理條件最好相同,且當 :步驟38轉換至步驟36時,在該㈣室中所變化的一切; 物所用的先驅物(如第一先驅物不再流入,且流入第二先驅 :,或第二先驅物與第—先驅物一起加入該室中)。為了在 :理期間改變溫度或壓力’有一相關於溫度變化之時間週 且其會不合需要地增加週期時間。 件:二’步驟38之第二處理條件可與步驟36之第-處理條 同。在一項具體實施例中,半導體基板12之溫度約為 85658 -12- 1231529 500至580攝氏度,且矽烷之分壓約為1〇至1〇〇〇1丁〇1^。可使 用惰性氣體(如氮或氬)之合流氣體。 步驟38之第二時間週期可與步驟36之第一時間週期相同 ,但疋该第二時間週期可以比該第一時間週期更長。咳第 二時間週期可為該第一時間週期之至少兩倍長。在一項具 體實施例中,該第二時間週期約為每晶圓3〇至4〇秒。在L 項較佳具體實施例中,步驟38及步驟36之組合時間係少於 或等於母晶圓約60秒,以達到有效之製造週期時間。 在奈米晶體20生長之後(即流入不同之第二先驅物氣體 之後),該等奈米晶體20可在惰性環境中退火,如氮,如圖 2中步驟4G所示’以獲取平衡形狀。退火溫度可約為750攝 氏度。也可使用任何用於退火方法之其他參數。 記憶體裝置1〇中使用之奈米晶體的所需尺寸可在3與7奈 米之間且在某些具體實施例中5奈米之目標直徑也係合適 的;丨¾•層18上之奈米晶體的覆蓋或區域密度可約為2〇% 。20〇/〇之區域密度對於+導體冑^製造也係合理的,由於 其在洋動閘結構所包括之奈米晶體之間隔中可提供一定公 差位準。隸也可獲取更高之區域密度,在此類更高區域 密度之具體實施财m緣儲存元件之接近可增加隨 後奈米晶體間電荷轉移之可能性,因而降低其絕緣之有益 效果。 藉由使用以上方法並奈米晶體形成之成核階段及生長階 段使用不同先驅物,可允許相對於其他方法增加週期時間 且減少製造費用之本半s w‘ 買 < 不木日日粗製造。此外,藉由使用所述之 85658 -13- 1231529 兩階段方法,可較好地控制奈米晶體之成核及生長。 於前面的說明書中,已參考特定具體實施例來說明本發 明:然而,熟知本技術人士應明白可對本發明作各種修改 及變化’而不致背離如下申請專利範圍所提出的本發明之 範嘴。例如,也可使用具有適合成核及生長階段特^之其 他先驅物。此外,奈米晶體可為除矽以 緒.且可選擇是否雜捧。此外,可在除穿随;;電 他層域任意介電層上形成奈米晶體。在此項具體實施例 中。玄#先驅物與I米晶體形成層μ的黏附係妻文與其形成 之材料相關。因此,說明書暨附圖應視為解說,而不應視 為限制,並且所有此類的修改皆屬本發明範疇内。 關於特定具體實施例的優勢、其他優點及問題解決方案 已如上述。但是,豸等優勢、優點、問題解決方案及產生 或彰顯任何優勢、優點或解決方案的任何元件,均不應視 為任何或所有t料㈣__、必要項或基本功能或 疋件°本文中所使用的術語「包括」、「包含」或其任何其 他夂化’都疋用來涵蓋非專有内含項’使得包括元件清單 的程序、方法、物品或裝置,不僅包括這些元件,而且還 包括未明確列出或此類程序、方法、物品或裝置原有的其 他元件。 【圖式簡單說明】 本發明已藉由實例來進行說明,但本發明未限定在附圖 内,其中相似的參考符號代表相似的元件,並且其中: 圖h兄明已根據本發明之_項具體實施例形成奈米晶體 85658 -14- 1231529 之記憶體裝置的斷面圖; 具體實施例形成圖1奈米晶體之 圖2 έ兒明根據本發明一項 流程圖;而且 圖3說明兩切先驅物的生長率對比溫度之曲線圖。 熟悉此項技術者可以發現,為了簡化及清楚起見 有需要將圖式中的元件依照比例繪製。例如,為 瞭解本發明的具體實施例,圖中部分元件的尺;有助於 件比起來可能過度放大。 U其他元 【圖式代表符號說明】 1 0 記憶體裝置 12 半導體基板 13 源極延伸 14 深源極區域 15 没極延伸 16 汲極區域 1 8 穿隧介電層 20 奈米晶體 22 控制介電質 24 控制電極 26 間隔物 3 〇 製程 32 步驟 34 步驟 36 步驟 38 步驟 40 步驟 85658 -15-
Claims (1)
1231529 拾、申請專利範圍: 1. 一種形成奈米晶體之方法(30),其包括·· 提供(32)—基板(12); 形成一覆蓋該基板之介電質(18); 在一化學汽相沈積室中放置(34)該基板; ,:-第-階段期間將一第一先驅物氣體流入(2 6)該化 學’飞相沈積室中’以第一預定條件在該介電質上成核奈 米晶體(20)’該等第一預定條件於一第一時間週期存在於 該化學汽相沈積室中; 終止將该第一先驅物氣體流入該化學汽相沈積室中; 以及 ▲在-第二階段期間將—不同之第二先驅物氣體流入⑽ 該化學汽相沈積室巾,以在第二預定條件下生長該等奈 米曰Β體,該等第:預定條件於—第二時間存在於該 化學汽相沈積室中。 I如申請專利範圍第1項之方法,其·進一步包括: 在机入a亥不同之第二先驅物氣體後於-惰性環境中退 火(40)該等奈米晶體。 3·如申請專利範圍第旧之方法,其進一步包括使該等第二 預定條件等同於該等第_預定條件。 4. -種形成奈米晶體之方法⑽,其包括: 提供(32)—基板(12); 形成—覆蓋該基板之介電質(18); 在—化學汽相沈積室中放置(34)該基板; 85658 1231529 在-第-階段期間,將一第一先驅物氣體流入㈠6)該化 學汽相沈積室中,以第一預定處理條件在該介電質上成 核奈米晶體,該等第—預定處理條件於—第__時間週期 存在於該化學汽相沈積室中;以及 在該第-階段後之-第二階段期間,將一第二先驅物 氣體流M38)該化學汽相沈積室中,以在第三預定處理條 件下生長该等奈米晶體’該等第二預定處理條件於一第 一%間週期存在於該化學汽相沈積室中。 5. 6. 如申請專利範圍第4項之方法,其進一步包括: 丄在終止將該第-先驅物氣體流入該化學汽相沈積室之 前’將該第二先驅物氣體流入(38)該化學汽相沈積室中。 如申請專㈣圍第4項之方法,其進—步包括在該化學汽 相沈積室_實_化學汽相沈積’作為—快速熱化學汽 才 /匕積(rapid thermal chemical vapor deposition ; RTCVD)。 如申請專利範圍第4項之方法’其進一步包括使用乙矽烷 實現該第-先驅物氣體’使用矽烷實現該第二先驅物氣 體’且使用二氧化矽實現該介電質。 8· —種形成奈米晶體(2〇)之方法(3〇),其包括: 提供(32)一半導體基板(12); 形成一覆蓋該半導體基板之介電層(18); 在一化學汽相沈積室中放置(34)該半導體基板,以實現 該介電層上材料之一快速熱化學汽相沈積; 在一第一階段期間,於一第一時間週期將乙矽烷氣體 流入(36)該化學汽相沈積室中,以在該介電層上形成複數 85658 -2- 1231529 個奈米晶體,此時該化學汽相沈積室中的溫度在攝氏 度至530攝氏度範圍内,且乙石夕烧氣體分壓在⑺至⑽ mT〇rr之範圍内;以及 在該第一階段後之-第二階段期間,於-第二時間週 期將石夕烧氣體流入(38)該化學汽相沈積室中,以在該化學 =相沈積室中存在之處理條件下生長奈米晶體,該化學 汽相沈積室之溫度及分壓至少與該第一時間週期期間相 同’且該第二時間週期之長度長於該第一時間週期。 9· 一種形成奈米晶體(2〇)之方法(3〇),其包括·· 提供(32)—基板(12); 形成一覆蓋該基板之介電質(1 8); 在一化學汽相沈積室中放置(34)該基板; 在一第一階段期間,將該介電質之一表面上具有一第 一黏附係數之—第—先驅物氣體流人(3 6)該化學汽相沈 積室中^第1定處理條件在該介電質上成核奈米晶 體°玄等第一預定處理條件於一第一時間週期存在於該 化學汽相沈積室_ ;以及 在一第-階段期間,將-第二先驅物氣體流入(38)該化 學汽㈣積室中,以在第二預定處理條件下生長奈米晶 體4等第_預定處理條件於—第二時間週期存在於該 化子汽相沈積至中,該第二先驅物氣體在該介電質之該 表面上具有一第二黏附係數,其小於該第一黏附係數, 且在4等奈米晶體之一表面上具有高於該第二黏附係數 之一第二黏附係數。 85658 1231529 10.如申請專利範圍第9項之方法,其進一步包括在開始將該 第二先驅物氣體流入該化學汽相沈積室之前,停止流入 該第一先驅物氣體。 85658
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Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7121474B2 (en) * | 2002-06-18 | 2006-10-17 | Intel Corporation | Electro-optical nanocrystal memory device |
FR2847567B1 (fr) | 2002-11-22 | 2005-07-01 | Commissariat Energie Atomique | Procede de realisation par cvd de nano-structures de materiau semi-conducteur sur dielectrique, de tailles homogenes et controlees |
KR100526463B1 (ko) * | 2003-05-07 | 2005-11-08 | 매그나칩 반도체 유한회사 | 반도체 소자의 제조 방법 |
TWI276206B (en) * | 2003-11-25 | 2007-03-11 | Promos Technologies Inc | Method for fabricating flash memory device and structure thereof |
US20050258470A1 (en) * | 2004-05-20 | 2005-11-24 | Bohumil Lojek | Gate stack of nanocrystal memory and method for forming same |
US7265036B2 (en) * | 2004-07-23 | 2007-09-04 | Applied Materials, Inc. | Deposition of nano-crystal silicon using a single wafer chamber |
KR100615093B1 (ko) * | 2004-08-24 | 2006-08-22 | 삼성전자주식회사 | 나노크리스탈을 갖는 비휘발성 메모리 소자의 제조방법 |
US20060046383A1 (en) * | 2004-09-02 | 2006-03-02 | Shenlin Chen | Method for forming a nanocrystal floating gate for a flash memory device |
US7307888B2 (en) * | 2004-09-09 | 2007-12-11 | Macronix International Co., Ltd. | Method and apparatus for operating nonvolatile memory in a parallel arrangement |
US7324376B2 (en) * | 2004-09-09 | 2008-01-29 | Macronix International Co., Ltd. | Method and apparatus for operating nonvolatile memory cells in a series arrangement |
US7345920B2 (en) | 2004-09-09 | 2008-03-18 | Macronix International Co., Ltd. | Method and apparatus for sensing in charge trapping non-volatile memory |
US7327611B2 (en) * | 2004-09-09 | 2008-02-05 | Macronix International Co., Ltd. | Method and apparatus for operating charge trapping nonvolatile memory |
US7170785B2 (en) * | 2004-09-09 | 2007-01-30 | Macronix International Co., Ltd. | Method and apparatus for operating a string of charge trapping memory cells |
US7327607B2 (en) * | 2004-09-09 | 2008-02-05 | Macronix International Co., Ltd. | Method and apparatus for operating nonvolatile memory cells in a series arrangement |
US7813160B2 (en) * | 2005-01-11 | 2010-10-12 | The Trustees Of The University Of Pennsylvania | Nanocrystal quantum dot memory devices |
US20060189079A1 (en) * | 2005-02-24 | 2006-08-24 | Merchant Tushar P | Method of forming nanoclusters |
US7101760B1 (en) | 2005-03-31 | 2006-09-05 | Atmel Corporation | Charge trapping nanocrystal dielectric for non-volatile memory transistor |
US20060220094A1 (en) * | 2005-03-31 | 2006-10-05 | Bohumil Lojek | Non-volatile memory transistor with nanotube floating gate |
US7241695B2 (en) * | 2005-10-06 | 2007-07-10 | Freescale Semiconductor, Inc. | Semiconductor device having nano-pillars and method therefor |
US7491599B2 (en) * | 2005-12-09 | 2009-02-17 | Macronix International Co., Ltd. | Gated diode nonvolatile memory process |
US7269062B2 (en) * | 2005-12-09 | 2007-09-11 | Macronix International Co., Ltd. | Gated diode nonvolatile memory cell |
US7888707B2 (en) * | 2005-12-09 | 2011-02-15 | Macronix International Co., Ltd. | Gated diode nonvolatile memory process |
US7283389B2 (en) | 2005-12-09 | 2007-10-16 | Macronix International Co., Ltd. | Gated diode nonvolatile memory cell array |
US7272038B2 (en) * | 2005-12-09 | 2007-09-18 | Macronix International Co., Ltd. | Method for operating gated diode nonvolatile memory cell |
KR100837413B1 (ko) * | 2006-02-28 | 2008-06-12 | 삼성전자주식회사 | 나노결정을 포함하는 메모리 소자 제조 방법 및 이에 의해제조된 메모리 소자 |
KR100785015B1 (ko) * | 2006-05-18 | 2007-12-12 | 삼성전자주식회사 | 실리콘 나노 결정을 플로팅 게이트로 구비하는 비휘발성메모리 소자 및 그 제조방법 |
US7432158B1 (en) | 2006-07-25 | 2008-10-07 | Freescale Semiconductor, Inc. | Method for retaining nanocluster size and electrical characteristics during processing |
US7445984B2 (en) | 2006-07-25 | 2008-11-04 | Freescale Semiconductor, Inc. | Method for removing nanoclusters from selected regions |
US20080246101A1 (en) * | 2007-04-05 | 2008-10-09 | Applied Materials Inc. | Method of poly-silicon grain structure formation |
CN101459094B (zh) * | 2007-12-13 | 2010-09-29 | 中芯国际集成电路制造(上海)有限公司 | 测量半球形颗粒多晶硅层厚度的方法 |
US7995384B2 (en) * | 2008-08-15 | 2011-08-09 | Macronix International Co., Ltd. | Electrically isolated gated diode nonvolatile memory |
US7871886B2 (en) | 2008-12-19 | 2011-01-18 | Freescale Semiconductor, Inc. | Nanocrystal memory with differential energy bands and method of formation |
US7799634B2 (en) * | 2008-12-19 | 2010-09-21 | Freescale Semiconductor, Inc. | Method of forming nanocrystals |
US8536039B2 (en) * | 2010-03-25 | 2013-09-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nano-crystal gate structure for non-volatile memory |
JP5337269B2 (ja) * | 2010-04-27 | 2013-11-06 | 東京エレクトロン株式会社 | アモルファスシリコン膜の成膜方法および成膜装置 |
WO2012090819A1 (ja) * | 2010-12-28 | 2012-07-05 | シャープ株式会社 | 微結晶シリコン膜の製造方法、微結晶シリコン膜、電気素子および表示装置 |
US8329543B2 (en) * | 2011-04-12 | 2012-12-11 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device having nanocrystals |
US8329544B2 (en) | 2011-04-12 | 2012-12-11 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device having nanocrystals |
US8679912B2 (en) | 2012-01-31 | 2014-03-25 | Freescale Semiconductor, Inc. | Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor |
US8951892B2 (en) | 2012-06-29 | 2015-02-10 | Freescale Semiconductor, Inc. | Applications for nanopillar structures |
CN104952802B (zh) * | 2014-03-25 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | 闪存存储单元的形成方法 |
US9356106B2 (en) * | 2014-09-04 | 2016-05-31 | Freescale Semiconductor, Inc. | Method to form self-aligned high density nanocrystals |
US9929007B2 (en) * | 2014-12-26 | 2018-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | e-Flash Si dot nitrogen passivation for trap reduction |
TWI711728B (zh) * | 2016-08-29 | 2020-12-01 | 聯華電子股份有限公司 | 形成晶格結構的方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0659911A1 (en) | 1993-12-23 | 1995-06-28 | International Business Machines Corporation | Method to form a polycrystalline film on a substrate |
US5850064A (en) | 1997-04-11 | 1998-12-15 | Starfire Electronics Development & Marketing, Ltd. | Method for photolytic liquid phase synthesis of silicon and germanium nanocrystalline materials |
US6060743A (en) | 1997-05-21 | 2000-05-09 | Kabushiki Kaisha Toshiba | Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same |
JP3727449B2 (ja) | 1997-09-30 | 2005-12-14 | シャープ株式会社 | 半導体ナノ結晶の製造方法 |
US6320784B1 (en) * | 2000-03-14 | 2001-11-20 | Motorola, Inc. | Memory cell and method for programming thereof |
US6344403B1 (en) | 2000-06-16 | 2002-02-05 | Motorola, Inc. | Memory device and method for manufacture |
US6297095B1 (en) | 2000-06-16 | 2001-10-02 | Motorola, Inc. | Memory device that includes passivated nanoclusters and method for manufacture |
US6455372B1 (en) | 2000-08-14 | 2002-09-24 | Micron Technology, Inc. | Nucleation for improved flash erase characteristics |
CN1305232A (zh) * | 2001-02-27 | 2001-07-25 | 南京大学 | 锗/硅复合纳米晶粒浮栅结构mosfet存储器 |
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