TWI222197B - Manufacturing method of semiconductor device and electronic apparatus, and calculating method of connection condition - Google Patents
Manufacturing method of semiconductor device and electronic apparatus, and calculating method of connection condition Download PDFInfo
- Publication number
- TWI222197B TWI222197B TW092103143A TW92103143A TWI222197B TW I222197 B TWI222197 B TW I222197B TW 092103143 A TW092103143 A TW 092103143A TW 92103143 A TW92103143 A TW 92103143A TW I222197 B TWI222197 B TW I222197B
- Authority
- TW
- Taiwan
- Prior art keywords
- connection
- temperature
- solder
- connection conditions
- range
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 150000001875 compounds Chemical class 0.000 claims abstract description 24
- 238000011156 evaluation Methods 0.000 claims abstract description 10
- 230000006378 damage Effects 0.000 claims abstract description 9
- 229910000679 solder Inorganic materials 0.000 claims description 72
- 238000010438 heat treatment Methods 0.000 claims description 19
- 230000007423 decrease Effects 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910017944 Ag—Cu Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 238000004364 calculation method Methods 0.000 claims description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 2
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 claims 2
- 239000011574 phosphorus Substances 0.000 claims 2
- 229910000969 tin-silver-copper Inorganic materials 0.000 claims 2
- 238000002844 melting Methods 0.000 abstract description 54
- 230000008018 melting Effects 0.000 abstract description 54
- 238000005476 soldering Methods 0.000 abstract description 6
- 238000009736 wetting Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 13
- 230000004913 activation Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 238000005452 bending Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000005253 cladding Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 229910018104 Ni-P Inorganic materials 0.000 description 2
- 229910018536 Ni—P Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000012552 review Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
Classifications
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
- Investigating And Analyzing Materials By Characteristic Methods (AREA)
Description
1222197 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係關於算i出將以半導體裝置爲代表之電子零件 連接在電子電路基板上之連接條件的算出方法。 【先前技術】 在以第7圖所示之焊錫凸塊將電子零件搭載連接於基 板上時,該焊接的溫度曲線係考慮對電子零件所造成之熱 衝擊和浸溼等焊接性而決定(仲田周次;往後之微焊接技 術,工業調查會、1991、 P.174〜P.179)。 另外,存在有種種之迴焊裝置,而且依據連接之電子 零件和基板的大小,其連接條件也不同。 那些連接條件,即加熱條件,主要是由焊錫之浸溼性 和電子零件的耐熱溫度所決定。 第1圖顯示其代表性的迴焊條件,第2圖顯示第1圖 之220°C以上的部份。 【發明內容】 發明揭示(發明槪要) 在先前的技術中,迴焊條件對焊接後之連接強度所造 成的影響,完全未被考慮到。 即在第1圖之迴焊條件中,在1片基板上連接大小不 同的多數電子零件(含半導體裝置)時,由於熱容量差存 在,所以對小電子零件的連接部施以高的加熱過程。熱負 (2) (2)1222197 載如太大,連接界面強度降低,會產生在界面破壞之問題 〇 另外,在進行重工時,對存在於其周邊之電子零件的 連接部施以加熱過程,又重工次數如增加,加熱過程被累 算。如此加熱過程一被累算,熱負載在電子零件和基板的 連接部會變大,在連接界面破壞的可能性提高。 特別是在使用於連接的焊錫如使用以Sn爲主成分, 含Ag及Cu之至少其中一方的無鉛焊錫(特別是,Sn-3( 重量%)Ag-0.5(重量%)Cu)時,對熱負載顯著變得脆弱。 此係無鉛焊錫含多量的容易與電極部之包覆材料反應之 Sn,而且焊錫之融點也比Sn37Pb高,因此作業溫度變高 ,對界面強度造成之影響更大所致。 即本申請案之發明的目的之一爲:提升在利用無鉛焊 錫以將電子零件構裝在電子基板的電極時之電子裝置的連 接可靠度。 另外,本申請案之發明的另一目的爲提供:適用於此 種連接之迴焊條件、適用該種連接之半導體裝置。 上述目的是以如下之形態而獲得解決。 在以含Ag、Cu而以Sn爲主成分之無鉛焊錫連接具 有以Ni和P爲主成分之金屬層的半導體裝置,和具備端 子的電子電路基板時,如以220°C以上、2 50 °C以下之溫 度,加熱配置在電子電路的金屬層和電子電路基板的端子 間之焊錫40秒以上、80秒以下予以接合時,可以提升電 子電路基板和半導體裝置間的接合可靠度,所以能夠提升 (3) (3)1222197 電子裝置之可靠度。 上述加熱條件之220 °C以上的平均溫昇速度或者平均 降溫速度如設爲〇.7°C / s以上、4.0°C / s以下,更可以 提升連接可靠度。 上述加熱條件如以2 3 0 °C / s以上之溫度加熱焊錫3 5 秒以上,更可以提升連接可靠度。 【實施方式】 發明的最好實施形態 (實施例1 ) 利用第7圖之流程來說明本發明之連接技術。 第7 ( a )圖係焊錫加熱前之狀態,第7 ( b )圖爲焊 錫加熱後狀態。 在電子電路基板14的在構成電子電路的一部份之Cu 電極銲墊(或者配線)10上形成以無電解Ni-P電鍍之金 屬層和印刷Sn3 AgO. 5 Cu之焊錫膏的焊錫層。 電子零件9係在其背面形成電極10,在電極10上形 成 Ni之金屬層1 1,在該金屬層1 1上以初期迴焊 Sn3Ag0.5Cu之焊錫球,以形成焊錫凸塊12。 在此種電子零件A(28mm四方、256腳、1.27mm間 距、銲墊直徑0.6mm)、電子零件B(18mm四方、256腳 、0.8間距、銲墊直徑0.4mm)、電子零件C(5mm四方、8 腳、1.2 7mm間距、銲墊直徑0.6 mm)之3種半導體產品( 封裝零件)形成凸塊,連接在電子電路基板。 -8- (4) (4)1222197 第3圖顯示對電子電路基板的連接條件。 如第3圖所示,零件A之焊錫凸塊形成,是在最高 溫度240°C、217°C以上之熔化時間30s的條件下進行, 零件B之焊錫凸塊形成,是在最高溫度24 5 °C、217°C以 上之熔化時間3 4 s之條件下進行,零件C之焊錫凸塊形成 ,是在最高溫度25 5 °C、217°C以上的熔化時間38s之條 件下進行。 製作以以上之條件來連接電子零件之電子基板共20 片,加以迴焊,進行衝擊彎曲試驗,評估連接可靠度。 不管全部之封裝零件上面中央部的溫度是在第1圖所 示之連接條件內接合,在最小且連接條件達到最高溫度 2 5 5 °C的零件C共20個中,於7個之測試基板由連接界面 破壞。 由此,知道即使以第1圖之曲線資料連接,也可能產 生連接不良。 (實施例2 ) 對於25mm四方、256腳(1.27mm間距、銲墊直徑 0.6mm )之封裝零件,進行藉由焊錫球之凸塊形成後,利 用焊錫膏連接於測試基板,焊錫球爲Sn3 AgO. 5 Cu (焊錫 球直徑0.75mm),焊鍚膏爲Sn3 AgO · 5 Cu,在電極銲墊中 使用無電解Ni-P電鍍(厚度8mm)以作爲包覆材料。焊 錫凸塊形成係在最高溫度24(TC、217°C以上之熔化時間 40s之條件下進行。對基板的連接條件設爲最高溫度230 -9 - (5) (5)1222197 °C、240°C、250°C ,Sn3 AgO. 5Cu 焊錫膏之融點 2 17 °C 以 上的熔化時間設爲40s、160s、240s予以連接。連接後進 行衝擊彎曲試驗,評估連接可靠度。第4圖顯示衝擊彎曲 試驗結果。由第4圖知道,在25 0°C、90s以上,240°C、 160s以上時,會發生連接界面的破壞。但是,在2 5 0 °C、 4 0 s,2 4 0 °C、9 0 s以下時,在衝擊彎曲試驗下,並無破壞 ,知道爲良好之連接。由以上,可決定在連接可靠度不降 低之區域,即最高溫度25 (TC時,以 220 °C以上之熔化時 間在80s以內,最高溫度240°C時,220°C以上之熔化時 間在150s以內爲適當條件。第5圖顯示對基板的連接適 當條件中,最高溫度250°C之情形。另外,第6圖顯示第 5圖之220t以上之部份。 由第4圖以及第6圖可以明白,在製造具有形成有藉 由形成在以Ni和P爲主成分之金屬層上之Sn-Ag-Cu系之 無鉛焊錫所形成的凸塊的半導體裝置,和具備電極之電子 電路基板的電子裝置之際,藉由在220°C以上、25 0 °C以 下之溫度區間將無鈴焊錫加熱4 0秒以上、8 0秒以下,可 以提升連接可靠度。 另外,在第6圖之2 1 7 °C以上範圍中,使加熱溫度的 平均溫昇速度或者平均降溫速度在0.7°C/s以上、4.0°C /s以下,可以更提升連接可靠度。 另外,使焊錫在25〇t以下、23〇°C / s以下的溫度加 熱3 5秒以上,可以進一步提升連接可靠度。 另外,由半導體裝置製造商和電子零件製造商將以下 -10- (6) (6)1222197 資訊··在具有以Ni和p爲主成分的金屬層上所形成的 Sn-Ag-Cu系的無錯焊錫構成之凸塊之半導體裝置中,可 以在2 2 0 °C以上、2 5 〇 °C以下之溫度範圍加熱上述無鉛焊 錫4 0秒以上、80秒以下和電子零件一齊以書面或者網際 網路公開給使用半導體裝置者時,身爲電子零件之使用者 的電子裝置製造商(set maker)便可以提供連接可靠度高 的電子電路裝置。 (實施例3及4 ) 接著,爲了更廣泛適用這些連接條見,一再檢討之結 果,得知以以下方法產生溫度曲線最好。 另外,形成在檢討用的電極上之電鍍層膜質因批次、 電鍍材料之製造商、電鍍裝置而不同,所以和上述實施例 多少有些誤差。 第8圖爲顯示求得不降低連接界面強度的溫度曲線的 流程圖。首先,使熔化溫度和熔化時間改變,在基板的連 接銲墊上連接焊錫。爲了簡化,以保持第9圖所示之熔化 溫度爲一定之溫度曲線進行連接。之後,以不同之條件進 行剪斷試驗,以此求得在連接界面不產生破壞之適當迴焊 條件的範圍。以此條件試驗之適當迴焊範圍爲基礎,判定 連接溫度曲線是否適當。 但是,此求得之適當迴焊範圍爲一定溫度的加熱曲線 之故’與第10圖使用在量產時之具有峰値的曲線不同, 所以無法原樣適用該適當迴焊範圍。因此,有無產生界面 -11 - (7) 1222197 破壞是由熱負載所決定,同樣由熱負載所決定之化合物厚 度相同則表示被給予同等之熱負載,以此想法爲基礎,利 用計算將一定溫度之加熱曲線的適當迴焊範圍轉換爲具有 峰値的加熱曲線的適當迴焊範圍。 如依據佐籐等:高可靠度微焊接技術,工業調查會, P. 2 3 3〜23 9,化合物厚度係遵循式(1 )、( 2 )所示之擴 散的/ t法則。 [數1] X二涵 —式(1) D-Z)〇 exp(-0/^7) _ -μ Χ(μπι):擴散距離(化合物厚度) T(K):焊錫熔化溫度 D(pm2/s):外觀擴散常數 D〇(gm2/s):頻度因子 t(s):時間(融點以上之熔化時間)Q(eV):活化能 k(eV/K):波耳茲曼常數 (Boltzmann’s constant) -5、 ( = 8.62X10 )
Γ-217«(rmax-217)Sin (〇 … -式⑶
Tmax :最高溫度(°c ) ,tm : 217°c以上熔化時間(S) -12- (8)1222197 义-=Σ 2A) exp〔·^^
Att = 2D0 exp^ - Q ^:(250+ 273)' ^250 —式(4) t2 5(): 2 5 0 t: —定溫度曲線換算熔化時間(s) 式(2 )中,藉由求取擴散常數的頻度因子D〇和活化 能Q,熔化溫度和熔化時間如決定,可單一決定化合物厚 度。因此,首先進行焊錫和連接銲墊之界面的剖面觀察, 求得形成在界面之化合物厚度,由此求得之化合物厚度進 行阿倫尼烏斯(Arrhenius,Svante August)繪圖,求得式 (2 )之頻道因子D〇和活化能Q。而且,如第1 1圖,對 於具有1個峰値之任意的曲線,使焊錫之融點以上的部份 近似正弦半波,在將其分割之各微小區間中,由所獲得之 頻道因子D〇和活化能Q計算化合物厚度,藉由將其全部 加總,可以求得全部熱負載之化合物厚度。設給予成長此 厚度之化合物的熱負載之一定溫度的加熱曲線與具有1個 此峰値之曲線等效,由所獲得之一定溫度的加熱曲線條件 下之適當迴焊範圍以求得具有1個峰値之曲線的適當迴焊 範圍。式(3 )爲顯示曲線之近似式,式(4 )爲表示轉換 爲2 5 (TC —定溫度曲線之轉換式。 由上式,可以獲得具有1個如第1 〇圖之峰値的曲線 條件的不降低連接界面強度之適當迴焊範圍。在此獲得之 適當迴焊範圍進行焊錫連接,能夠獲得在量產時連接界面 強度不會降低之連接。 -13- (9) (9)1222197 (實施例3 ) 首先,對於具有Cu/電解Ni電鍍/Au之包覆材料構造 的電極銲墊之基板,在銲墊上熔化連接Sn3Ag0.5Cii之焊 錫球,形成焊錫凸塊。此時的連接條件爲如第9圖所示之 一定溫度曲線,熔化溫度爲2 3 0 °C、2 4 0 °C、2 5 0 °C,時間 爲 5s、10s、30s、60s、120s、180s,分別改變其熔化時 間以形成凸塊。另外,由此剪斷試驗結果,求得此次評估 的包覆材料的適當迴焊範圍。第1 3圖顯示適當迴焊範圍 。判定連接界面強度降低的基準爲:以破壞模式爲之,將 全部的凸塊都在焊錫內破壞時當成沒有強度降低,在焊錫 和包覆材料的界面即使有1個凸塊破壞時則判斷爲強度降 低。剪斷凸塊數分別設爲1 0個凸塊。 接著,在個別形成的凸塊中,對於熔化溫度23 0°C、 240°C、25(TC,熔化時間180s的條件之凸塊,以SEM進 行剖面觀察。第1 4圖顯示觀察照片的例子。由此照片求 得化合物厚度,將熔化溫度的倒數和外觀擴散常數的關係 當成阿倫尼烏斯圖顯示。第1 5圖顯示阿倫尼烏斯圖。以 此阿倫尼烏斯圖爲基礎,由式(1 ) 、( 2 )之擴散的/" t 法則以求得頻度因子D〇和活化能Q。頻度因子D〇爲 D〇 = 5.56X106(mm2/s),活化能 Q 爲 Q = 〇.93(eV)。
接著’以所獲得之頻度因子D〇、活化能Q之値爲基 礎,將第13圖的適當迴焊範圍轉換爲具有1個峰値之溫 度曲線的適當迴焊範圍。對於在被認爲適於當成 Sn3 Ag〇. 5Cu之焊錫球的連接條件之最高溫度225〜260°C -14- (10) (10)1222197 的範圍中,以1°C爲1刻度、熔化時間10〜100s之範圍 中,以1 〇°C爲1刻度的具有1個峰値的溫度曲線全部, 如第1 1圖所示,將近似正弦半波後的曲線分割爲微小區 間,以所獲得之頻度因子Do和活化能Q之値爲基礎,利 用式(1 ) 、( 2 ),計算各微小區間的化合物厚度,然後 求得全部熱負載的化合物厚度,予以資料庫化。在第13 圖之適當迴焊範圍中,在25 0°C時60s下,連接界面強度 降低,所以認爲此條件爲適當、不適當之|界,由此資料 庫求得相當於在此條件連接時的化合物厚度之具有1個峰 値溫度曲線的範圍。第1 6圖顯示具有1個峰値溫度曲線 的適當迴焊範圍。也同時顯示爲了簡化而將凸塊形成條件 、基板的迴焊條件、重工時之熱負載條件都設爲相同條件 而加以計算且重工次數也加以考慮之適當迴焊範圍。 接著,進行第1 6圖所獲得之具有1個峰値的溫度曲 線的適當迴焊範圍的驗證。對於具有Cu/電解Ni電鍍/Au 之包覆材料構造的電極銲墊之基板,在銲墊上熔化連接 Sn3 AgO. 5 Cu之焊錫球,形成焊錫凸塊。熔化條件係使用 ••最高溫度爲24(TC,在Sn3Ag0.5Cu之融點217°C以上 的熔化時間爲20s、35s、50s、80s之具有1個峰値的溫 度曲線,對於個別之樣本給予1次〜4次之熱負載。之後 ,對於形成之焊錫凸塊進行剪斷試驗。以217°C以上之熔 化時間熔化時間20s連接,迴焊次數爲1次至4次之樣本 全部,其結果在焊錫內破壞,在熔化時間3 5 s、4次迴焊 品,在熔化時間50s、3次及4次迴焊品,在熔化時間80s -15- (11) (11)1222197 、2次、3次、4次迴焊品中,都產生破壞。由以上,可 以驗證第1 6圖之具有1個峰値的溫度曲線之適當迴焊範 圍爲正確。 (實施例4 ) 接著,對於具有Cu/電解Ni電鍍/Au之包覆材料構造 的電極銲墊之基板,在銲墊上熔化連接Sn3Ag0.5Cu之焊 錫球,形成焊錫凸塊。此時的連接條件爲如第9圖所示之 一定溫度曲線,熔化溫度爲230°C、240°C、250°C,時間 爲 5s、10s、30s、60s、120s、180s,分別改變其熔化時 間以形成凸塊。之後,對於形成之凸塊,進行剪斷試驗。 第17圖顯示剪斷試驗結果。另外,由此剪斷強度結果以 求得此次評估之包覆材料的適當迴焊範圍。第1 8圖顯示 適當迴焊範圍。判定連接界面強度降低的基準爲:以破壞 模式爲之,將全部的凸塊都在焊錫內破壞時當成沒有強度 降低,在焊鍚和包覆材料的界面即使有1個凸塊破壞時則 判斷爲強度降低。剪斷凸塊數分別設爲1 〇個凸塊。 接著,以熔化溫度23 0°C、250°C、2 70 °C,熔化時間 180s的條件形成凸塊,以SEM進行剖面觀察。第19圖顯 示觀察照片的例子。由此照片求得化合物厚度,將熔化溫 度的倒數和外觀擴散常數的關係當成阿倫尼烏斯圖顯示。 第2 0圖顯示阿倫尼烏斯圖。以此阿倫尼烏斯圖爲基礎, 由式(1 ) 、( 2 )之擴散的,t法則以求得頻度因子D0和 活化能Q。頻度因子D。爲D〇 = 5.77Xl〇 (mm2/s),活化能 -16- (12) (12)1222197 Q 爲 Q = 0.3 l(eV)。 接著,以所獲得之頻度因子D〇、活化能Q之値爲基 礎,將第1 8圖的適當迴焊範圍轉換爲具有1個峰値之溫 度曲線的適當迴焊範圍。對於在被認爲適於當成 Sn3Ag0.5Cu之焊錫球的連接條件之最高溫度2 2 5〜2 6 0 °C 的範圍中,以1°C爲1刻度、熔化時間10〜100s之範圍 中,以10 °C爲1刻度的具有1個峰値的溫度曲線全部, 如第11圖所示,將近似正弦半波後的曲線分割爲微小區 間,以所獲得之頻度因子Do和活化能Q之値爲基礎,利 用式(1 ) 、( 2 ),計算各微小區間的化合物厚度,然後 求得全部熱負載的化合物厚度,予以資料庫化。在第18 圖之適當迴焊範圍中,在250 °C時60s下,連接界面強度 降低,所以認爲此條件爲適當、不適當之邊界,由此資料 庫求得相當於在此條件連接時的化合物厚度之具有1個峰 値溫度曲線的範圍。第2 1圖顯示具有1個峰値溫度曲線 的適當迴焊範圍。也同時顯示爲了簡化而將凸塊形成條件 、基板的迴焊條件、重工時之熱負載條件都設爲相同條件 而加以計算且重工次數也加以考慮之適當迴焊範圍。 接著,進行第2 1圖所獲得之具有1個峰値的溫度曲 線的適當迴焊範圍的驗證。對於具有Cu/電解Ni電鍍/Au 之包覆材料構造的電極銲墊之基板,在銲墊上熔化連接 Sn3 AgO. 5 Cu之焊錫球,形成焊錫凸塊。熔化條件係使用 ••最高溫度爲240°C,在Sn3Ag0.5Cu之融點217°C以上 的熔化時間爲15s、25s、35s、60s之具有1個峰値的溫 -17- (13) (13)1222197 度曲線,對於個別之樣本給予1次〜4次之熱負載。之後 ,對於形成之焊錫凸塊進行剪斷試驗。剪斷凸塊數分別設 爲10個凸塊。以21 以上之熔化時間熔化時間15s連 接,迴焊次數爲1次至4次之樣本全部,其結果在焊錫內 破壞,在熔化時間2 5 s、4次迴焊品,在熔化時間3 5 s、3 次及4次迴焊品,在熔化時間60s、2次、3次、4次迴焊 品中,都產生破壞。由以上,可以驗證第2 1圖之具有1 個峰値的溫度曲線之適當迴焊範圍爲正確。 對於伴隨以往完全未被考慮之熱容量差和重工等所引 起的熱負載增加所導致的連接界面強度降低的問題,藉由 利用本發明,在如第1 6圖所示之具有1個峰値的任意溫 度曲線中,可以求得不會有連接界面強度降低的良好連接 之適當迴焊範圍。 如以上所述,如依據本申請案所記載之發明,可以抑 制電子裝置的連接界面強度的降低。 產業上的利用可能性 另外,本發明爲關於半導體裝置的發明,有利用在產 業上之可能性。 【圖式簡單說明】 第1圖係顯示利用焊錫凸塊連接之電子零件連接在一 般基板之連接條件圖。 第2圖係顯示利用焊錫凸塊連接之電子零件連接在一 般基板之連接條件的220 °C以上的部份圖。 -18- (14) (14)1222197 第3圖係顯示在實施例1中,3個封裝零件連接在測 試基板的連接條件圖。 第4圖係對於實施例2中,在上述封裝零件形成凸塊 ,藉由焊錫膏連接在基板之樣本,所做的衝擊彎曲試驗評 估結果圖。 第5圖係第2實施例中,由上述衝擊彎曲試驗評估結 果所求得之最高溫度250°C時的適當連接條件。 φ 第6圖係顯示在實施例2中,由上述衝擊彎曲試驗評 估結果所求得之最高溫度2 5 0 °C之適當連接條件的2 2 0 °C 以上部份之圖。 第7圖係顯示電子零件和電子電路基板的接合流程圖 〇 第8圖係顯示求取連接界面強度不會降低的適當迴焊 範圍之方法的流程圖。 第9圖係顯示使熔化溫度爲一定之溫度曲線例(250 °C 一定)圖。 _ 第1 0圖係顯示具有1個峰値的溫度曲線例圖。 第Π圖爲在具有1個峰値的曲線中,以正弦半波近 似焊錫融點以上之部份,加以分割爲微小區間之例。 第12圖係顯示在實施例3中,由一定溫度曲線所連 接的焊錫凸塊的剪斷試驗評估結果圖。 第1 3圖係顯示在實施例3中,由對於由一定溫度曲 線所連接的焊錫凸塊進行剪斷試驗評估所求得之適當迴焊 範圍圖。 -19- (15) (15)1222197 第1 4圖係顯示在實施例3中,對於於由一定溫度曲 線所連接的焊錫凸塊,以SEM進行剖面觀察之例(250°C 、1 8 0 s熔化)圖。 第1 5圖係顯示在實施例3中,由一定溫度曲線連接 的焊錫凸塊之剖面SEM照片以求得化合物厚度,顯示出 熔化溫度之倒數和化合物厚度之平方關係的阿倫尼烏斯( Arrhenius, Svante August )圖。 第16圖係顯示在實施例3中,對於具有1個峰値之 曲線條件的連接溫度適當迴焊範圍圖° 第17圖係顯示在實施例4中,由一定溫度曲線所連 接的焊錫凸塊的剪斷試驗評估結果圖。 第1 8圖係顯示在實施例4中,對於由一定溫度曲線 所連接之焊錫凸塊,進行剪斷試驗評估所求得之適當迴焊 範圍圖。 第1 9圖係顯示在實施例4中,對於由一定溫度曲線 所連接之焊錫凸塊,以SEM進行剖面觀察之例(25 0°C、 180s熔化)圖。 第20圖係顯示在實施例4中,由一定溫度曲線所連 接之焊錫凸塊的剖面SEM照片求得化合物厚度,顯示出 熔化溫度之倒數和化合物厚度之平方關係的阿倫尼烏斯圖 〇 第21圖係顯示在實施例4中,對於具有1個峰値之 曲線條件的連接溫度適當迴焊範圍圖。 -20- (16)1222197 【主 要元件對照表】 9 電子零件 10 電極 11 金屬層 12 銲墊 14 電子電路基板
-21 -
Claims (1)
- (1) (1)1222197 拾、申請專利範圍 i· 一種電子裝置之製造方法,是針對具有形成有凸 塊之半導體裝置,該凸塊是由形成在以Ni (鎳)和p (磷) 爲主成分之金屬層上的Sn-Ag-Cu系(錫-銀—銅)的無 鉛焊錫所形成;和具備電極之電子電路基板的電子裝置之 製造方法,其特徵爲: 在220°C以上、250 °C以下之溫度區間加熱上述無鉛 焊錫4 0秒以上、8 0秒以下。 2 ·如申請專利範圍第1項記載之電子裝置之製造方 法,其中,上述加熱溫度在220 °C以上的平均溫昇速度或 者平均降溫速度爲0.7°C /秒以上、4.0°C /秒以下。 3 ·如申請專利範圍第2項記載之電子裝置之製造方 法中,其中,在230 °C /秒以上之溫度加熱上述焊錫35 秒以上。 4· 一種半導體裝置,是針對具有以形成在以Ni (鎳 )和P(磷)爲主成分之金屬層上的Sn-Ag-Cu系(錫一銀 -銅)的無鉛焊錫所構成的凸塊之半導體裝置,其特徵爲 顯示上述無鉛焊錫可以在220 °C以上、25 (TC以下之 溫度區間加熱40秒以上、80秒以下之資訊被公開。 5· —種連接條件之算出方法,其特徵爲: 變電子零件的凸塊和電子電路基板的電極之連接條件 ,以進行焊錫連接,分別進行連接強度評估試驗,以求得 在電極和焊錫界面沒有產生破壞之連接條件。 -22- (2) (2)1222197 6 ·如申請專利範圍第5項記載之連接條件之算出方 法’其中,以上述熱負載爲基準,將上述連接條件轉換爲 具有相同熱負載之任意的連接條件以求得一般化之連接條 件。 7 ·如申請專利範圍第6項記載之連接條件之算出方 法’其中,以上述熱負載爲基準,將該良好之連接條件轉 換爲具有同樣熱負載而有1個溫度峰値之任意的連接條件 以求得一般化之連接條件。 8 ·如申請專利範圍第7項記載之連接條件之算出方 法,其中,以由上述熱負載所單一決定的連接界面的化合 物厚度爲基準,將該連接條件轉換爲具有同樣的化合物厚 度而有1個溫度峰値之任意的連接條件以算出一般化之連 接條件。-23-
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US6917113B2 (en) * | 2003-04-24 | 2005-07-12 | International Business Machines Corporatiion | Lead-free alloys for column/ball grid arrays, organic interposers and passive component assembly |
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2002
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Also Published As
Publication number | Publication date |
---|---|
KR100560029B1 (ko) | 2006-03-13 |
KR20030071511A (ko) | 2003-09-03 |
CN1442892A (zh) | 2003-09-17 |
JP4136641B2 (ja) | 2008-08-20 |
TW200308070A (en) | 2003-12-16 |
JP2003324124A (ja) | 2003-11-14 |
US7217645B2 (en) | 2007-05-15 |
US20030230806A1 (en) | 2003-12-18 |
CN1307702C (zh) | 2007-03-28 |
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