TWI221968B - System having an apparatus for controlling use of a communication bus and method for controlling use of a communication bus in a system - Google Patents

System having an apparatus for controlling use of a communication bus and method for controlling use of a communication bus in a system Download PDF

Info

Publication number
TWI221968B
TWI221968B TW091111284A TW91111284A TWI221968B TW I221968 B TWI221968 B TW I221968B TW 091111284 A TW091111284 A TW 091111284A TW 91111284 A TW91111284 A TW 91111284A TW I221968 B TWI221968 B TW I221968B
Authority
TW
Taiwan
Prior art keywords
bus
communication bus
control
data segment
transmission
Prior art date
Application number
TW091111284A
Other languages
English (en)
Chinese (zh)
Inventor
William C Moyer
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TWI221968B publication Critical patent/TWI221968B/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW091111284A 2001-06-23 2002-05-28 System having an apparatus for controlling use of a communication bus and method for controlling use of a communication bus in a system TWI221968B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/888,278 US6775727B2 (en) 2001-06-23 2001-06-23 System and method for controlling bus arbitration during cache memory burst cycles

Publications (1)

Publication Number Publication Date
TWI221968B true TWI221968B (en) 2004-10-11

Family

ID=25392904

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091111284A TWI221968B (en) 2001-06-23 2002-05-28 System having an apparatus for controlling use of a communication bus and method for controlling use of a communication bus in a system

Country Status (8)

Country Link
US (1) US6775727B2 (enExample)
JP (1) JP4139771B2 (enExample)
KR (1) KR100899951B1 (enExample)
CN (1) CN1230758C (enExample)
DE (1) DE10296959T5 (enExample)
GB (1) GB2390200B (enExample)
TW (1) TWI221968B (enExample)
WO (1) WO2003001388A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI506536B (zh) * 2013-01-10 2015-11-01 Accton Technology Corp 執行裝置及其堆疊方法與堆疊系統
CN107480081A (zh) * 2016-06-07 2017-12-15 旺宏电子股份有限公司 具有可中断指令序列的存储器及其操作方法

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7107365B1 (en) * 2002-06-25 2006-09-12 Cypress Semiconductor Corp. Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus
JP2004062319A (ja) * 2002-07-25 2004-02-26 Renesas Technology Corp データ処理装置
DE10300342A1 (de) 2003-01-09 2004-07-22 Wilhelm Karmann Gmbh Cabriolet-Fahrzeug
US6971033B2 (en) * 2003-01-10 2005-11-29 Broadcom Corporation Method and apparatus for improving bus master performance
CN1296844C (zh) * 2003-06-20 2007-01-24 上海奇码数字信息有限公司 数据传送方法和数据传送系统
GB0317699D0 (en) * 2003-07-29 2003-09-03 Ibm A copy engine and a method for data movement
US7013357B2 (en) * 2003-09-12 2006-03-14 Freescale Semiconductor, Inc. Arbiter having programmable arbitration points for undefined length burst accesses and method
US7334059B2 (en) * 2004-03-03 2008-02-19 Freescale Semiconductor, Inc. Multiple burst protocol device controller
DE602004019990D1 (de) * 2004-08-30 2009-04-23 Magima Digital Information Co Verfahren und system zum datentransfer
CN1307571C (zh) * 2004-11-26 2007-03-28 上海广电(集团)有限公司中央研究院 一种低速总线结构及其数据传输方法
US7617338B2 (en) * 2005-02-03 2009-11-10 International Business Machines Corporation Memory with combined line and word access
KR100633773B1 (ko) * 2005-07-01 2006-10-13 삼성전자주식회사 버스 시스템 및 버스 중재 방법
US8813052B2 (en) * 2005-12-07 2014-08-19 Microsoft Corporation Cache metadata for implementing bounded transactional memory
US8225297B2 (en) 2005-12-07 2012-07-17 Microsoft Corporation Cache metadata identifiers for isolation and sharing
US8001538B2 (en) 2005-12-07 2011-08-16 Microsoft Corporation Software accessible cache metadata
US7865897B2 (en) 2006-02-03 2011-01-04 Freescale Semiconductor, Inc. Selective transaction request processing at an interconnect during a lockout
US8898652B2 (en) * 2006-03-23 2014-11-25 Microsoft Corporation Cache metadata for accelerating software transactional memory
US8266387B2 (en) * 2007-06-27 2012-09-11 Microsoft Corporation Leveraging transactional memory hardware to accelerate virtualization emulation
US9043553B2 (en) * 2007-06-27 2015-05-26 Microsoft Technology Licensing, Llc Leveraging transactional memory hardware to accelerate virtualization and emulation
US8176253B2 (en) * 2007-06-27 2012-05-08 Microsoft Corporation Leveraging transactional memory hardware to accelerate virtualization and emulation
JP2009116702A (ja) * 2007-11-07 2009-05-28 Toshiba Corp 半導体集積回路
US8478920B2 (en) * 2010-06-24 2013-07-02 International Business Machines Corporation Controlling data stream interruptions on a shared interface
US20120089759A1 (en) * 2010-10-08 2012-04-12 Qualcomm Incorporated Arbitrating Stream Transactions Based on Information Related to the Stream Transaction(s)
CN102724389B (zh) * 2011-11-15 2017-06-13 新奥特(北京)视频技术有限公司 一种同平台非编系统间的监视器输出方法
FR2982961B1 (fr) * 2011-11-22 2014-09-05 Schneider Electric Usa Inc Arbitrage de dispositif de commande prioritaire
CN103257942B (zh) * 2013-03-27 2015-12-02 青岛中星微电子有限公司 一种片上系统共享总线请求处理的方法及装置
US9606853B2 (en) * 2014-03-28 2017-03-28 Intel Corporation Protecting a memory device from becoming unusable
US10475492B1 (en) 2018-07-27 2019-11-12 Macronix International Co., Ltd. Circuit and method for read latency control

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4710916A (en) * 1985-08-02 1987-12-01 Gte Laboratories Incorporated Switching apparatus for burst-switching communications system
DE3782335T2 (de) * 1987-04-22 1993-05-06 Ibm Speichersteuersystem.
US5388228A (en) 1987-09-30 1995-02-07 International Business Machines Corp. Computer system having dynamically programmable linear/fairness priority arbitration scheme
US4987529A (en) 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US5072365A (en) 1989-12-27 1991-12-10 Motorola, Inc. Direct memory access controller using prioritized interrupts for varying bus mastership
KR920004993A (ko) * 1990-08-28 1992-03-28 한태희 버스 중재 로직을 가진 컴퓨터 시스템
EP0559408B1 (en) 1992-03-04 1998-08-26 Motorola, Inc. A method and apparatus for performing bus arbitration using an arbiter in a data processing system
US5467295A (en) 1992-04-30 1995-11-14 Intel Corporation Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit
US5535333A (en) * 1993-03-30 1996-07-09 International Business Machines Corporation Adapter for interleaving second data with first data already transferred between first device and second device without having to arbitrate for ownership of communications channel
JPH0830549A (ja) * 1994-07-18 1996-02-02 Fuji Xerox Co Ltd バス制御装置
US5889973A (en) 1995-03-31 1999-03-30 Motorola, Inc. Method and apparatus for selectively controlling interrupt latency in a data processing system
US5758105A (en) * 1995-12-04 1998-05-26 International Business Machines Corporation Method and apparatus for bus arbitration between isochronous and non-isochronous devices
US5822758A (en) * 1996-09-09 1998-10-13 International Business Machines Corporation Method and system for high performance dynamic and user programmable cache arbitration
US5894562A (en) 1996-10-28 1999-04-13 Motorola, Inc. Method and apparatus for controlling bus arbitration in a data processing system
US5944800A (en) * 1997-09-12 1999-08-31 Infineon Technologies Corporation Direct memory access unit having a definable plurality of transfer channels
US6088751A (en) * 1998-02-12 2000-07-11 Vlsi Technology, Inc. Highly configurable bus priority arbitration system
US6330646B1 (en) * 1999-01-08 2001-12-11 Intel Corporation Arbitration mechanism for a computer system having a unified memory architecture
US6687821B1 (en) * 2000-03-31 2004-02-03 Intel Corporation System for dynamically configuring system logic device coupled to the microprocessor to optimize application performance by reading from selection table located in non-volatile memory
US6513089B1 (en) * 2000-05-18 2003-01-28 International Business Machines Corporation Dual burst latency timers for overlapped read and write data transfers
US6772254B2 (en) * 2000-06-21 2004-08-03 International Business Machines Corporation Multi-master computer system with overlapped read and write operations and scalable address pipelining
US6671284B1 (en) * 2000-08-04 2003-12-30 Intellon Corporation Frame control for efficient media access
US6564304B1 (en) * 2000-09-01 2003-05-13 Ati Technologies Inc. Memory processing system and method for accessing memory including reordering memory requests to reduce mode switching

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI506536B (zh) * 2013-01-10 2015-11-01 Accton Technology Corp 執行裝置及其堆疊方法與堆疊系統
US9367506B2 (en) 2013-01-10 2016-06-14 Accton Technology Corporation Executive device and control method and electronic system thereof
CN107480081A (zh) * 2016-06-07 2017-12-15 旺宏电子股份有限公司 具有可中断指令序列的存储器及其操作方法
TWI639086B (zh) 2016-06-07 2018-10-21 旺宏電子股份有限公司 具有可中斷指令序列的記憶體及其操作方法
US10289596B2 (en) 2016-06-07 2019-05-14 Macronix International Co., Ltd. Memory and method for operating a memory with interruptible command sequence
CN107480081B (zh) * 2016-06-07 2020-05-12 旺宏电子股份有限公司 具有可中断指令序列的存储器及其操作方法

Also Published As

Publication number Publication date
JP4139771B2 (ja) 2008-08-27
CN1507592A (zh) 2004-06-23
US6775727B2 (en) 2004-08-10
GB2390200A (en) 2003-12-31
WO2003001388A1 (en) 2003-01-03
KR20040012964A (ko) 2004-02-11
US20020199052A1 (en) 2002-12-26
KR100899951B1 (ko) 2009-05-28
CN1230758C (zh) 2005-12-07
DE10296959T5 (de) 2004-08-05
GB0324805D0 (en) 2003-11-26
JP2004531830A (ja) 2004-10-14
GB2390200B (en) 2005-05-18

Similar Documents

Publication Publication Date Title
TWI221968B (en) System having an apparatus for controlling use of a communication bus and method for controlling use of a communication bus in a system
US11138143B2 (en) Techniques for command validation for access to a storage device by a remote client
US20190155760A1 (en) NVME Data Processing Method and NVME Device
KR101881089B1 (ko) 스트림 트랜잭션 정보에 기초하여 페이지 관리 정책들을 적용하기 위한 메모리 제어기들, 시스템들 및 방법들
KR20210038313A (ko) 레이턴시에 중점을 둔 판독 동작과 대역폭에 중점을 둔 판독 동작 사이의 동적 변경
KR19990067846A (ko) 버스 시스템 동작 방법 및 장치
TW200931250A (en) Memory controller for performing memory block initialization and copy
JP4250207B2 (ja) 対称多重処理システム、そのための割込制御ユニット、および対称多重処理システム内でプロセッサ割込信号を開始するための方法
JPH09179816A (ja) データ処理システム(非対称バス・アービトレーション・プロトコル)
WO2002088970A1 (en) Crossbar multipath resource controller system and method
JPH06231074A (ja) システムバスの多重アクセス方式
KR900001120B1 (ko) 우선도가 낮은 유니트를 우선도가 높은 위치에 위치시키기 위한 분배된 우선도 회로망 로직을 가진 데이타 처리 시스템
EP1811393A1 (en) Method and system for data transfer
US8943238B2 (en) Operations using direct memory access
US6532507B1 (en) Digital signal processor and method for prioritized access by multiple core processors to shared device
KR20070056724A (ko) 클락 신호의 출력을 제어할 수 있는 컨트롤러와 그 방법,및 상기 컨트롤러를 구비하는 시스템
JP2008009817A (ja) 半導体装置及びデータ転送方法
CN112445737B (zh) 通过非透明桥设备传输信息的系统、方法和该设备
TWI330811B (en) Apparatus and method for sparse line write transactions
CN104753830A (zh) 基带芯片及其数据处理方法
JPH04134551A (ja) 複数のデータ処理エージェントの間でデータを転送するバスにおいて、第1のエージェントがサービスの必要を第2のエージェントへ知らせる方法
KR100487218B1 (ko) 칩 내장형 버스를 인터페이스하기 위한 장치 및 방법
EP1761855B1 (en) Data processing system and method for interconnect arbitration
CN101194235A (zh) 存储器控制装置及存储器控制方法
JP2000250850A (ja) バス制御装置、マスタ装置及びスレーブ装置並びにバス制御方法

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent