GB2390200B - System and method for controlling bus arbitration during cache memory burst cycles - Google Patents

System and method for controlling bus arbitration during cache memory burst cycles

Info

Publication number
GB2390200B
GB2390200B GB0324805A GB0324805A GB2390200B GB 2390200 B GB2390200 B GB 2390200B GB 0324805 A GB0324805 A GB 0324805A GB 0324805 A GB0324805 A GB 0324805A GB 2390200 B GB2390200 B GB 2390200B
Authority
GB
United Kingdom
Prior art keywords
cache memory
bus arbitration
controlling bus
burst cycles
during cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0324805A
Other languages
English (en)
Other versions
GB2390200A (en
GB0324805D0 (en
Inventor
William C Moyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Motorola Inc filed Critical Freescale Semiconductor Inc
Publication of GB0324805D0 publication Critical patent/GB0324805D0/en
Publication of GB2390200A publication Critical patent/GB2390200A/en
Application granted granted Critical
Publication of GB2390200B publication Critical patent/GB2390200B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB0324805A 2001-06-23 2002-05-15 System and method for controlling bus arbitration during cache memory burst cycles Expired - Fee Related GB2390200B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/888,278 US6775727B2 (en) 2001-06-23 2001-06-23 System and method for controlling bus arbitration during cache memory burst cycles
PCT/US2002/018358 WO2003001388A1 (en) 2001-06-23 2002-05-15 System and method for controlling bus arbitration during cache memory burst cycles

Publications (3)

Publication Number Publication Date
GB0324805D0 GB0324805D0 (en) 2003-11-26
GB2390200A GB2390200A (en) 2003-12-31
GB2390200B true GB2390200B (en) 2005-05-18

Family

ID=25392904

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0324805A Expired - Fee Related GB2390200B (en) 2001-06-23 2002-05-15 System and method for controlling bus arbitration during cache memory burst cycles

Country Status (8)

Country Link
US (1) US6775727B2 (enExample)
JP (1) JP4139771B2 (enExample)
KR (1) KR100899951B1 (enExample)
CN (1) CN1230758C (enExample)
DE (1) DE10296959T5 (enExample)
GB (1) GB2390200B (enExample)
TW (1) TWI221968B (enExample)
WO (1) WO2003001388A1 (enExample)

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US6971033B2 (en) * 2003-01-10 2005-11-29 Broadcom Corporation Method and apparatus for improving bus master performance
CN1296844C (zh) * 2003-06-20 2007-01-24 上海奇码数字信息有限公司 数据传送方法和数据传送系统
GB0317699D0 (en) * 2003-07-29 2003-09-03 Ibm A copy engine and a method for data movement
US7013357B2 (en) * 2003-09-12 2006-03-14 Freescale Semiconductor, Inc. Arbiter having programmable arbitration points for undefined length burst accesses and method
US7334059B2 (en) * 2004-03-03 2008-02-19 Freescale Semiconductor, Inc. Multiple burst protocol device controller
DE602004019990D1 (de) * 2004-08-30 2009-04-23 Magima Digital Information Co Verfahren und system zum datentransfer
CN1307571C (zh) * 2004-11-26 2007-03-28 上海广电（集团）有限公司中央研究院 一种低速总线结构及其数据传输方法
US7617338B2 (en) * 2005-02-03 2009-11-10 International Business Machines Corporation Memory with combined line and word access
KR100633773B1 (ko) * 2005-07-01 2006-10-13 삼성전자주식회사 버스 시스템 및 버스 중재 방법
US8001538B2 (en) 2005-12-07 2011-08-16 Microsoft Corporation Software accessible cache metadata
US8225297B2 (en) 2005-12-07 2012-07-17 Microsoft Corporation Cache metadata identifiers for isolation and sharing
US8813052B2 (en) * 2005-12-07 2014-08-19 Microsoft Corporation Cache metadata for implementing bounded transactional memory
US7865897B2 (en) 2006-02-03 2011-01-04 Freescale Semiconductor, Inc. Selective transaction request processing at an interconnect during a lockout
US8898652B2 (en) * 2006-03-23 2014-11-25 Microsoft Corporation Cache metadata for accelerating software transactional memory
US8266387B2 (en) * 2007-06-27 2012-09-11 Microsoft Corporation Leveraging transactional memory hardware to accelerate virtualization emulation
US8176253B2 (en) * 2007-06-27 2012-05-08 Microsoft Corporation Leveraging transactional memory hardware to accelerate virtualization and emulation
US9043553B2 (en) * 2007-06-27 2015-05-26 Microsoft Technology Licensing, Llc Leveraging transactional memory hardware to accelerate virtualization and emulation
JP2009116702A (ja) * 2007-11-07 2009-05-28 Toshiba Corp 半導体集積回路
US8478920B2 (en) * 2010-06-24 2013-07-02 International Business Machines Corporation Controlling data stream interruptions on a shared interface
US20120089759A1 (en) * 2010-10-08 2012-04-12 Qualcomm Incorporated Arbitrating Stream Transactions Based on Information Related to the Stream Transaction(s)
CN102724389B (zh) * 2011-11-15 2017-06-13 新奥特（北京）视频技术有限公司 一种同平台非编系统间的监视器输出方法
FR2982961B1 (fr) * 2011-11-22 2014-09-05 Schneider Electric Usa Inc Arbitrage de dispositif de commande prioritaire
TWI506536B (zh) 2013-01-10 2015-11-01 Accton Technology Corp 執行裝置及其堆疊方法與堆疊系統
CN103257942B (zh) * 2013-03-27 2015-12-02 青岛中星微电子有限公司 一种片上系统共享总线请求处理的方法及装置
US9606853B2 (en) * 2014-03-28 2017-03-28 Intel Corporation Protecting a memory device from becoming unusable
US10289596B2 (en) * 2016-06-07 2019-05-14 Macronix International Co., Ltd. Memory and method for operating a memory with interruptible command sequence
US10475492B1 (en) 2018-07-27 2019-11-12 Macronix International Co., Ltd. Circuit and method for read latency control

Citations (3)

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US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US5506972A (en) * 1987-09-30 1996-04-09 International Business Machines Corporation Computer system having dynamically programmable linear/fairness priority arbitration scheme
US5740376A (en) * 1992-04-30 1998-04-14 Intel Corporation Signaling protocol for a peripheral component interconnect

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US5072365A (en) 1989-12-27 1991-12-10 Motorola, Inc. Direct memory access controller using prioritized interrupts for varying bus mastership
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DE69320508T2 (de) 1992-03-04 1999-03-04 Motorola, Inc., Schaumburg, Ill. Verfahren und Gerät zur Busarbitrierungsdurchführung mit einem Arbiter in einem Datenverarbeitungssystem
US5535333A (en) * 1993-03-30 1996-07-09 International Business Machines Corporation Adapter for interleaving second data with first data already transferred between first device and second device without having to arbitrate for ownership of communications channel
JPH0830549A (ja) * 1994-07-18 1996-02-02 Fuji Xerox Co Ltd バス制御装置
US5889973A (en) 1995-03-31 1999-03-30 Motorola, Inc. Method and apparatus for selectively controlling interrupt latency in a data processing system
US5758105A (en) * 1995-12-04 1998-05-26 International Business Machines Corporation Method and apparatus for bus arbitration between isochronous and non-isochronous devices
US5822758A (en) * 1996-09-09 1998-10-13 International Business Machines Corporation Method and system for high performance dynamic and user programmable cache arbitration
US5894562A (en) 1996-10-28 1999-04-13 Motorola, Inc. Method and apparatus for controlling bus arbitration in a data processing system
US5944800A (en) * 1997-09-12 1999-08-31 Infineon Technologies Corporation Direct memory access unit having a definable plurality of transfer channels
US6088751A (en) * 1998-02-12 2000-07-11 Vlsi Technology, Inc. Highly configurable bus priority arbitration system
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US6687821B1 (en) * 2000-03-31 2004-02-03 Intel Corporation System for dynamically configuring system logic device coupled to the microprocessor to optimize application performance by reading from selection table located in non-volatile memory
US6513089B1 (en) * 2000-05-18 2003-01-28 International Business Machines Corporation Dual burst latency timers for overlapped read and write data transfers
US6772254B2 (en) * 2000-06-21 2004-08-03 International Business Machines Corporation Multi-master computer system with overlapped read and write operations and scalable address pipelining
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US5506972A (en) * 1987-09-30 1996-04-09 International Business Machines Corporation Computer system having dynamically programmable linear/fairness priority arbitration scheme
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US5740376A (en) * 1992-04-30 1998-04-14 Intel Corporation Signaling protocol for a peripheral component interconnect

Also Published As

Publication number Publication date
CN1230758C (zh) 2005-12-07
US20020199052A1 (en) 2002-12-26
GB2390200A (en) 2003-12-31
CN1507592A (zh) 2004-06-23
JP4139771B2 (ja) 2008-08-27
TWI221968B (en) 2004-10-11
DE10296959T5 (de) 2004-08-05
JP2004531830A (ja) 2004-10-14
WO2003001388A1 (en) 2003-01-03
US6775727B2 (en) 2004-08-10
KR20040012964A (ko) 2004-02-11
GB0324805D0 (en) 2003-11-26
KR100899951B1 (ko) 2009-05-28

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20080515