TW561553B - Method and structure for oxide/silicon nitride interface substructure improvements - Google Patents
Method and structure for oxide/silicon nitride interface substructure improvements Download PDFInfo
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- TW561553B TW561553B TW091122325A TW91122325A TW561553B TW 561553 B TW561553 B TW 561553B TW 091122325 A TW091122325 A TW 091122325A TW 91122325 A TW91122325 A TW 91122325A TW 561553 B TW561553 B TW 561553B
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 229910052581 Si3N4 Inorganic materials 0.000 title claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 66
- 230000007704 transition Effects 0.000 claims abstract description 43
- 150000004767 nitrides Chemical class 0.000 claims abstract description 39
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 30
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000001301 oxygen Substances 0.000 claims abstract description 13
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 13
- 238000012545 processing Methods 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000005121 nitriding Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910020286 SiOxNy Inorganic materials 0.000 claims description 2
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 230000001939 inductive effect Effects 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- XOJVVFBFDXDTEG-UHFFFAOYSA-N Norphytane Natural products CC(C)CCCC(C)CCCC(C)CCCC(C)C XOJVVFBFDXDTEG-UHFFFAOYSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 description 78
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 19
- 229910052796 boron Inorganic materials 0.000 description 19
- 239000003989 dielectric material Substances 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 239000010409 thin film Substances 0.000 description 11
- 238000000137 annealing Methods 0.000 description 10
- 239000002131 composite material Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 10
- 239000012535 impurity Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000000839 emulsion Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 238000001308 synthesis method Methods 0.000 description 2
- KJZTUUBEBITBGM-UHFFFAOYSA-N B#[Hf] Chemical compound B#[Hf] KJZTUUBEBITBGM-UHFFFAOYSA-N 0.000 description 1
- 229910008310 Si—Ge Inorganic materials 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012771 household material Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- -1 nitride nitride Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
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Description
561553 A7 B7
五、發明説明( 發明範疇 本發明係最一般性關於半導體積體電路裝置及形成此等 裝置之方法。更確切而言,本發明係關於用於形成分層閘 介電薄膜結構之材料、方法及結構,該薄膜結構包括一層 氧化物薄膜、一層氮化物薄膜及一層在氧化物和氮化物薄 膜間形成的包含氮和氧之過渡層。 發明背景 半導體積體電路裝置一般包括一層薄介電材料,一般為 熱生長氧化物’該材料充當併入半導體積體電路裝置的電 曰θ體所用之閘介電材料。閘介電材料一般在半導體基材上 的充當通道區域之區域上形成。在閘介電材料下的半導體 基材中形成通道時,電晶體回應對閘介電薄膜上形成的^ 電極所施加的電壓起作用。閘介電薄膜的品質和整合性對 電晶體裝置的官能性和壽命非常關鍵,其包括對形成電晶 體裝置所用材料和方法很敏感的一組極緊界定操作性能。 因此,抑制任何不合需要摻雜種類遷入閘介電薄膜或者通 過閘介電薄膜並遷入其下緊鄰通道區域非常重要。 多晶矽薄膜普遍用作半導體積體電路中電晶體所用的閘 電極材料。多晶矽可為”n-類型”多晶矽或”類型,,多晶矽 。例如,”P-類型”多晶矽材料指在多晶矽薄膜中包括卜類 型捧雜劑雜質之材料。在半導體工業中普遍使用且較佳的 P-類型摻雜劑為硼。在多晶矽薄膜内用硼作為雜質摻雜劑 時,將硼保持在多晶矽薄膜内具有關鍵意義,尤其是抑制 硼遷入或通過形成部分電晶體的閘介電薄膜。 -4-
561553 A7 _________B7______ 五、發明説明(2 ) 但在將硼作為摻雜雜質引入多晶矽後,用於形成半導體 裝置的隨後高溫處理操作可導致硼自多晶矽擴散並進入閘 介電材料,或者通過閘介電材料並進入閘介電區域下形成 的電晶體之通道區域。硼擴散在利用950°C至1050°C範圍 溫度以活化硼的活化製程發生。在其他高溫處理操作或操 作所完成裝置期間亦可能發生硼擴散。當硼擴散進入閘介 電材料或通道區域時,閘介電材料的可靠性降低,並可能 破壞裝置的功能性。抑制硼或其他雜質自多晶矽互連及閘 結構擴散並進入及通過閘介電薄膜的意義因此增加。因此 ’理想在閘電極/閘介電結構内具有一種内建裝置,以抑 制硼擴散出p-類型多晶矽並進入或通過閘介電材料。 抑制上述硼擴散的一個較佳方法為利用包括氧化物薄膜 和上面的矽氮化物薄膜的分層閘介電薄膜。一種替代但類 似的方法利用一層氧化物薄膜、一層氮化物薄膜及一層第 二氧化物薄膜。使氧化物薄膜及上面的氮化物薄膜組合形 成閘介電材料可成功抑制硼自p_類型多晶矽滲透進入下面 的通道區域或達到下面的氧化物薄膜和半導體基材表面間 形成的界面。此外,使氧化物及氮化物薄膜組合形成閘介 €材料亦減少電流漏泄。然而,包括石夕氮化物層之閘結構 一般帶來電荷捕陷問題且通道遷移性降低,而且驅動電流 降低。電荷捕陷問題一般存在於氧化物層和氮化物間形成 的突變界面。此等捕陷電荷難以退火。另外,用於試圖糾 正突變氮化物/氧化物界面電荷捕陷問題的退火處理一般 導致氮擴散,並使氮遷到氧化物薄膜和下面半導體基材表 •5- ^纸張尺度適时Η ®家料(CNS) a视格(21Gx 297公$-------- 561553 A7 B7 五、發明説明 面間的界面。在該界面存在氮亦導致電荷捕陷問題並使通 道遷移性降低以及驅動電流減少。 在今天快速發展的半導體裝置製造工業中,形成半導體 積體電路的元件部件不斷縮小。與此趨向一致,現正製造 越加小型尺寸的電晶體。因此,較薄閘介電薄膜必不可少
裟 此等較薄薄膜加劇以上問題,並產生其他問題。例如, 在根據習知方法製造具有在1〇至5〇埃範圍厚度之氮化物薄 膜時,薄膜可能包括針孔或小空隙。除上述能夠捕陷電荷 及使薄膜整合性降低的針孔和捕陷部件外,形成氮化物薄 膜一般在基材上發揮應力。高薄膜應力能夠導致基材中位 錯’這將導致驅動電流減小及結漏泄。
由於與硼擴散有關的問題以及由將氮化物薄膜加入閘材 料抑制擴散的同時代嘗試之缺點,說明在技藝上仍需要提 供包括足夠薄且抑制硼滲透的閘材料、無氮或其他摻雜雜 質及有關電荷捕陷問題的氧化物/基材表面界面以及無電 荷捕陷問題的氮化物/氧化物界面之方法及結構。 發明概要 為滿足此等和其他需要及考慮到其目的,本發明提供一 種用於在半導體表面上形成的半導體電晶體之閘結構。該 閘結構包括氧化物層、氮化物層以及插在氧化物層和氮化 物層間之過渡層。薄過渡層在氧化物和氮化物層間形成界 面,且包括氮和氧作為其組分,並在氧化物和氮化物之間 提供保持原態且沒有缺陷的界面。存在氮化物層抑制硼和 其他摻雜雜質不理想擴散。 6- 本紙張尺狀用中® Η家標準(CNS) A4規格(21GX撕公嫠) 561553
發明説明( 本發明亦提供一種形成電晶體閘結構方法。該方法包括 形成薄閘氧化物層。在一個較佳具體實施例中,該薄閘氧 化物層可為一種分級結構,該分級結構由單獨形成的氧化 物層之複合物組成。然後在閘氧化物層上形成包含氮和氧 之薄過渡層。在一個典型具體實施例中,過渡層可用遠端 氧化反應及不大於100°C之形成溫度形成。然後在過渡層 上沉積碎氮化物層。 所形成的閘介電結構實質上沒有電荷捕陷,且包括在氧 化物和基材間形成的高品質界面以及在氧化物和氮化物層 間形成的高品質界面。 圖式之簡單說明 自以下詳細說明結合有關附圖可對本發明獲得最佳瞭解 。應強調,根據一般實際,圖式的各種部件未按比例繪製 。相反,為清楚起見,各種部件的尺寸被任意擴大減小。 附圖中包括分別代表橫截面視圖的以下各圖: 圖1顯示一種在基材上形成的典型閘氧化物薄膜; 圖2顯示另一種在基材上形成的典型閘氧化物薄膜,特 別為分級閘氧化物薄膜; 圖3顯示一種在如圖2所示分級閘氧化物薄膜上形成的過 渡層; 圖4顯示一種在如圖3所示結構上形成的氮化物薄膜; 圖5顯示一種複合薄膜結構,該結構包括在圖4所示氮化 物層上形成的閘電極材料;及 圖6顯示一種在圖5所示複合薄膜結構圖案化後產生的典 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公爱) 裝 訂 線 561553 A7 B7 五、發明説明( 型閘結構。 在整個說明書及申請專利範圍中,相同數位代表相同部 件。 發明詳細說明 本發明知>供一種用於在半導體表面上形成的半導體電^ 體之閘結構及形成該閘結構方法本發明提供一種薄閑氧 化物層以及在該閘氧化物層上形成的薄碎氮化物薄膜。在 該薄閘乳化物層和梦氮化物薄膜之間插入一層過渡層。兮 過渡層包括氮和氧,且在氧化物層和矽氮化物薄膜之間提 供一種低應力、保持原態的界面。較佳用遠端電衆氮化 (RPN)反應器形成過渡層。在一個較佳具體實施例中,閉 氧化物可為一層由兩層單獨形成的薄膜組成的分級閘氧化 物層。在一個典型具體實施例中,分級閘氧化物薄膜可包 括2 -步驟合成法’其包括在高於薄膜黏彈性溫度之溫度使 一層氧化物薄膜生長於一層預生長的低溫熱生長Si〇2層上 ’以形成複合分級S i 02結構。所形成的複合閘介電結構可 包括小於20埃之合計厚度,因此,適用於今天的次微米整 合水平。 由本發明方法形成的結構由於存在氮化物薄膜對彌擴散 及滲透提供極佳抵抗力。因此,消除由硼滲透導致的閾電 壓Vt移位。類似亦降低閘漏泄電流。存在過渡層及用於形 成過渡層之方法使在由過渡層占據的氧化物/氮化物界面 處的固定電荷結合最小。存在過渡層亦降低遷移性h損 失。包括本發明閘介電材料的所形成電晶體亦享有可靠性 -8 - 本纸張尺度適用中國國冢標準(CNS) A4規格(210 X 297公釐) ' "" -- 561553 A7 B7 五、發明説明(6 ) 增強及低斷路狀態電流之優點。由於過渡層提供最小限度 或操固定電荷的無應力氧化物/氮化物界面,所以不需要 隨後的退火製程。由用RPN技術形成的過渡層完成的低應 力氮化物層同樣不需要隨後的退火製程。因此,排除由退 火製程帶來的不理想擴散效應。 現在轉向綠圖,圖1和圖2分別為顯示在基材上形成的典 閘氧化物薄膜之橫截面圖。圖3 - 6顯示在圖2所示的典型 分級氧化物薄膜上形成電晶體閘之製程次序。 圖1顯示基材10,該基材可為矽基材,如常用於半導體 製造工業上的習知矽晶圓。根據其他典型具體實施例,基 材10可由其他材料形成。基材1〇包括初始上表面(未顯示) ,該表面可用各種方法熱氧化,以在基材1〇上形成侵蝕基 材10的初始上表面之氧化物層。典型氧化物層14可用各種 適合方法形成,如在熱壁爐中熱氧化或使用冷壁快熱氧化 (RTO)系統。在一個典型具體實施例中,基材1〇可為矽, 而氧化物層14可為二氧化矽Si〇2薄膜。氧化物層14與基材 10形成界面16,且亦包括上表面18。氧化物層14之厚度2〇 可在5至100埃之範圍内,較佳在5至20埃範圍内,但亦可 在其他典型具體實施例使用其他厚度。所顯示表面i 2為基 材10的最上表面,且最上表面與氧化物層14形成界面16。 在一個典型具體實施例中,可將氧化物層14用作電晶體閘 所用的部分介電層,且可將其選擇性稱為閘氧化物層14。 在一個典型具體實施例中,氧化物層14為單一且連續的二 氧化矽Si02薄膜。 冬 中國國家標準(CNS) A4規格(21Gx 297公羡)---
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線 561553 A7 B7 五、發明説明(7 ) 圖2顯示在基材1〇上形成的氧化物層另一個典型具體實 施例。圖2中所示的氧化物層14G為一層由上氧化物層14u 和下乳化物14L形成的複合薄膜。圖2中所示的典型氧化物 層14G可被認作為一層分級閘氧化物薄膜,且可用2_步驟 合成方法形成,該方法包括在已形成預生長的低溫熱生長 si〇2層後以高於薄膜黏彈性溫度(Tye)之溫度生長一層氧化 物薄膜。以此方法產生複合分級Si〇2結構14G。根據分級 閘氧化物具體實施例,上氧化物層14U為由順序形成薄膜 形成的第一層或在相對低溫及低於Si〇2黏彈性溫度 Tve(〜925 C )之溫度生長的預生長Si〇2層。較下的氧化物層 14L為順序形成薄膜的第二層,且為經選擇在或高於黏彈 性ZfflL度的較鬲氧化溫度形成的薄膜。典型分級氧化製程順 序包括,在極度稀釋的氧化環境(小於〇 1%〇2)以典型94〇_ 1050t溫度於低於黏彈性溫度之溫度熱生長的預生長Si〇2 層上進行最終高溫氧化步驟。在一個典型具體實施例中, 可用在750-800 c範圍之溫度生長預生長的Si〇2層,但亦 可選擇性使用其他熱氧化溫度。在一個典型具體實施例中 ,預生長的Si〇2層14U可包括在8·15埃範圍内之厚度以, 但亦可選擇性使用其他厚度。預生長的上氧化物層ΐ4υ在 相冷卻期間提供分級及應力釋放。應小心接近Τκ調節形 成下氧化物層14L所用的第二氧化製程之冷卻速率,以增 強生長誘導的應力鬆弛。預生長的氧化物層提供分級,並 2與基材10形成界面16的最終高溫Si〇2薄膜充當應力調節 交換器。下氧化物層14L之厚度26可在5-5〇埃範圍内變化 -10-
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561553 五、發明説明(8 ) ,最佳在5至15埃之範圍内。分級和調節冷卻在氧化物層 i4G和基材U)之間產生_層無應變平面型界面μ。因此,
Sl/S叫界面相對保持原態.,且比習知技術可取得較低界 面捕陷密度。分級的氧化物薄膜14G包括上表面Μ。根據 其他典型具體實施例,可用各種操作順序形成分級氧化物 層14G’以包括低應力及相對保持原態、無缺陷的基材/氧 化物界面。 雖然可用圖1所示的典型單層氧化物層14或圖2所示的分 級、複合氧化物層14G用作欲隨後根據本發明方法處理的 閘氧化物薄膜’但圖3-6顯示在圖2所示的典型分級氧化物 層14G上形成的隨後沉積薄膜結構。 本發明在氧化物薄膜上提供一層氮化物I,以㈣硼擴 散及滲透。本發明的一個有利方面為圖3中所示在閘氧化 物層和隨後形成矽氮化物層(圖3中未顯示)間形成的過渡 層28。過渡層28包括氧和氮二者。在一個典型具體實施例 中,過渡層28可為碎氧氮化物si〇xNy薄膜。根據另一個典 型具體實施例,過渡層28可為摻氮的二氧化矽薄膜。可用 各種方法形成過渡層2 8,且根據該較佳具體實施例,可使 用不大於100°C之形成溫度。根據一個典型具體實施例, 可在遠端電漿氮化(RPN)反應器中處理圖2所示結構及分級 氧化物層14G的特定上表面18 ^此反應器較佳保持於真空 下,且使上表面18暴露於穿透上表面18並將二氧化矽(Si〇2) 傳入氧氮化物或氮摻雜的氧化物薄膜之帶負電荷氮、帶正 電荷氮及/或原子氮種類。在另一個典型具體實施例中, 11 - 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 561553 A7 B7 I、發明説明(9~~ ^ 可將過渡層28作為摻氮的氧化物或矽氧氮化物薄膜沉積於 上表面18上。可選擇性使用包含氮和氧的其他薄膜。原子 氮及其相關離子和陽離子可由遠端RF裝置、遠端電子迴 旋加速器共振(ECR)裝置及感應耦合電漿(ICP)裝置、微波 裝置或任何其他此等產生原子氮及/或帶正電荷氮和帶負 電荷氮之裝置。可使過渡層28形成低1埃之厚度,但亦可 使用至高10埃的其他厚度。根據其他典型具體實施例,過 渡層28之厚度30可呈現其他值。根據一個典型具體實施例 ,與氧化合的各種氮種類包括在分級氧化物層14G的上表 面18,以形成過渡層28。過渡層28包括上表面32。 圖4顯示在過渡層2 8上形成的碎氮化物薄膜3 4。夕氮化 物薄膜34包括厚度38,該厚度可在2-100埃範圍内,較佳 2-10埃。可用低壓化學蒸氣沉積(LPCVD)技術形成矽氮化 物薄膜3 4 ’但亦可選擇性使用其他技術。根據典型具體實 施例’可使用熱壁LPC VD加熱爐,或在減塵下使用LPC VD 冷壁快熱反應器。根據形成矽氮化物薄膜34所用的各種典 型具體實施例,應選擇操作條件,以使實質上沒有氮達到 界面16。 根據一個典型具體實施例,可形成薄膜堆,以包括小於 20埃的合計厚度36,但亦可選擇性使用其他薄膜厚度。矽 氮化物薄膜34包括上表面40。根據本發明方法形成的結構 包括在矽氮化物層34和分級氧化物層14G間形成的實質無 缺陷之界面區域41。電荷捕陷部位及因此的固定電荷在界 面區域4 1消除或最小,可將此界面區域認為過渡層28及其 -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 561553
可區別上表面和下表面。過渡層28亦減少矽氮化物薄膜34 m在分級氧化㈣14G上產生的應力。可用圖4中所示 的複合介電結構作為電晶體元件所用閘介電材料。所形成 界面1 6貝貝上供氮和電荷捕陷及與其存在有關的遷移性問 題。在一個典型具體實施例中,基材/氧化物界面16可包 括小於0.5%或更小濃度的氮,且其不超過丨原子/釐米2。 雖;二所开y成貝貝典電荷捕陷缺陷的保持原態界面-界面區 域41消除需要任何退火步驟,但仍可隨後進行選擇性退火 製私。在一個典型具體實施例,如果使用此退火製程,則 可在小於850°C之溫度及使用包含小於3%氧與惰性氣體的 溫和氧化氣體混合物進行退火製程。可在任何各種隨後處 理點進行選擇性退火製程。 圖5顯示在石夕氮化物薄膜34上形成的典型閘電極薄膜42 。在一個典型具體實施例中,閘電極薄膜42可為摻n或摻p 的多晶矽或Si-Ge合金,但亦可選擇性使用其他導電及半 導體薄膜。在一個典型具體實施例中,閘電極薄膜42可為 掺有硼的p-型材料。閘電極薄膜42包括上表面44及可根據 裝置需要變化的厚度46。在一個較佳具體實施例中,圖5 所示結構將作為欲在通道區域4 8上形成的電晶體裝置所用 之閘介電材料/閘電極。可用習知方法隨後使圖5中所示的 結構圖案化。例如,可在閘電極薄膜42之上表面44上形成 感光薄膜,且可隨後用習知方法使該感光薄膜顯影。可用 一序列習知蝕刻操作蝕刻該複合薄膜堆《或者可使用其他 方法使圖5中所示的結構圖案化。圖6顯示圖案化後的圖5 -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 561553 A7
裝
訂
線
Claims (1)
- 561553•:種半導體產物,其包括在一半導體表面上所形成的電 曰9把,其具一閘結構,包括一形成於半導體表面上的氧 化物層、一直接在該氧化物層上形成的包含氮和氧之過 渡層、一直接在該過渡層上形成的氮化物層以及在該氮 化物層上形成的閘電極層。 2·根據申請專利範圍第1項之半導體產物,其中該半導體 產物之特徵為在該半導體表面和該氮化物層間的界面實 質上無氮和氧存在。 3·根據申請專利範圍第1項之半導體產物,其中該電晶體 層包括矽氧氮化物(SiOxNy)和摻氮的二氧化矽其中之一。 4·根據申請專利範圍第丨項之半導體產物,其中該氧化物 層、該過渡層及該氮化物層之組合厚度不大於2奈米。 5· —種形成半導體產物之方法,其包括: 提供一具有矽表面之半導體基材; 在該矽表面上形成一氧化物層; 在該氧化物上形成一矽氮化物層;及 在該氧化物層和該矽氮化物層之間形成一包括氮和氧 之過渡層,為此,提供至少一種之原子形式氮、帶負電 荷氮及帶正電荷氮,以滲透該上表面並與該上表面的氧 化合,藉此將氮加到該氧化物層的上表面,並形成該過 渡層。 6.根據申請專利範圍第5項之方法,其中該形成過渡層之 步驟包括不大於100°C之形成溫度。 7·根據申請專利範圍第5項之方法,其中該形成過渡層之 -15- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 561553 A8 B8 C8 _ D8 六、申請專利範圍 - 步驟包括形成梦氧氮化物和掺氮的氧化物層之—。 8·根據申請專利範圍第5項之方法,其中該至少—種之原 子形式氮、帶負電荷氮及帶正電荷氮係藉由選自由射頻 裝置、電子迴旋加速器共振裝置、感應耦合電装裝置及 微波裝置所組成之群的遠端氮化源提供。 9·根據申請專利範圍第5項之方法,其中該形成矽氮化物 層之步驟包括使用所選擇製程條件的低壓化學蒸氣沉積 (LPCVD)製程,使得實質上沒有氮達到在該矽表面和該 氧化層間形成的界面。 10· —種形成半導體產物之方法,其包括: 提供一具有矽表面之半導體基材; 在該梦表面上形成一氧化物層; 在該氧化物上形成一矽氮化物層;及 在該氧化物層和該碎氮化物層之間形成一包括氮和氧 之過渡層, 其中該形成過渡層之步驟包括在一個遠端電漿氮化反 應器中處理該氧化物層。 11· 一種形成半導體產物之方法,其包括: 提供一具有矽表面之半導體基材; 在該矽表面上於75(TC -800°c範圍之溫度生長一第一 氧化物薄膜,然後由一個在高於該第二氧化物薄膜之黏 彈性溫度進行的熱氧化生長製程形成一第二氧化物薄膜 ,藉以在該矽表面上形成一分級的氧化物層; 在該氧化物層上形成一矽氮化物層;及 -16- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 561553 8 8 8 8 A B c D 六、申請專利範圍 在該氧化物層和該碎氮化物層之間形成一包括氮和氧 之過渡層。 -17- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
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US20020102797A1 (en) * | 2001-02-01 | 2002-08-01 | Muller David A. | Composite gate dielectric layer |
US20030104707A1 (en) * | 2001-11-16 | 2003-06-05 | Yoshihide Senzaki | System and method for improved thin dielectric films |
GB0204308D0 (en) * | 2002-02-23 | 2002-04-10 | Voith Fabrics Heidenheim Gmbh | Papermachine clothing |
TWI225668B (en) * | 2002-05-13 | 2004-12-21 | Tokyo Electron Ltd | Substrate processing method |
US6890831B2 (en) | 2002-06-03 | 2005-05-10 | Sanyo Electric Co., Ltd. | Method of fabricating semiconductor device |
JP2005101503A (ja) * | 2003-03-26 | 2005-04-14 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP4717385B2 (ja) * | 2003-08-27 | 2011-07-06 | 三菱電機株式会社 | 半導体装置 |
KR100604846B1 (ko) | 2004-04-23 | 2006-07-31 | 삼성전자주식회사 | 다층의 유전체층을 포함하는 메모리 소자 및 그 제조 방법 |
JP4579637B2 (ja) * | 2004-10-01 | 2010-11-10 | 東京エレクトロン株式会社 | 半導体記憶装置及びその製造方法 |
EP1691383A1 (en) * | 2005-02-14 | 2006-08-16 | TDK Corporation | Capacitor, method of making the same, filter using the same, and dielectric thin film used for the same |
KR20060095819A (ko) * | 2005-02-28 | 2006-09-04 | 삼성전자주식회사 | 금속 질화물을 트랩 사이트로 이용한 메모리 소자를 그 제조 방법 |
KR100601995B1 (ko) | 2005-03-02 | 2006-07-18 | 삼성전자주식회사 | 물성 변환층을 이용한 트랜지스터와 그 동작 및 제조 방법 |
KR100761361B1 (ko) * | 2006-05-02 | 2007-09-27 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조방법 |
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KR100792412B1 (ko) * | 2006-12-27 | 2008-01-09 | 주식회사 하이닉스반도체 | 서로 반대되는 성질의 응력을 갖는 다중 하드마스크를구비한 반도체소자 및 그의 제조 방법 |
US20100244206A1 (en) * | 2009-03-31 | 2010-09-30 | International Business Machines Corporation | Method and structure for threshold voltage control and drive current improvement for high-k metal gate transistors |
WO2011097178A2 (en) * | 2010-02-02 | 2011-08-11 | Applied Materials, Inc. | Methods for nitridation and oxidation |
US10515905B1 (en) * | 2018-06-18 | 2019-12-24 | Raytheon Company | Semiconductor device with anti-deflection layers |
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EP1266054B1 (en) * | 2000-03-07 | 2006-12-20 | Asm International N.V. | Graded thin films |
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