TW557542B - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
TW557542B
TW557542B TW091116347A TW91116347A TW557542B TW 557542 B TW557542 B TW 557542B TW 091116347 A TW091116347 A TW 091116347A TW 91116347 A TW91116347 A TW 91116347A TW 557542 B TW557542 B TW 557542B
Authority
TW
Taiwan
Prior art keywords
oxide film
film
semiconductor device
substrate surface
mentioned
Prior art date
Application number
TW091116347A
Other languages
English (en)
Inventor
Takashi Kuroi
Katsuyuki Horita
Katsuomi Shiozawa
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of TW557542B publication Critical patent/TW557542B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)

Description

^^7542 修正 月 曰 —-MM 91118347 六、申請專利範圍 並+ 5 Ϊ t請專利範圍第1項之半導體裝置之製造方法， 兵T，另包括： 述上(^)以1上述步驟（e)之後露出之上述第1半導體膜之上 6 Μ晶成長法成長第2半導體膜的步驟。 其中，·另t請專利範圍第1項之半導體裝置之製造方法， 部之2)；»於^上述步驟（d)之前，在上述第1絕緣膜之開口角 丨之7對應位置形成斜面的步驟。 直中7，· t Ϊ請專利範圍第6項之半導體裝置之製造方法， 八中上迷步驟（h)係包括： 上述上述步驟（a)之後，形成第2絕緣膜用於覆蓋 述弟1絕緣膜的步驟；及 形狀2 ^1驟對上述第2絕緣膜進行非等向性蝕刻而形成側壁 上述料而 少 側面。 ’係包括上述側壁形狀之上述第2絕緣膜之 JL中8，· T t Ϊ專利範圍第6項之半導體裝置之製造方法， Τ上述步驟（h)係包括： 開σ (角於上述步驟（a)之後，對上述第1絕緣膜之上述 9 :ΪΓ虫刻而形成上述斜面的步驟。 製造方法，ΪΪ利範圍第1至8項中任-項之半導體裝置之 準標記區；一，上述半導體基板係包括元件形成區及對 上述步驟（C)係包括： 1 2108-5050-PFl(N).ptc 第28頁 M7542 9111fi^7
六、申請專利範圍 (C丨）除去上述元件形成區内之上沭以备儿时 除去上述對〜厂 u、+、始、上迷第1乳化膜，但不 對丰私圮區内之上述第1氧化膜的步驟。 1〇· 一種半導體裝置之製造方法，包括： 膜的(二1於半導體基板之基板表面1以特定圖型形成” ，的步驟’上述半導體基板係包 成:邑广 區； u丨卞仏欣（he及對準標記 另包括： (D於上述步驟（i)之後露出 成長法成長半導體膜的步驟； 《基板表面上以遙晶 面之(ίί)产對广於述Λ、導體膜施予研磨俾使上述半導體膜之上 ,,;上述絕緣膜之上面之高度的步驟；及 C 1 )於上述步驟（k )之後，你μ、+，坤丄 ^ S - nn n ^ , 吏上述對準軚記區内之露出 表面之凹凸增大據以形成對準標記的步驟。 11·如申請專利範圍第10項t半導體裝置之製造方 法’其中’上述步驟（丨）係包括： 部分(d除去上述對準標記區内之上述絕緣膜之至少- 之半導體裝置之製造方 内之上述半導體膜之至少 12·如申請專利範圍第1〇項 法，其中，上述步驟（丨）係包括 (1 - 2 )除去上述對準標記區 一部分的步驟。
TW091116347A 2001-09-20 2002-07-23 Method of manufacturing semiconductor device TW557542B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001286920A JP2003100861A (ja) 2001-09-20 2001-09-20 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW557542B true TW557542B (en) 2003-10-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW091116347A TW557542B (en) 2001-09-20 2002-07-23 Method of manufacturing semiconductor device

Country Status (4)

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US (2) US6737315B2 (zh)
JP (1) JP2003100861A (zh)
KR (1) KR100503935B1 (zh)
TW (1) TW557542B (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4439935B2 (ja) * 2004-02-02 2010-03-24 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US7186622B2 (en) 2004-07-15 2007-03-06 Infineon Technologies Ag Formation of active area using semiconductor growth process without STI integration
US7298009B2 (en) 2005-02-01 2007-11-20 Infineon Technologies Ag Semiconductor method and device with mixed orientation substrate
DE102005039667A1 (de) * 2005-08-22 2007-03-01 Infineon Technologies Ag Verfahren zum Herstellen einer Struktur mit geringem Aspektverhältnis
US8530355B2 (en) 2005-12-23 2013-09-10 Infineon Technologies Ag Mixed orientation semiconductor device and method
KR100775963B1 (ko) 2006-07-12 2007-11-15 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR100806351B1 (ko) * 2007-02-16 2008-02-27 삼성전자주식회사 반도체 장치의 형성 방법
JP2008218656A (ja) * 2007-03-02 2008-09-18 Denso Corp 半導体装置の製造方法及び半導体ウエハ
JP5586970B2 (ja) 2010-01-25 2014-09-10 キヤノン株式会社 情報処理装置および制御方法およびプログラム
JP2014216377A (ja) * 2013-04-23 2014-11-17 イビデン株式会社 電子部品とその製造方法及び多層プリント配線板の製造方法

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JPS59129439A (ja) 1983-01-14 1984-07-25 Nec Corp 半導体装置用基板の製造方法
JPS61203632A (ja) * 1985-03-06 1986-09-09 Nec Corp 半導体基板
JPH042115A (ja) * 1990-04-19 1992-01-07 Fujitsu Ltd 半導体装置の製造方法
JP3500820B2 (ja) 1995-11-24 2004-02-23 ソニー株式会社 半導体装置の製造方法
JPH10312964A (ja) * 1997-05-13 1998-11-24 Sony Corp 半導体装置の製造方法
US5894152A (en) * 1997-06-18 1999-04-13 International Business Machines Corporation SOI/bulk hybrid substrate and method of forming the same
US5930620A (en) * 1997-09-12 1999-07-27 Advanced Micro Devices Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures
JP2000031480A (ja) * 1998-07-15 2000-01-28 Sony Corp 半導体層の形成方法及び半導体装置の製造方法
JP2000100931A (ja) * 1998-09-25 2000-04-07 Seiko Epson Corp 半導体装置及びその製造方法
JP2001015591A (ja) * 1999-06-30 2001-01-19 Toshiba Corp 半導体装置の製造方法・半導体装置
JP4649006B2 (ja) * 1999-07-16 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置
JP3308245B2 (ja) * 1999-08-12 2002-07-29 住友ゴム工業株式会社 空気入りタイヤ
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JP3609737B2 (ja) * 2001-03-22 2005-01-12 三洋電機株式会社 回路装置の製造方法

Also Published As

Publication number Publication date
KR20030025819A (ko) 2003-03-29
US20030054597A1 (en) 2003-03-20
US6737315B2 (en) 2004-05-18
US20040082165A1 (en) 2004-04-29
JP2003100861A (ja) 2003-04-04
KR100503935B1 (ko) 2005-07-26
US6890837B2 (en) 2005-05-10

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