TW556214B - Methods for reducing the number of interconnects to the PIRM memory module - Google Patents

Methods for reducing the number of interconnects to the PIRM memory module Download PDF

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Publication number
TW556214B
TW556214B TW091111446A TW91111446A TW556214B TW 556214 B TW556214 B TW 556214B TW 091111446 A TW091111446 A TW 091111446A TW 91111446 A TW91111446 A TW 91111446A TW 556214 B TW556214 B TW 556214B
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TW
Taiwan
Prior art keywords
memory
circuit
interface
patent application
scope
Prior art date
Application number
TW091111446A
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English (en)
Chinese (zh)
Inventor
Carl P Taussig
Original Assignee
Hewlett Packard Co
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Publication date
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Publication of TW556214B publication Critical patent/TW556214B/zh

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
  • Semiconductor Memories (AREA)
TW091111446A 2001-06-29 2002-05-29 Methods for reducing the number of interconnects to the PIRM memory module TW556214B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/894,143 US6478231B1 (en) 2001-06-29 2001-06-29 Methods for reducing the number of interconnects to the PIRM memory module

Publications (1)

Publication Number Publication Date
TW556214B true TW556214B (en) 2003-10-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW091111446A TW556214B (en) 2001-06-29 2002-05-29 Methods for reducing the number of interconnects to the PIRM memory module

Country Status (7)

Country Link
US (1) US6478231B1 (enExample)
EP (1) EP1271539B1 (enExample)
JP (1) JP3953902B2 (enExample)
KR (1) KR20030003054A (enExample)
CN (1) CN1395252A (enExample)
DE (1) DE60212004T2 (enExample)
TW (1) TW556214B (enExample)

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* Cited by examiner, † Cited by third party
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US5673218A (en) 1996-03-05 1997-09-30 Shepard; Daniel R. Dual-addressed rectifier storage device
US6956757B2 (en) 2000-06-22 2005-10-18 Contour Semiconductor, Inc. Low cost high density rectifier matrix memory
AU2001294817A1 (en) * 2000-09-27 2002-04-08 Nup2 Incorporated Fabrication of semiconductor devices
US7800932B2 (en) * 2005-09-28 2010-09-21 Sandisk 3D Llc Memory cell comprising switchable semiconductor memory element with trimmable resistance
US7139183B2 (en) * 2004-07-21 2006-11-21 Hewlett-Packard Development Company, L.P. Logical arrangement of memory arrays
US7106639B2 (en) * 2004-09-01 2006-09-12 Hewlett-Packard Development Company, L.P. Defect management enabled PIRM and method
US20080025069A1 (en) * 2006-07-31 2008-01-31 Scheuerlein Roy E Mixed-use memory array with different data states
US7486537B2 (en) * 2006-07-31 2009-02-03 Sandisk 3D Llc Method for using a mixed-use memory array with different data states
US7450414B2 (en) * 2006-07-31 2008-11-11 Sandisk 3D Llc Method for using a mixed-use memory array
US7393739B2 (en) * 2006-08-30 2008-07-01 International Business Machines Corporation Demultiplexers using transistors for accessing memory cell arrays
US7813157B2 (en) 2007-10-29 2010-10-12 Contour Semiconductor, Inc. Non-linear conductor memory
US8045416B2 (en) 2008-03-05 2011-10-25 Micron Technology, Inc. Method and memory device providing reduced quantity of interconnections
US8325556B2 (en) 2008-10-07 2012-12-04 Contour Semiconductor, Inc. Sequencing decoder circuit
US8422324B2 (en) * 2011-08-26 2013-04-16 Nanya Technology Corp. Method and apparatus for sending test mode signals
EP2946385B1 (en) 2013-01-18 2020-01-08 Hewlett-Packard Enterprise Development LP Interconnection architecture for multilayer circuits
KR102222445B1 (ko) 2015-01-26 2021-03-04 삼성전자주식회사 선택적으로 동작하는 복수의 디램 장치를 포함하는 메모리 시스템
CN109884613A (zh) * 2019-03-29 2019-06-14 湖南赛博诺格电子科技有限公司 一种基于fpga的二极管阵列在线同步控制系统及方法

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US4415991A (en) * 1981-06-22 1983-11-15 The United States Of America As Represented By The Secretary Of The Navy Multiplexed MOS multiaccess memory system
JPS63128463A (ja) * 1986-11-18 1988-06-01 Nec Corp マイクロプロセツサ多重化システム構成
FR2629941B1 (fr) * 1988-04-12 1991-01-18 Commissariat Energie Atomique Memoire et cellule memoire statiques du type mis, procede de memorisation
JPH0935490A (ja) * 1995-07-17 1997-02-07 Yamaha Corp 半導体記憶装置
US5909617A (en) * 1995-11-07 1999-06-01 Micron Technology, Inc. Method of manufacturing self-aligned resistor and local interconnect
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KR100289813B1 (ko) * 1998-07-03 2001-10-26 윤종용 노아형플렛-셀마스크롬장치
JP3344331B2 (ja) * 1998-09-30 2002-11-11 日本電気株式会社 不揮発性半導体記憶装置
US6256767B1 (en) * 1999-03-29 2001-07-03 Hewlett-Packard Company Demultiplexer for a molecular wire crossbar network (MWCN DEMUX)
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Also Published As

Publication number Publication date
EP1271539A3 (en) 2004-06-23
JP2003022690A (ja) 2003-01-24
DE60212004D1 (de) 2006-07-20
CN1395252A (zh) 2003-02-05
US6478231B1 (en) 2002-11-12
KR20030003054A (ko) 2003-01-09
JP3953902B2 (ja) 2007-08-08
DE60212004T2 (de) 2007-03-29
EP1271539B1 (en) 2006-06-07
EP1271539A2 (en) 2003-01-02

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