TW536765B - Chip package structure for array type bounding pad - Google Patents

Chip package structure for array type bounding pad Download PDF

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Publication number
TW536765B
TW536765B TW090125929A TW90125929A TW536765B TW 536765 B TW536765 B TW 536765B TW 090125929 A TW090125929 A TW 090125929A TW 90125929 A TW90125929 A TW 90125929A TW 536765 B TW536765 B TW 536765B
Authority
TW
Taiwan
Prior art keywords
pads
pad
row
wafer
innermost
Prior art date
Application number
TW090125929A
Other languages
English (en)
Inventor
Wen-Lung Cheng
I-Feng Chang
Hung-Cheng Huang
Original Assignee
Acer Labs Inc
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Filing date
Publication date
Application filed by Acer Labs Inc filed Critical Acer Labs Inc
Priority to TW090125929A priority Critical patent/TW536765B/zh
Priority to US10/142,453 priority patent/US6707164B2/en
Priority to JP2002188887A priority patent/JP2003133470A/ja
Application granted granted Critical
Publication of TW536765B publication Critical patent/TW536765B/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

536765 ^S-J〇l25929 五、發明說明（1) 本發明係有關於_私η 種具有至少四排之陳引日日片封裝結構，且特別有關於一 晶片封裝結構、球林瞌型銲墊的打線式（wire—bonding) 或倒裝晶片（fUp Ch車列（Bal1 Grid Array，bga)結構 隨著半導體科技的構。 其設計複雜度日=决進，半導體晶片的執行速度以及 (packaging)也皿不^丨雜因此，半導體之封裝 就打線式的封/上新，以期提昇封裝效率。
Pad)配置是一個重、要°冓而/ ，晶片上的銲墊（bonding 格陣列（BGA )結構中，=即，因為在封裝結構，例如球 製程而使間隙變得極丨’土板上的導電線路可以利用微影 Pitch) fBl'E (b〇ndlng ^ 法設計成與導電線路相 業之/隔原則與設計原則，無 計是決定鲜塾封裝鲜塾配置設 一般而言，晶片夕 的連接（簡稱輪人Am與n決定其與外部電路元件 具體地說，功能越多m接Λ1 /〇 ί接）數目與方式。更 多。因此，I C銲塾配w 日曰 八1/0連接一般也越 目前常見的ί=Γ須：慮其功能來決定。 in-line )銲墊設計于配置广广包括有單排（single 計。由於晶片的功能Λ及；;錯型曰==…鲜塾設 墊數也必須增加，單: < =片表面之取大可容許銲 錯型銲墊設計可捭力4 ，墊6又计”，、法滿足此一需求；而交 度’故較廣為採用。有關交錯型鲜塾之晶片速設 536765 ___案號 90125929__年月日_修正____， 五、發明說明（2) 計可參見第1圖與第2圖。 第1圖與第2圖揭示一習知交錯型銲墊之晶片封褒結構 100。該封裝結構1 00包括一基板120，基板120的上表面設 置有一父錯型銲墊晶片110、一接地環（ground ring) I 30、一電源環（power ring ) 1 40以及複數導電線路 (conductive trace) 160。晶片110表面設置有複數銲墊 122，如第2圖所示，配置成交錯的兩排。銲墊122包括用 以接地的接地墊、用以提供電源的電源墊、以及用以輸入 /輸出訊號的訊號墊（或稱輸入/輸出墊，〗/〇墊）。另 外’銲墊122分別由銲線122a、122b、122c與12 2d連接至 接地環1 3 0、電源環1 4 0以及導電線路1 6 〇。最後，由一封 膠體（package body ) 1 50 包覆晶片 11 〇、銲線1 22a、 122b、122c與122d、以及基板120上表面，而完成封裝。 如第2圖所示，銲線122a係將外側之銲墊122做為接地 墊而連接至接地環130 ;銲線122b係將外側之銲墊122做為 電源墊而連接至電源環1 4 0 ;銲線1 2 2 c係將外側之銲墊1 2 2 做為訊號墊連接至導電線路丨60 ;而銲線122d係將内側之 銲墊1 2 2做為訊號墊連接至導電線路丨6 〇。在此習知例中， 銲墊1 2 2中之訊號墊數目較多，因此將連接至較接近晶片 II 〇之接地環1 3 0與電源環1 4 0的接地墊與電源墊配置於外 側’且銲線係分層（t； i e r )配置，以避免發生短路。如第 1圖曰所示，銲線122a與122b之線弧高度（loop height)係 車乂銲線122c低，而銲線1 22c之線弧高度係較銲線丨22d低。 然而，上述交錯型銲墊配置方法的晶片表面之最大可
536765 案號 90125929 五、發明說明（3) 片面積，如此會使晶片變大，成本提高，且影響良率。因 此，習知技術已提出一種三排陣列銲墊之晶片封裝結構， 其設計可參見第3圖與第4圖說明之。 第3圖與第4圖揭示習知的三排陣列銲墊之晶片封裝結 構20 0，與交錯型銲墊封裝結構類似，該封裝結構2 〇〇包括 一基板220，基板2 20的上表面設置有一三排陣列銲墊晶片 210、一接地環2 30、一電源環240以及複數導電線路26〇。 如第4圖所不，晶片2 1 〇表面設置有配置成交錯排列成三排 的銲塾222，#中，外排銲塾222只包含電源塾以及接地 墊，而中排及内排的銲墊22 2做為訊號墊。如第3圖所示， 外排銲塾222由低層銲線222a連接至接地環23〇或電源環 240 ,而中排與内排的銲墊2 22分別由 222b與222c連接至導雷螅政9Rn . ^日”门層的知線 F曰最後，由一封膠體250包 f曰曰片。0、、#線222a、222b與222c、以及基板22〇上表 面’而完成封裝。 上述習知的交錯型晶片封裝結 封裝結構200係、以打線式封装 U & 一排陣列日日片 而 ^ Λ ΛΑ 了衣W構做為範例加以說明，麸 :裝 差異在於打線式封裝結構係以y線格1^(bga )結構，其 而倒裝晶片結構或球格陣列^導電線路與銲墊， 式，或是將晶片上的銲塾予;j t透過將晶片倒裝的方 以銲線打線的方式，即可直12列式排列’如此不需 晶片上的銲塾排列為其重點接^導電線路與銲墊。由於 封裝結構100或三排陣M a u此上述習知的交錯型晶片 __---徘單列曰曰片封裝結構200也可應用於倒裝 0636-7180TWFl.ptc 536765
晶片（F 1 i p Ch i p )結構或球格陣列（BGa )結構。 使相排陣列銲墊之晶片封裳結構的配置可 使相冋曰曰片面積的最大可容許銲墊數增加，然而， 口 有外排銲墊包含電源墊以及接地墊，因此電源墊 ^ 墊的數目仍然受到限制，所增加的最大可容許銲墊數^地 限，換言之，相同銲墊數之晶片面積可減小的範 限制、。且由於習知三排陣列銲墊之晶片封裝結構的配=1 中’連接電源墊或接地墊的銲線之間距離接近，而數旦 J增加，所造成的電感效應會產生雜訊，因而影響訊二品 發明概述： 有鐘於此， 構，可使得相同 換曰之’本發明 小，因而降低成 本發明之另 設計可使得銲線 少，有效控制訊 本發明之第 板，具有一基板 一電源環以及複 表面，晶片之週 一最内排銲墊、 排銲墊，其中最 且最外排銲墊以 本發明之 晶片面積 於相同銲 一目的在於 提出一種晶片封裝結 許銲墊數更為增加； 使晶片面積更為減 封裝良率。 晶片’其鲜塾配置之 所造成的電感效應降低，因而使雜訊減 號品質。 一形態係揭示一種封 的最大可容 墊數時，可 本，且容易控制晶片 一目的在於提出一種 上表面， 數導電線 邊具有複 一次内排 内排銲墊 及次外排 裝結構，包括：一基 該基板上表面設置有一接地環、 路；以及一晶片，設置於基：板上 數銲墊，排列成至少四排，包括 銲墊、一次外排銲墊以及一最外 銲墊只包括訊號墊’ 電源墊以及接地墊。 以及次内排 銲墊只包括
0636-7180TWFl.ptc 第7頁 536765 案號 90125929 五、發明說明（5) 上述第一形悲之封裝結構可為一倒裝晶片結構（F 1 i p Chip Structure )或一球格陣列（BGA )封裝結構。 又，上述第一形態之封裝結構更可包括y: °一组 線，分別電性連接該晶片之最外排銲墊中之電源塾至基板 之電源環，以及電性連接最外排銲墊中之接地墊至美 接地環，纟中第一組銲線具有大體相同之線弧高度？一第 一組銲線，分別電性連接該晶片之次外排銲墊中之 至基板之該電源環，以及電性連接次外地 ;基板；接：：線其：第二組鲜線具有大體相同之= J 二組#線’分別電性連接該晶片之次内排鲜塾至 iii”應之？電線路，其中第三組銲線具有大體相同 —弟四組銲線’分別電性連接該晶片之最内 1if:基ί上相對應之導電線路，其中第四組鋅線具有 i 高f;以及一封膠體，包覆晶片、第- 上ί 1封ΐ =、，且以及第四組銲線、以及基板上表面。 對於B ^ t fy;構中，最内排銲墊與次内排銲墊係可相 = 銲墊係可相對於“ 片之侧邊垂直對齊塾卜排鲜塾係可相對於晶 中：一 2 f ?裝結構中，銲墊係可構成複數銲墊組， i直針審於县、，且匕括一個最内排銲墊、一個次内排銲墊、 ίΐ=ΞίΓ銲塾的一個次外排銲塾、以及垂直對齊 度個最外排銲塾。另外，每-銲塾組之寬 ^更了相專於兩個鋒墊間距（bonding pad pitch)之寬 0636-7180TWFl.ptc 第8頁 536765 案號 90125929 五、發明說明（6) 本發明之第二形態係揭示一種 複數銲墊位於該晶片之上表面週邊 排列成至少四排，包括一最内排銲 a外排鮮塾以及一最外排鲜塾’其 排銲墊只包括訊號墊，且最外排銲 括電源墊以及接地墊。 上述第二形態之陣列型銲墊晶 内排銲墊係可相對於晶片之一側邊 係可相對於晶片之側邊垂直對齊最 墊係可相對於晶片之側邊垂直對齊 又，上述第二形態之陣列型銲 成複數鲜墊組，其中每一鲜塾組包 個次内排銲墊、垂直對齊於最内排 墊、以及垂直對齊於次内排銲墊的 外’每一銲墊組之寬度更可相等於 (bonding pad pitch)之寬度。 上述陣列型銲墊晶片可適用於 適用於一球格陣列結構。 透過本發明之陣列型銲墊之晶 相同晶片面積的最大可容許銲墊數 使用本發明之陣列型銲墊之晶片封 與習知晶片相同的銲塾數時，可使 而降低晶片封裝成本，且容易控制 另外，透過本發明之陣列型銲 & 1：源、I以及接地墊設計成配置於 列 型 銲 墊 晶 片 ， 包 括 其 特 徵 在 於 參 修 銲 墊 係 ，— 次 内 排 銲 墊 — 最 内 排 鲜 墊 以 及 次 内 以 及 次 外排 銲 墊 只 包 中 9 最 内 排 銲 墊 與 次 錯 排 列 9 次 外排 銲 墊 排 銲 墊 且 最 外排 銲 内 排 銲 墊 〇 晶 片 中 5 銲 墊 係 可 構 個 最 内 排 銲 墊 墊 的 一 個 次 外排 銲 個 最 外 排 銲 墊 〇 另 個 銲 墊 間 距 倒 裝 晶 片 結 構 或 可 封 裝 結 構 可 具 有 使 加 的 優 點 ， 換 之 結 構 9 在 晶 片 上 具 有 片 面 積 更 為 減 小 5 因 片 封 裝 良 率 〇 之 晶 片 封 裝 結 構 9 由 以及次外排袭
0636.7180TWFl.ptc 第9頁 536765 曰 正 案號 90125929 五、發明說明（7) - 墊’較習知的三排陣列銲塾之晶片封裝纟士 雷、s μ 〇構的配置可增加 電源塾以及接地塾的配置，故可使得連接 二 的銲線增加，而使得所造成的電感效應降了 ，接也墊 因此，本發明可有效控制晶片傳輸的訊號品質夕雜Λ。 為使本發明之上述及其他目的、特徵^優點許爭日日萌 易懂，下文特舉數個較佳實施例，並配合岡b更月顓 說明。 1 σ所附圖式做詳細 圖式說明： 剖二圖係顯示習知交錯型銲塾之晶片封震結構的局部 去除知交錯型鲜塾之晶片封裝結構 咏封膠體1 5 0後的局部上視圖。 傅 部剖Γ圖圖係顯示習知三排陣列鲜塾之晶片封裝結構的局 構去Γ封圖Λ顯示第3圖之習知三排陣列鮮墊之晶片封褒結 示封勝體2 5 0後的局部上視圖。 Ό 視圖第5圖係顯示本發明一實施例之陣列型銲墊晶片的上 =6圖係顯示第5圖中銲墊排列的示意圖。 結構的7局圖印係顯示本發明一實施例中陣列型銲墊晶片封裝 〜σΙ剖面圖。 構去ί 11示第7圖中陣列型鲜塾晶片封袭社 得云除封膠體50後的局部上視圖。 衣、、°
0636-7180TWF1. 第10頁 536765 _案號90125929_年月日_^ 五、發明說明（8) 符號說明： 1〜封裝結構； 1 0〜陣列型銲墊晶片； 1 2、1 2 0、2 2 0 〜基板； 20、122、2 22 〜銲墊； 2 1〜最外排銲墊； 2 2〜次外排銲墊； 2 3〜次内排銲墊； 24〜最内排録墊； 2 1 a〜第一組鮮線； 2 2 a〜第二組銲線； 2 3 a〜第三組銲線； 2 4 a〜第四組銲線； 2 5〜鲜塾組； 3 0、1 3 0、2 3 0〜接地環； 40、140、240〜電源環； 50、150、250〜封膠體； 6 0、1 6 0、2 6 0〜導電線路； P〜銲墊間距； I 0 0〜交錯型銲墊之晶片封裝結構； II 0〜交錯型銲墊晶片； 122a、12 2b、122c、122d、222a、222b、222c 〜銲 線， 2 0 0〜三排陣列銲墊之晶片封裝結構； 2 1 0〜三排陣列銲墊晶片。
0636-7180TWFl.ptc 第11頁 536765 SS—M25929 曰 修正 五、發明說明（9) 實施例 請 片1 〇 〇 片10之 少四排 最内排 最外排 只用以 只用以 為 說明有 第 墊24與 墊配置 錯排列 最内排 直對齊 墊21 ( 排列。 (bond 即一個 内排銲 銲墊23 每一銲
0636-7180TWFl.ptc 第12頁 詳細說明： 參見第5圖’說明本發明一實施例之陣列型銲墊晶 該實施例中，晶片1 〇上配置有複數銲墊2 〇，位於晶 上表面週邊。本發明之特徵在於銲墊2 〇係排列成至 以上’例如本實施例中為四排，由内而外分別為一 銲墊24、一次内排銲墊23、一次外排銲墊22以及一 銲墊2 1。另外，最内排銲墊2 4以及次内排銲墊2 3係 做為訊號墊，且最外排銲墊2丨以及次外排銲墊2 2係 做為電源墊以及接地墊。 更具體地描述本發明之銲墊排列，請參考第6圖， 關第5圖中銲墊2 〇排列的特徵。 6圖中，銲墊2 〇排列的方式係如下所述。最内排銲 人内排銲墊2 3 (即吼號墊）係類似於習知交錯型銲 的方法，相對於晶片10之一侧邊（參考第5圖）交 ’曰而次外排銲墊2 2係相對於晶片丨〇之側邊垂直對齊 ，墊2 4 ’且最外排銲墊2 1係相對於晶片丨〇之側邊垂 ;人2排銲墊23。換言之，次外排銲塾22與最外排銲 即接地墊與電源塾）也係相對於晶片1〇之側邊交錯 又，銲塾20與銲塾20之間係間隔有鲜塾間距 ing pad pitch)P，而由备 ^ .^ , 叩田母一排銲墊20各取一個， 最内排鲜塾2 4、一個次内姑&日批 航9/1从y u t 人円排#墊23、垂直對齊於最 塾2 4的一個次外排鋅墊2 2、^^ ^ y η 匕 以及垂直對齊於次内排
的一個最外排銲墊21，構忐 & b F .,oc: 而— 褥成—組銲墊組2 5。如此， 墊組2 5之寬度即如第6圖所千* ____] # $相4於兩個銲墊間距p 536765 案號 90125929
之寬度2P。藉由如此的配置，即可設計出本發明之陣列型 銲墊晶片1 0。 請再參見第7圖與第8圖，說明本發明一實施例之陣列 型銲墊晶片封裝結構1。 ' 如第7圖與第8圖所示，陣列型銲墊晶片封裝結構i包 括一基板1 2 ’基板1 2的上表面設置有一接地環3 〇、一電源 環4 0、複數導電線路6 〇、以及如前所述的陣列型銲墊晶片 10。晶片10表面設置有如前述配置的銲墊2〇，由晶片1〇内 向外同樣分別為最内排銲墊2 4、次内排銲墊2 3、次外排鲜 墊22以及最外排銲墊21。 如第7圖所示，最外排銲墊21係由線弧高度位於最低 層之第一組銲線2 1 a連接至接地環3 〇 ;次外排銲墊2 2係由 線孤局度位於第一組銲線2 1 a上方之第二組銲線2 2 &連接至 電源環40 ;而次内排銲墊23以及最内排銲墊24係用以做為 汛號墊’分別由線弧高度位於第二組銲線22a上方之第三 組銲線23a，以及最上方之第四組銲線22a連接至導電線路 6〇 °最後，由一封膠體50包覆晶片1〇、銲線21a、22a、 2 3a與2 4a、以及基板12上表面，而完成封裝。上述的第— =銲線21a、第二組銲線22a、第三組銲線23a以及第四組 銲線24a係分別具有大體相同的高度，以分別錯開而避免 短路。 在此必須特別說明，本實施例中，最外排銲墊2丨係僅 做為接地墊，全部由線弧高度位於最低層之第一組銲線 21a連接至接地環3〇，而次外排銲墊22係僅做為電源墊， 由線弧高度位於第一組銲線2 i a上方之第二組銲線22a連接
536765 月 曰 —修正 皇號 90125929^ 五、發明說明（11) 至電源環240 ;铁而 ,^ 言之，只要各二，發明並非限定於如此的配置，換 。以及次外排鮮以;免短路，最外排銲墊 僅以最外排銲塾21做為電源塾，而次是 地墊等的配置，皆可使用於本發明。‘塾22僅做為接 另卜上述只施例係以打線式封穿：έ士搂兹/, 型鮮墊晶片以及其封裝結構之特徵，例說明陣列 r陣列結構，以及其他類似裝結構或-裝晶片結構或球格陣列結構與打線ΐ封如㈣述，倒 打線式封裝、结構係以銲線 電路的差異在於 將晶片上的薛塾予以球格陣列；：;片到裝的方式，或是 ^的方式，即可直接連接導電線路口此：需以鮮線打 要係以晶片上之銲墊排列為特此。由於本發明主 r曰片以及其封裝結構，如第5圖以因=明之陣列型銲 :於倒裝晶片（Flip Chi :6圖所示，也可應 構。 飞衣格陣列（BGA )結 另外’本發明並不限定於每 合乎晶片設計需求的情況下，、可於二：例之四排銲墊；在 外的排數’以達到晶片之需求。、婷塾之外另增加額I擊 雖然本發明已以數個較佳 :::定本發明，任何熟習此項技藝】露：上，然其並非 之=匕=些許的更動與潤i不發明 --!L_圍田視後附之申請專利範圍所取:因此本發明 IIIIWiffiiELwm隱mi燃侧，_ r~— ---匕疋者為準 第14頁 0636-7180TWFl.ptc

Claims (1)

  1. 536765
    1 · 一種封裝結構，包括： 一基板’具有一基板上表面，該基板上表面設置有一 接地環、一電源環以及複數導電線路；以及 一晶片，設置於該基板上表面，該晶片之週邊具有複 數麵墊’邊等銲墊係排列成至少四排，包括一最内排銲 墊、一次内排銲墊、一次外排銲墊以及一最外排銲墊，其 中為最内排銲墊以及該次内排銲墊只包括訊號墊，且該最 外排銲墊以及該次外排銲墊只包括電源墊以及接地墊。 2.如申請專利範圍第1項所述之封裝結構，更包括： 一第一組銲線，分別電性連接該晶片之該最外排銲墊 中之電源墊至該基板之該電源環，以及電性連接該最外排 銲塾中之接地墊至該基板之該接地環，其中該第一組銲線 具有大體相同之線弧高度； 一第二組銲線，分別電性連接該晶片之該次外排銲墊 中之電源墊至該基板之該電源環，以及電性連接該次外排 知墊中之接地墊至該基板之该接地環，其中該第二組鲜線 具有大體相同之線弧高度； 、 、 一第三組銲線，分別電性連接該晶片之該次内排銲塾 至該基板上相對應之該等導電線路，其中該第三組銲線具 有大體相同之線弧高度； 一第四組銲線，分別電性連接該晶片之該最内排銲塾 至a亥基板上相對應之該等導電線路，其中該第四組鐸線具 有大體相同之線弧高度；以及 一封膠體，包覆該晶片、該等第一組、第二組、第 組以及第四組銲線、以及該基板上表面。
    0636-7180TWFl.ptc 第15頁 536765 __案號90125929 车月 日 铬?f · 六、申請專利範圍 3 ·如申請專利範圍第1項或第2項所述之封裝結構，其 中： 該最内排銲塾與該次内排銲塾係相對於該晶片之一側 邊交錯排列； 該次外排鮮塾係相對於該晶片之該側邊垂直對齊該最 内排銲墊；且 邊最外排鲜塾係相對於該晶片之該側邊垂直對齊該次 内排銲墊。
    4·如申請專利範圍第丨項或第2項所述之封裝結構，其 中該等銲墊係構成複數銲墊組，每一該等銲墊組包括一個 該最内排鮮塾、一個該次内排銲墊、垂直對齊於該最内排 銲墊之一個次外排銲墊、以及垂直對齊於該次内排銲墊之 一個最外排銲塾。 5·如申請專 該等銲墊組之寬 Pitch )之寬度c 6 ·如申請專 裝結構係*-球格 7.如申請專 裝結構係一倒裝 8· —種陣列 上表面週邊，其 該等銲墊係 次内排銲墊、一 内排銲墊以及該 利範圍第4項所述之封裝結構，其中每一 度係相等於兩個銲墊間距（b〇nding pad 利 陣 利 晶 範圍第1項所述之封裝結構，其中該封 列（BGA )封裝結構。 範圍第1項所述之封裝結構，其中該封 片結構（Flip chip Structu re ) ° 1 干塾1曰曰曰片’包括複數銲墊位於該晶片之 徵在於： 列成至少四排，包括一最内排銲墊、一 外排鲜墊以及一最外排銲墊，其中該最 内排銲墊只包括訊號墊，且該最外排銲
    536765 _m 90125929__玍月日 條正 •一 六、申請專利範圍 墊以及該次外排銲墊只包括電源墊以及接地墊。 9 ·如申請專利範圍第8項所述之陣列型銲墊晶片，其 中： 邊最内排銲墊與該次内排銲墊係相對於該晶片之一側 邊交錯排列； 邊次外排銲塾係相對於該晶片之該側邊垂直對齊該最 内排銲墊；且 該 内排銲墊 10 中該等 該最内 最外排銲墊係相對於該晶片之該侧邊垂直對齊該 銲墊之 一個最 11 其中每 (bond 12 中該晶 Struct .如申請專利範圍第8項所述之陣列型銲墊晶片，其 銲墊係構成複數銲墊組，每—該等銲墊组包括一個 排銲j、-個該次内排銲墊、垂直對齊於該最内排 孙：二2排銲墊、以及垂直對齊於該次内排銲墊之 外排銲塾。 .-如/二專範圍第10項所述之陣列型銲墊晶片， . ,、、且之寬度係相等於兩個銲塾間距 mg pad pitch )之寬度。 .如申請專利範圍第8項所述 片係適用於一倒$曰Μ α #，^皁列型紅墊晶片，其 ure) 〇 凌日日片結構（Flip Chip 1 3 ·如申晴專利範圍第8工苜讲 平幻[BGA )封裝結構。
    0636-7180TWFl.ptc 第17頁
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