TW520495B - Semiconductor storage device and method for evaluating the same - Google Patents

Semiconductor storage device and method for evaluating the same Download PDF

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Publication number
TW520495B
TW520495B TW090116859A TW90116859A TW520495B TW 520495 B TW520495 B TW 520495B TW 090116859 A TW090116859 A TW 090116859A TW 90116859 A TW90116859 A TW 90116859A TW 520495 B TW520495 B TW 520495B
Authority
TW
Taiwan
Prior art keywords
memory
semiconductor memory
volatile
volatile semiconductor
storage device
Prior art date
Application number
TW090116859A
Other languages
English (en)
Chinese (zh)
Inventor
Masanori Uchihashi
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Application granted granted Critical
Publication of TW520495B publication Critical patent/TW520495B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
TW090116859A 2000-07-10 2001-07-10 Semiconductor storage device and method for evaluating the same TW520495B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000209122A JP2002025272A (ja) 2000-07-10 2000-07-10 半導体記憶装置およびその評価方法

Publications (1)

Publication Number Publication Date
TW520495B true TW520495B (en) 2003-02-11

Family

ID=18705581

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090116859A TW520495B (en) 2000-07-10 2001-07-10 Semiconductor storage device and method for evaluating the same

Country Status (5)

Country Link
US (1) US6529408B2 (ja)
EP (1) EP1172821A1 (ja)
JP (1) JP2002025272A (ja)
KR (1) KR100418647B1 (ja)
TW (1) TW520495B (ja)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8005740B2 (en) 2002-06-03 2011-08-23 Research Affiliates, Llc Using accounting data based indexing to create a portfolio of financial objects
US7747502B2 (en) 2002-06-03 2010-06-29 Research Affiliates, Llc Using accounting data based indexing to create a portfolio of assets
US8374937B2 (en) 2002-04-10 2013-02-12 Research Affiliates, Llc Non-capitalization weighted indexing system, method and computer program product
US8374951B2 (en) * 2002-04-10 2013-02-12 Research Affiliates, Llc System, method, and computer program product for managing a virtual portfolio of financial objects
JP4246977B2 (ja) * 2002-08-29 2009-04-02 富士通マイクロエレクトロニクス株式会社 半導体メモリ
DE10323237B4 (de) * 2003-05-22 2015-05-21 Qimonda Ag Verfahren und Vorrichtung zur Optimierung der Funktionsweise von DRAM-Speicherelementen
US8131620B1 (en) 2004-12-01 2012-03-06 Wisdomtree Investments, Inc. Financial instrument selection and weighting system and method
KR100930411B1 (ko) * 2008-04-10 2009-12-08 주식회사 하이닉스반도체 퓨즈 정보 제어 장치, 이를 이용한 반도체 집적회로 및그의 퓨즈 정보 제어 방법
EP2408453B1 (en) 2009-03-17 2022-01-05 Nicox Ophthalmics, Inc. Ophthalmic formulations of cetirizine and methods of use
JP5529661B2 (ja) * 2010-07-23 2014-06-25 ラピスセミコンダクタ株式会社 半導体メモリ
AU2012298732A1 (en) 2011-08-23 2014-02-27 Research Affiliates, Llc Using accounting data based indexing to create a portfolio of financial objects

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06243677A (ja) * 1993-02-19 1994-09-02 Hitachi Ltd 半導体記憶装置とメモリ装置及びその品種設定方法
US5615159A (en) 1995-11-28 1997-03-25 Micron Quantum Devices, Inc. Memory system with non-volatile data storage unit and method of initializing same
US5721703A (en) 1996-04-29 1998-02-24 Micron Technology, Inc. Reprogrammable option select circuit
WO1998013828A1 (fr) 1996-09-26 1998-04-02 Mitsubishi Denki Kabushiki Kaisha Memoire a semi-conducteur du type synchrone
JP3831040B2 (ja) * 1997-01-31 2006-10-11 株式会社ルネサステクノロジ 半導体集積回路
JPH10302476A (ja) * 1997-02-26 1998-11-13 Toshiba Corp 半導体集積回路装置
KR100274602B1 (ko) 1997-11-20 2000-12-15 윤종용 동기형 메모리 장치
JP3610211B2 (ja) * 1997-12-12 2005-01-12 株式会社ルネサステクノロジ 半導体記憶装置
US6005810A (en) * 1998-08-10 1999-12-21 Integrated Silicon Solution, Inc. Byte-programmable flash memory having counters and secondary storage for disturb control during program and erase operations
JP4587500B2 (ja) * 1998-11-11 2010-11-24 ルネサスエレクトロニクス株式会社 半導体集積回路、メモリモジュール、記憶媒体、及び半導体集積回路の救済方法

Also Published As

Publication number Publication date
US6529408B2 (en) 2003-03-04
EP1172821A1 (en) 2002-01-16
JP2002025272A (ja) 2002-01-25
KR20020005999A (ko) 2002-01-18
KR100418647B1 (ko) 2004-02-11
US20020003729A1 (en) 2002-01-10

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