TW519728B - Apparatus for connecting a semiconductor die to a substrate and method therefor - Google Patents

Apparatus for connecting a semiconductor die to a substrate and method therefor Download PDF

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Publication number
TW519728B
TW519728B TW090131698A TW90131698A TW519728B TW 519728 B TW519728 B TW 519728B TW 090131698 A TW090131698 A TW 090131698A TW 90131698 A TW90131698 A TW 90131698A TW 519728 B TW519728 B TW 519728B
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Taiwan
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surface area
substrate
pad
trace
conductive
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TW090131698A
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English (en)
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Burton J Carpenter
Nhat D Vo
Christopher T Clark
William M Stone
Trent S Uehling
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Motorola Inc
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/0949—Pad close to a hole, not surrounding the hole
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    • H05K3/22—Secondary treatment of printed circuits
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    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
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Description

519728 A7
五、發明説明（ 1申請案參考 本申請案已於2000年12月21日在美國專利申請案第 09/746,976號中提出申請。 發明領域 本發明係與半導體裝置有關，特別是與接觸一半導體晶 粒與一基板的裝置及其方法有關。 發明背景 在如”覆晶（flip chip)，，的半導體製程中，在半導體晶粒的 墊（pad)區域上製造凸塊（bump)以將此晶粒連接至一封裝體 或一基板’此基板係用於連接半導體晶粒之電路與印刷電 路板。 第1圖顯示習知具有錫鉛凸塊丨6之半導體晶粒丨〇及在電 性連接削之基板2 0，有很多方法可在半導體晶粒1 〇上形成 錫鉛凸塊1 6，一般來説，首先在晶粒丨〇上形成墊丨2，接著 在墊1 2上形成銅間柱（copper stud)丨4以支撑錫鉛凸塊丨6。 在基板20上提供相對應之墊位置，並在基板2〇上形成跨越 該塾位置之銅跡線（copper trace)22，在銅跡線22所設計的 位置上定義一墊區域，在銅跡線22上形成一鎳層26可製備 此塾，並在鎳層26上形成一相對薄的金層24，在墊區域周 圍形成一防焊層（solder mask)28，當焊料（s〇ider)融熔時可 承載焊料，使得液態焊料可停留在墊區域上而不會因毛細 現象沿銅跡線被帶走；防焊層亦可控制幫助維持介於半導 體晶粒1 〇與基板2 0間最小之絕緣高度（stand〇ff height)的凸 塊形狀。 -4- 本纸張尺度適用宁國國家標準(CNS) A4規格(210><297公釐) 一" -—_ - 五 、發明說明（ 之It圖顯示第1圖在電性連接後之半導體晶㈣與基板20 I — I域爲7 %性連接半導體晶粒1 〇與基板2 0，放置半 2印粒10 ’使得當錫錯凸塊㈣解或迴焊⑽㈣時， ^的烊料會潤濕金層24以形成_電性連接。防焊層的形 ::鉛凸塊之體積與電的尺寸等均爲製作一具有最小絕 =度〈可靠電性連接重要的考慮因素，需注意金層㈣ 擴散至錫鉛凸塊中，且未顯示於第2圖中。 使用”覆晶"技術所製造的積體電路會具有上百個此類锡 錯凸塊’當積體電路上之凸塊數増加時，從成本與晶粒尺 寸觀點來看’絲凸塊連接的成本要愈低、晶粒尺寸要愈 小會愈好；然而’受限於防焊層材料能力之限制及會溶解 所需1開π尺寸的製程，必須減小防焊層的開口尺寸。 、因此’纟需要降低尺寸、間距（pi叫並具有良好可靠性 之半導體中需要錫鉛凸塊的連接。 圖式簡述 本發明係以範例説明 <，而非受限於附圖，且相同的元 件標示爲相同的參考號碼，其中： 第1圖顯示習知具有錫錯凸塊之半導體晶粒與電性連接前 之基板墊區域。 第2圖顯示在第i圖電性連接後之半導體晶粒與基板整區 域。 第3圖顯示根據本發明具有錫鉛凸塊之半導體晶粒與電性 連接命』之基板塾區域。 第4圖顯示在第3圖電性連接後之半導體晶粒與基板。 -5- 本纸張尺度制t ® ®家料(CNS) A4規格(210 X m公g--—-— 519728 A7
裝
線 519728 A7 B7 五、發明説明（4 ) —- 印刷私路板（未顯示）間的電性訊號。在某些具體實施例中 ，銅跡線可爲在墊區域下形成之貫穿孔（via)。在銅跡線5 2 所没计的位置上，定義一墊區域以與錫鉛凸塊4 6接觸並電 性連接，首先由在銅跡線52上形成一鎳層54來製備墊區域 ，接著在鎳層54上形成一金層56。需注意在所顯示之具體 實施例中，層56所使用之材料爲金；然而，在其他具體實 施例中，金可由其他抗氧化且可潤濕的金屬所取代。此外 ，層56可在芫成銅跡線52時當作移除的遮罩（爪以㈡。 金層56的金比銅跡線52的銅具有較大的，，可焊接性，，，爲 了敘述本發明，金屬的”可焊接性”，有時稱爲”潤濕性，，， 定義爲可焊接金屬相對的容易程度。_般來説，已知金比 裝 銅更易焊接，因此，當在半導體製造中使用锡㈣塊時， 金比銅具有更大的可焊接性。此外，已知銅比金更易在表 面上氧化，氧化物更降低了銅的可焊接性，因此需要使用 助焊劑（solder flux)以f助形成可靠的焊接接點。在所顯示 的具體實施例中，使用具有不同可焊接性的導電層可省略
線 防烊層的需要，此外，在銅跡線52表面上存在的氧化層更 增加了金與銅間的可焊接性之差異，氧化層可爲簡單的原 生氧^層（native oxide)，或爲在銅跡線52表面上沉積或成 長的氧化層，因此，焊料較不易潤濕具有氧化物的銅表面 ，因而有效地形成-抑制焊料因毛細,見象而沿跡線 走的壩（dam)。 ^ 藉由省略使用防焊層，可使用較小的焊料墊，亦可以浐 小的間距形成較小的塾。此外，較小的間距可允許更^ -7- 519728
的跡線跨過基板。在所顯示之具體實施例中，錫鉛凸塊的 直彼約50 μπι，相鄰兩跡線間之間距約1〇〇 μιη，其中，，間距 ’’定義爲兩實質平行之跡線中心的距離。與第1圖及第2圖 之先前技藝比較之，省略防焊層亦可在半導體晶片4〇與基 板5 0間幫助維持較大的絕緣高度（在第4圖中標示爲，，a ”）。
裝 第4圖顯示爲第3圖的半導體晶片4〇與基板5〇在錫鉛凸塊 融熔，或迴焊後，半導體晶片4〇與基板5〇間的電性連接。 在迴k製程中’金墊5 6擴散至錫錯凸塊中，並如一個別的 、明顯的層而消失。第4圖顯示金與銅上的氧化層間可焊接 性之差異抑制了焊料因毛細現象而被帶至銅跡線52下，因 此提供具有標示爲"A ”的適當絕緣高度之迴焊錫鉛凸塊。
線 第5圖顯示根據本發明之一具體實施例，基板5 〇部分的 俯視圖，並在銅跡線52的一端上形成金墊56。在所顯示之 具體實施例中，墊5 6—般具有方形形狀及由跡線52之寬度 定義的部分表面積，在其他具體實施例中，墊5 6的形狀可 不同。爲了説明本發明，亦只顯示一跡線5 2，在其他具體 實施例中，可實質平行跡線5 2而配置許多跡線。第5圖中 亦顯示與貫穿孔64連接之金墊62，貫穿孔64係用以提供自 基板50之一金屬層至基板50之另_金屬層的電性連接。基 板5 0可具有許多金屬層，且以類似金墊56的方法形成金墊 62。在某些具體實施例中，可在晶片貼附區域周園的基板 5 0上形成一防焊層60，在防焊層6〇 丁方銅跡線5 2則如虛 線顯示般地連續。在半導體晶片貼附至基板後，使用環= 樹脂以物理性地將晶片貼附至基板上（未顯示），環氧樹脂 -8 - 519728
發明説明（6 將覆蓋凸塊結構並提供連接強度與加強的可靠度。當將環 氧樹脂施加於基板50上時，環氧樹脂將覆蓋基板5〇上之晶 片周圍至焊料層6 0的邊緣。 弟6圖顯示爲第5圖沿銅跡線5 2中心一條線之基板部分的 截面圖’ 一半導體晶片（未顯示）將放置於基板5〇上，以將 晶片上之凸塊對準基板5 〇上相對應之墊位置，且視晶片尺 寸與晶片上凸塊的位置而定，晶片的邊緣大約介於蟄5 6與 防焊層60之間。 已於較佳具體實施例之文中敘述本發明，且熟習此項技 藝之人士需了解本發明可用數種方法修改之，並可推想其 他上述未特別指出與敘述之具體實施例。舉例來説，可使 用具有不同可焊接性之其他金屬來取代銅與金以形成跡線 及焊料墊，因此，下列之申請專利範圍包含本發明所有的 修改，且均落於本發明的實質範園中。 -9- 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐)

Claims (1)

  1. 519^28 德. 了Γ U第0糾,69㈣專利申請案 請專剎範圍修正本(91年11月） 申請專利範圍 -種内連接一半導體晶片與―印刷電路板之裝置，包含： 一基板；· ° 一導電跡線，該導電跡線係在該基板上所形成，該導 電跡線具有-第一表面積，該第一表面積具 焊接性； 一導電塾，該導電墊係在該導電跡線之第—表面積上 所形成，該導電墊具有一第二表面積，該第二表面積具 有一第二可焊接性，該第二可焊接性係大於該第一可焊 接性；且 ^ 其中可不需使用其他材料而將該半導體晶片上之一锡 鉛凸塊連接至該第二表面積，並將該焊料維持在該第二 表面積上。 2· 如申請專利範圍第η之裝置，其中該導電跡線由銅所 組成。 3. 如申請專利範圍第丨項之裝置，其中該導電墊具有—由 金所組成之層。 4. 如申請專利範圍第3項之裝置，其中該導電墊具有一在 5 該由金組成之層與該導電跡線間由鎳所組成之層。 如申請專利範圍第i項之裝置，其中相鄰於該第二表面 積的該第-表面積之原生氧化層增加了該第—表面積與 該第二表面積間的可焊接性差異，以抑制該焊料流至該 第一表面積上。 6. 一種電性連接一半導體晶片與一基板的方法，包含下列 步騾： 本纸張尺度 t國®家格(21G χ 297公爱） 在薇基板上形成一導電跡線，該導電跡線包含— 金屬； 定義該導電跡線之一表面積，並於該表面積上 導電墊；且 形成包含一第二金屬之該導電墊，該第二金屬比該第 一金屬具有較大的可焊接性； 其中當電性連接該半導體晶片與該基板的一錫鉛凸塊 融熔時，孩錫鉛凸塊將不會流至該第一金屬上。 厂如申請專利範圍第6項之方法，其中該導電跡線係以 所形成。 8·如中請專利範圍第6項之方法，其中形成料電跡線的 步驟包括形成具有包含原生氧化層之一表面的該導電跡 線，及形成包含形成金導電墊之該導電墊步驟。 9 · 一種支撐一半導體晶粒之基板，包括·· 、一銅跡線，以將一電性訊號傳輸至該半導體晶片或自 違半導體晶片傳輸該電性訊號； 一金墊，該金墊係在該銅跡線上形成，該金墊可焊 連接該基板；且 其中該銅導線之一表面比該金墊之一表面具有—相對 低的可焊接性，因而可不需使用一防焊層而融熔及迴焊 一錫鉛凸塊，並在該焊料為液態時維持該焊料。 T 10.如申請專利範圍第9項之基板_，其中該鋼跡線包括一增 加該金墊與該銅跡線間可焊接性之差異的原生氧化表^
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JP3687610B2 (ja) * 2002-01-18 2005-08-24 セイコーエプソン株式会社 半導体装置、回路基板及び電子機器
US20050056458A1 (en) * 2003-07-02 2005-03-17 Tsuyoshi Sugiura Mounting pad, package, device, and method of fabricating the device
US8574959B2 (en) * 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
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