TW506022B - Apparatus and method for plating and polishing a surface of a semiconductor workpiece, a pad assembly for plating and polishing a semiconductor workpiece, an anode assembly for plating a semiconductor workpiece - Google Patents
Apparatus and method for plating and polishing a surface of a semiconductor workpiece, a pad assembly for plating and polishing a semiconductor workpiece, an anode assembly for plating a semiconductor workpiece Download PDFInfo
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- TW506022B TW506022B TW089106166A TW89106166A TW506022B TW 506022 B TW506022 B TW 506022B TW 089106166 A TW089106166 A TW 089106166A TW 89106166 A TW89106166 A TW 89106166A TW 506022 B TW506022 B TW 506022B
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- anode
- plating
- pad
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Links
- 238000000034 method Methods 0.000 title claims abstract description 61
- 238000007747 plating Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000005498 polishing Methods 0.000 title claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 49
- 239000003792 electrolyte Substances 0.000 claims abstract description 28
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 239000000126 substance Substances 0.000 claims abstract description 10
- 230000008021 deposition Effects 0.000 claims abstract description 9
- 238000000227 grinding Methods 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 3
- 238000005192 partition Methods 0.000 claims description 3
- 239000003513 alkali Substances 0.000 claims 1
- 239000002585 base Substances 0.000 claims 1
- 230000001788 irregular Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 25
- 230000008569 process Effects 0.000 abstract description 10
- 238000012546 transfer Methods 0.000 abstract description 3
- 238000007517 polishing process Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 65
- 239000010410 layer Substances 0.000 description 40
- 238000009713 electroplating Methods 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 239000000243 solution Substances 0.000 description 8
- 239000007788 liquid Substances 0.000 description 7
- 230000002079 cooperative effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052688 Gadolinium Inorganic materials 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- UIWYJDYFSGRHKR-UHFFFAOYSA-N gadolinium atom Chemical compound [Gd] UIWYJDYFSGRHKR-UHFFFAOYSA-N 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000005065 mining Methods 0.000 description 3
- 238000000429 assembly Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910052778 Plutonium Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- -1 copper Chemical class 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 208000037265 diseases, disorders, signs and symptoms Diseases 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 235000012489 doughnuts Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- OYEHPCDNVJXUIW-UHFFFAOYSA-N plutonium atom Chemical compound [Pu] OYEHPCDNVJXUIW-UHFFFAOYSA-N 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/11—Lapping tools
- B24B37/12—Lapping plates for working plane surfaces
- B24B37/16—Lapping plates for working plane surfaces characterised by the shape of the lapping plate surface, e.g. grooved
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/001—Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/10—Electrodes, e.g. composition, counter electrode
- C25D17/14—Electrodes, e.g. composition, counter electrode for pad-plating
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/04—Electroplating with moving electrodes
- C25D5/06—Brush or pad plating
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/22—Electroplating combined with mechanical treatment during the deposition
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/60—Electroplating characterised by the structure or texture of the layers
- C25D5/615—Microstructure of the layers, e.g. mixed structure
- C25D5/617—Crystalline layers
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
- C25F7/00—Constructional parts, or assemblies thereof, of cells for electrolytic removal of material from objects; Servicing or operating
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mechanical Engineering (AREA)
- Sustainable Development (AREA)
- Life Sciences & Earth Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
本舍明係有關於一種電鍍與研磨-半導體基材上之導 電材^方法與裝置。更明確地說,本發明係有關於一種 利用單$置在半導體基材上先電鍵後研磨導電材料的方 人裝置此外本發明係有關於一種用於交替地將導電 材料用於半導體基材上且亦在不將此導電材料施用至基材 上化研磨4基材的方法與裝置。此外,本發明提供一種電 鐘"儿積及/或利用新式墊總成研磨—基材表面上之導電材 料的方法與裝置。 傳統製造積體電路與裝置的製程步驟包括利用一電鍍 裝置於一半導體晶圓上電鍍金屬層。通常,該晶圓表面在 之刖已經蝕刻且含有許多洞與溝槽。晶圓電鍍的一目的為 均勻填滿14些洞與溝槽而不產生氣洞。已知氣洞的出現會 導致不良成效及具缺陷之裝置。在經過此電鐘步驟後,一 般利用一研磨裝置進行研磨步驟以達到晶圓上之大致平坦 表面。 在晶圓表面之種基層上鍍上導電材料在半導體產業中 具有重要及廣範的應用。傳統上,電鍍鋁及其他金屬以做 為形成一半導體晶片中多層金屬層的一層。然而,最近對 於在半導體晶片上沉積銅以作為内連結線路則引起更多的 興趣’此因相較於鋁,銅可降低電阻值且可使半導體晶片 在產生更少熱的情況下運作更快,造成晶片在可容性與效 率明顯增加。此外,已知銅比起鋁為更好的導體。 在ULSI晶片製程中,將銅薄膜電鍍至次微米洞與溝槽 變得更為困難,尤其是當結構大小低於〇.25μπι而縱橫 本紙張尺度適用中國國家德唔(、,S) AM規格(210:. 197 (請先間讀背面之注意事項再填窝本頁) -訂· :線-------- 4 506022 A7
經濟部智慧財產局員工消費合作社印製 五、發明說明( 比大於5 : 1。一般係使用化學氣相沉積填滿這些蝕刻入矽 基材之洞與溝槽。不幸的是,此製程目前對111^31技術中 内連結線路的研發與整合造成相當高的花費。 因此,需要一種更為精確、有效運用成本及可靠的方 法施加一導電材料於半導體基材上。 本發明之目的為提供一種方法與裝置,用於在一半導 體物件上電鍍/沉積一導電材料並接著研磨該物件表面。 本發明之另_目的為提供一^法與裝i,其利用以刷 鍍或電化學機械沉積在一半導體^件上電鍍/沉積一導電 材料並接著利用電研磨或化學機械研磨方式研磨該物件表 面。 本發明之再另一目的為提供一種方法與裝置,其在一 用以電鍍/沉積導電材料及研磨物件表面之單一裝置中具 有多腔。 本發明之另一目的為提供具有新式墊總成用#電鍍/ 沉積導電材料與研磨物件表面的方法與裝置^ ^ 本發明之再另一目的為提供一種方法與裝置,其再墊 或其他固定結構不與該物件直接接觸的情況下電鍍/沉積 一導電材料於一物件表面上。. 這些與其他本發明之目的可藉由在一單一裝置中提供 於互為相鄰的情況下各別電鍍與研磨步驟。一第一腔可用 以自一電解液中電鍍/沉積該導電材料至物件表面上\此 藉由提供一銜接於一柱狀陽極的墊及利用沉積於該墊上或 穿過該墊的電解㈣加該導電材料至該物件上來加以達成 本紙張尺度_中國ϋ標準(CNS)A4規^咖χ挪公髮) ------I---! I 訂— ----· (請先閱讀背面之注意事項再填寫本頁) 五、發明說明(3 ) 進行此電鍍的裝置包括一陽極與陰極、一物件或一與 陽極具一距離分開之物件。一銜接於該柱狀陽極的墊繞一 第軸凝轉且該物件繞一第二軸旋轉,而來自電解液的金 屬在一電動差施加於該物件與陽極間時沉積於該物件上。 或者,該電鍍腔可包括一陽極與陰極或物件具一距離 为開。在施加電力至該陽極板及陰極時,置於電鍵腔中的 電解液用以沉積導電材料至該物件表面上。 在一研磨腔中,一墊亦銜接於另一用以研磨物件表面 的柱狀陽極或一柱狀滾筒。研磨可藉由電研磨或化學機械 研磨方法加以達成。物件表面的研磨最好可避免導電材料 在物件的某些區域累積而提供一大致平坦的表面。 本發明進一步說明新的陽極總成,其具有獨特的陽極 墊設置,其可用以電鍍及/或研磨物件表面。 圖式簡要說明 這些與其他本發明之目的及優點藉由以下本發明較佳 實施例之詳細敘述並配合所附之圖示說明會更為清楚且更 容易了解。 第1圖說明一根據本發明要填以導電物之代表性介層 洞; 第2圖說明本發明之第一較佳實施例的透視圖; 第3圖說明本發明之第一較佳實施例的截面圖; 第4圖說明本發明之第二較佳實施例的透視圖; 第5圖說明本發明之第二較佳實施例的截面 506022 •fll- 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(4 ) 第6圖說明根據本發明之較佳實施例中一第一新式陽 極總成透視圖; 第7圖說明根據本發明之較佳實施例中一第一新式陽 極總成截面圖; 第8圖說明根據本發明之較佳實施例中一第二新式陽 極總成透視圖; > 第9圖說明根據本發明之較佳實施例中一第二新式陽 _ 極總成截面圖; 第10圖說明根據本發明之較佳實施例中「接近電鍍」 之裝置與方法的截面圖; 第11圖說明一具有數層與晶粒沉積其上的基材截面圖 第12A-12B圖說明根據本發明之較佳實施例中有利地 影響導電材料構造之方法截面圖。 本發明之較佳實施例將參考以下第1-12圖加以說明。 如上所述,習知製程使用不同機台、在不同的時間在洞與 溝槽中’或在其他包括許多不同半導體晶片的半導體基材 表面上所需要之位置獲得導電材料。因此,製造高品質半 導體積體電路裝置的設備花廢可為相當高。 本發明企劃不同的實施例,其對相同的裝置均為允許 的,用以電鍍/沉積一導電材料至表面上及於接觸洞、介 層洞及溝槽内,並可研磨晶圓表面。本發明可用於任何導 電材料,特別適用於銅作為導體,且用於具有高縱橫比之 次微米結構的ULSI積體電路製造上。 --------------裝--------訂---------------線 (請先閱讀背面之注咅?事項再填寫本頁)
506022 A7 ------— B7_____ 五、發明說明(5 ) 此外,雖然半導體晶圓將用以說明本發明之較佳實施 例,其他半導體物件如平面顯示器或磁帶頭亦可根據本發 明使用。 第1圖說明-形成介層洞之晶圓2的—部份。該介層洞 ’如同半導體技藝中所熟知為—導電材料,其電性連接不 同的電路層。如第i圖所示,該介層包括一導體8其可將較 下層導電層14與較上層導電層6連接,並有一絕緣層1〇環 繞其沉積。可了解到本發明可在多層積體電路晶片的任何 金屬層上操作。 第2圖說明本發明之第一較佳實施例的透視圖而第3圖 說明其截面圖。回頭參考第孓3圖,在一介層洞、溝槽、 及/或晶圓上的其他所需部份上利用一來自第一腔1〇〇的電 解液11施用一導電材料,最好為銅,而於一第二腔200中 ,對在非預期之區域所建構成的導電材料因在晶圓上,但 不在接觸洞、介層洞及溝槽中進行電研磨或化學機械研磨 而加以消除,或至少減到最少。此第一腔1〇〇由一中央隔 板60與第二腔2〇〇分開。 該第一與第二腔1〇〇、200各包括一陽極總成12、14, 其具有一圓形或方形機械墊16、18銜接於一柱狀陽極2〇、 22,其繞一第一軸24旋轉,而一具有晶圓的晶圓頭總成% 繞一第二軸28旋轉。整個晶圓頭總成26更可沿箭頭3〇的方 向自一邊移到另一邊以使晶圓2之中央區域可經電鍍或研 磨。柱狀陽極20、22連接至柄32、34以繞軸24旋轉。如其 說明’晶圓2在由機械墊16、18所覆蓋的區域内旋轉, (請先閱讀背面之注意事項再填寫本頁}
« I I I I I I I — — — — — — — — S 經濟部智慧財產局員工消費合作社印製
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•L·-#fm_I 經濟部智慧財產局員工消費合作社印製 以下將更詳細說明,其區域位於置有電鍍液u之腔100、200 内。雖然此處顯示對單一晶圓進行操作,應可了解本發明 可使用數個晶圓頭總成26。 參考第3圖,晶圓頭總成26可包括一非導電性,最好 圓形的夾頭36,具有最好為幾毫米深的凹腔於其中央,且 此凹腔可包括一支墊(未示)。將晶圓2利用傳統的傳輸型 態或真空機制先從背面載入凹腔中抵靠支墊,以確保晶圓 2在使用中相對晶圓頭總成26固定。一非導電性固持環4〇 如〇型環或其他橡膠類密封在晶圓頭總成26及一陰極接觸 電極38的周圍,其各推向晶圓2並將晶圓2固定定位。如向 固持環40下之夾頭36推抵的整個晶圓背面可避免與任何及 所有溶液,包括電解液接觸。其他傳統晶圓頭總成可在本 發明中加以使用。 取代上述陰極接觸38的使用,電動勢可利用一環導體 施加至晶圓。此外,其他施加電動勢至晶圓的方法可用於 本發明。例如,一液態導體或一可充氣管可用於本發明。 一使用液態導體或導電管以提供根據本發明所需的電動勢 之例子揭露於一同審查中之美國專利申請案第〇9/283〇24 ,Atty· Dkt· #42496/0253036,發明名稱為「與半導體基 材形成電性接觸的方法與裝置」,同樣由本發明之讓受人 所有’其内容在此作為參考加以敘述。 根據本發明,該第一腔1〇〇可用於電鍍而第二腔200可 用於研磨。兩腔100、200可交換使用而讓第一腔1〇〇可用 於研磨且第二腔200可用於電鍵。如前所述,該第一腔
本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公复 -9 —Μ--------^· ----------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 -----— R7 ____ 五、發明說明(7 ) 包括用以電鍍之第-陽極總成12而第二腔200包括用以電 :磨之第二陽極總成14°電動勢施加至陽極20、陽極22及 晶圓2。任何已知提供電動勢至兩柱狀陽極的方法可用於 發月中如I知所熟知者,施加至兩個各別柱狀陽極 、22之電動勢量的差異決定哪—個陽極總成用於電錢而哪 一個用於電研磨。 一電解液11自兩腔10〇、200之底部開口 5〇流出至該溶 液11與墊16、18接觸為止。該電解液u進一步經由側邊開 口 50循環回通道54到達底部開口5()。該電解液听經由一 儲存槽(未示)通過一進通道(未示)先送入第一與第二腔1〇〇 ' 200 〇 於第一腔100中,介於柱狀陽極20與陰極晶圓2間的第 電動差可使電解液11中的金屬經由墊16電鑛至晶圓表面 上在第一腔20〇中,晶圓的研磨係藉由柱狀陽極2〇與陰 極晶圓2間的第二電動差而進行。 本發明之電鑛製程可利用一刷鍍法或一「電化學機械 沉積」法來實行。對於「電化學機械沉積」法更詳細的敘 述可在共同審查中的美國專利申請案第〇9/2〇1929號,發 明名稱為「電化學機械沉積之方法與裝置」,同樣由本發 明之讓受人所有,其内容在此作為參考加以敘述。 本發明之研磨製程可藉由電研磨或化學機械研磨,在 以下對其詳細說明。在操作中,應可了解滾筒狀機械盤18 以類似於滾筒沙紙從牆上移除漆料的方法研磨晶圓。 在研磨腔200中’機械墊18之大小可在一特定時間内 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 10
if. r ·-·--------訂--------.··. (請先閱讀背面之注意事項再填寫本頁) 506022 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明( 研磨晶圓之一部份。一個或更多之驅動總成(未示)意可包 括在内以旋轉柱狀陽極20、22,並因而轉動機械墊16、18 ,以便使其與需要電鍍及研磨的晶圓2之一部份接觸。機 械墊16、18最好以非導電性多孔式材料如聚乙醢胺製成。 同時,機械墊16、18最好為圓形,但可為任何形狀,只要 其可有效電鍍及/或研磨晶圓。 第4圖說明本發明之第二較佳實施例的透視圖,而第5 圖說明其截面圖。此第二較佳實施例亦藉由一用來電鑛晶 圓2之第一腔300及一用來研磨晶圓2之第二腔4〇〇來實行。 該第一腔300藉由一中央分格板/壁來與第二腔4〇〇分開。 現參考第5圖,第一腔300包括一陽極板306於腔300之 底部。任何習知將陽極板306固接至腔300底部的方法或形 狀都可使用。電解液11晶由排水通道3〇2循環至底部開口 304或經過該陽極板3〇6。 第二腔400包括一機械墊402銜接於一柱狀滾筒404以 進行晶圓2之化學機械研磨。一柄406係用以使滾筒繞軸4〇8 旋轉。CMP為一材料平坦化製程,其結合半導體層如絕 緣層或金屬層之化學移除及基材表面之機械研磨。CMP &供晶圓的全面平坦化。例如,在晶圓製程中,CMP常 用以研磨建構成多層金數内連結線路結構的表面。 在依本發明之第二較佳實施例進行操作時,此裝置利 用電源施加一負電動勢至陰極接觸電極38及一正電動勢至 陽極板/遮板306。當兩電極間建立電流時,電解液中的金 屬沉積在晶圓2的表面上。 I I I - - ----t i ! el 4 1 I J (請先閱讀背面之注意事項再填寫本頁)
506022 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(9 ) 在此沉積後,亦利用該機械墊總成412進行晶圓的化 學機械研磨。一研磨試劑或研磨液可經由研磨液通道410 施用至研磨墊402上以研磨晶圓2。將第二腔400與第一腔 300分開的中央壁420應夠高以使研磨液不會進入到第一腔 300中。其他傳統避免研磨液進入電鍍腔300的方法都可用 於本發明。機械墊總成412因機械墊402的研磨或磨擦動作 而實質避免金屬變成永久沉積於晶圓2的表面上,其中此 種沉積為非預期的。因此,金屬,如銅係沉積於介層洞、 溝槽及如其之所需處,且實質避免沉積於非預期之區域如 晶圓之表面或場區域。 晶圓頭總成26面向機械墊總成412並以一控制力向下 推。此晶圓頭總成26與參考第2及3圖中的晶圓頭總成類似 且利用傳統馬達驅動之承軸(未示)繞著軸28旋轉。此晶圓 頭總成26亦可沿箭頭30的方向從一邊移動至另一邊,以使 該晶圓2的中央區域可被電鑛及研磨。 本發明可降低對脈衝產生電源的需求,此因由墊移動 所產生的機械脈衝已形成足夠的脈衝。此機械脈衝因晶圓 與墊在其相對於晶圓移動時的接觸而產生。此機械脈衝的 益處是其可在不需要具有脈衝功能之電源下改善晶粒大小 及銅膜完整性。 應注意到本發明之範圍企劃出將本發明之第一與第二 較佳實施例中的電鍍方法與研磨方法各別相互交換。例如 ,第二較佳實施例的CMP方法可與第一較佳實施例中的 電研磨方法互換。同樣的,第一較佳實施例的電鍍方法 (請先閱讀背面之注意事項再填寫本頁) • · 訂--------
506022 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(1〇 ) 與第二較佳實施例中的電鑛方法互換。 雖然此處僅詳細敘述本發明之兩個實施例,本發明的 實施可藉由任何數量之容器使用任何電鍍與研磨方法以達 成本發明之目的。例如,本發明中可使用三個腔,其中中 央腔可用以研磨而左右兩腔可用於電錢/沉積。 第6-9圖中所述之本發明進一步說明一種間歇施加導 電材料至半導體基材上及在此種導電材料未施加至基材上 時間歇研磨該基材的方法與裝置。當間歇施加導電材料時 ’本發明施用在物件與陽極間有電位差之電流以使該導電 材料在使用電流時可施加至該物件上。此外,相反的電流 脈衝可用於物件間。 第6圖說明根據本發明之第一陽極總成的透視圖而第7 圖說明其截面圖。陽極總成500包括一獨特的陽極墊設置 對物件802進行電鍍與研磨。將數條墊5〇2連接、黏合或機 械力接合至一柱狀陽極504以使該墊502自陽極504之外表 面突出。將電力施加至該柱狀陽極504及陰極物件802。當 柱狀陽極504繞第一軸510旋轉且物件802繞一第二軸512旋 轉時,物件802在陽極504面向物件(陰極)8〇2而其間無墊 時進行電鍍,其在墊502與物件機械接觸時進行研磨。物 件802若有需要更可藉由物件頭總成(未示)如箭頭52〇所示 從一邊移至另一邊。此種獨特的電鍍與研磨係由陽極總成 5〇〇造成,此因由墊502在物件表面的刷磨而產生的機械研 磨作用,及從陽極、電解液及物件結構之金屬電鍍。 第8圖說明根據本發明之第二陽極總成的透視圖而第9 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 13 I I-------I i — — — — — — --- I---Ί (請先閱讀背面之注咅?事項再填寫本頁) 506022 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(11 ) 圖說明其截面圖。此陽極總成600亦包括一獨特的陽極塾 設置對物件802進行電鍍與研磨。陽極總成600的形狀為在 中央有一洞606得甜甜圈形或環形。將數條墊602銜接至陽 極604以使該墊602自陽極604之外表面突出。當電力施加 至該陽極604及陰極物件602’且陽極604繞第一轴610旋轉 而物件802繞一第二軸612旋轉時,物件802在陽極604面向 物件(陰極)802而其間無墊時進行電鍍,且其在墊602與物 件8 02機械接觸時進行研磨。如上所述,此種獨特的電鑛 與研磨係由陽極總成600造成’此因由整602在物件表面的 刷磨而產生的機械研磨作用。此陽極總成600的直徑或大 小 < 小於物件802的直徑或大小。 在操作第6-9圖之陽極總成時,電解液或其他溶液可 自一置於靠近陽極504、506的儲存槽(未示)導入機械墊5〇2 、602。在一特定實施例中,陽極504、604可具有一進料 通道’其包括在陽極5 04、604中央之通道及在陽極5 〇4、604 内的孔洞,其一起提供溶液一可送入陽極與陰極間空隙的 通道。或者’此電解液可經由其他根據之前所述方法的通 道直接分佈至陽極總成500、600上。 此外,如第7圖所示,電解液可儲存於環繞物件製造 的#導電性腔530中。〇型環或其他傳統結構,如之前所 述,可在此實施例中用於將溶液儲存於腔530中。 根據本發明,在任何實施例中,由於機械動作係用以 防土#預期之導體建構於晶圓非預期的區域上,因此對於 調整抑制劑的需求降低,或所需之百分比例較傳統所使用 本紙張尺度適用中國國家標準(CNS)A4規袼(210 X 297公釐) 14 -MW ” i . 4^1·· AM MW —4* ΜΜΜ MM ΜΗ * Μ··· MM I I^OJ n ϋ n n n n ϋ (請先閱讀背面之注咅?事項再填寫本頁) 506022 A7 B7 經 濟- 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明(12 的少 在另一實施例中,如第6_9圖所說明之新式總成可主 要用於電鍍/沉積導電材料至物件表面而不研磨相同表面 。此可在墊或其他固定物只用於靠近物件表面以改良電解 液之物質傳輸時達成。 例如,第10圖說明根據本發明之「接近電鑛」裝置與 方法的截面圖。第10圖說明一具有電解液置於其中的非導 電性腔700。此腔700包括具有數條墊5〇2或固定物銜接或 機械接合至陽極504上陽極總成500。在操作時,當墊束5〇2 繞軸510旋轉時且與物件802間隔一距離時(墊束5〇2未與物 件802直接接觸),物件802藉由電解液η進行電鍍。陽極5〇4 與墊束502應最好以讓電解液U連續且可施加/喷濺至物件 的速度旋轉’並因而經由陽極總成50〇、電解液及物件(陰 極)802形成封閉電流。當一縫隙8〇〇為約〇-5釐米且含電解 液之溶液凸面時,產生非常高的質量傳輸而因而沉積高品 質金屬膜至物件表面上。此外,取決於連接至柱狀電極5〇4 的塾或固定物之種類、形狀及結構,縫隙8〇〇可大於5釐米 此處所述之實施例中,塾或固定物的硬度與塾對物件 之相對移動速度配合。最好的塾應為具有多孔且堅硬以具 有最佳功效。 本發明可降低對脈衝產生電源的需求,此因由墊移動 所產生的機械脈衝已形成足夠的脈衝。此機械脈衝因晶圓 與塾在其相對於晶圓移動時的接觸而產生。此機械脈衝的 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 15 · ^ i I I I---J----- I ----^ (請先閱讀背面之注意事項再填寫本頁) ^[)22
經濟部智慧財產局員工消費合作社印製 五、發明說明(13 ) 益處是其可在不需要具有脈衝功能之電源下改善晶粒大小 及銅膜完整性。 現在利用第11圖與第12A-12B圖敘述本發明之改良實 施例。本發明已定位為亦可有利的影響利用電鍍製程施加 之導電材料的品質。第11圖說明傳統基材900,其具有一 阻障層902及一種基層904沉積其上。如其所示,該種基層 904由各別之晶粒形成,其以預定之方向排列,如<m> 晶格方向。在經過傳統電鐘製程後,於其上形成導電電鑛 層908的原子在一段時間後會聚集形成晶粒910,此晶粒910 維持原有其下之種基層904晶格方向。因此,若種基層904 具有<111>的晶格方向,則導電電鑛層908也會有相同的 方向。 相反的,本發明發現到藉由電鍍與研磨,如上所述, 研磨會改變所施加之導電電鍍層的晶格方向成為更隨機紊 亂。如第12A圖所示,在對電鍍層958中的第一層958A原 子進行研磨時,研磨器,如前述墊402,研磨此第一層原 子且改變此第一層中的垂吊鍵。因此,如第12β所示,下 一層施加其上的原子不會以如同第一層原子所形成的方式 形成。經決定此研磨動作造成原子在一段時間後會形成原 子自然堆疊之晶粒而傾向產生與其原應有的結構不同之結 構。通常,此結構顯示其會更趨紊亂。如第12B圖中所述 之晶粒960即為其結果。因此,電鍍層958不會有與種基層 相同的晶袼方向。 當此製程不斷重覆,且持績電鍍及所施加之晶粒經研 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 16 (請先閱讀背面之注意事項再填寫本頁) #· 訂-------- ·· 經濟部智慧財產局員工消費合作社印製 506022 A7 、______ B7 五、發明說明(Μ ) 磨,此舉會導致電鍍層968在其晶粒程度上有更大的紊敗 度而因此電鑛層具有更均勻的特性。 經決定施加在種基層904上的前幾層原子可經研磨, 且此會有效改變所產生的晶粒分佈。亦可持續研磨經由電 鍍製程施加的原子,因而持績增加此效果。 雖然本發明僅對上述實施例詳細說明,熟此技藝者應 > 可輕易了解在不偏離本發明之新穎性教示及優點下所做之 丨 實施例修改均屬本發明之範疇。 元件標號對照 2…晶圓 36…炎頭 8…導體 38…陰極 4、6…導電層 40…固持環 10…絕緣層 50…開口 lL···電解液 11…溶液 12、14…陽極總成 54…通道 16、18…機械墊 60…隔板 2 0、2 2…陽極 100…第一腔 24··· % 一 轴 200···第二腔 26…晶圓頭總成 300…第一腔 28…第二軸 306…陽極板 30…箭頭 302…通道 3 2、3 4…柄 304…開口 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -17 - I------------· I----II --— III (請先閱讀背面之注意事項再填寫本頁) 506022 A7 B7 發明說明(I5 ) 400…第二腔 610…轴 402…機械墊 602…塾 404…滾筒 604…陽極 4 0 6…柄 700…腔 408…軸 800…縫隙 412…機械墊總成 802…物件 410…通道 900…基材 500…陽極總成 902…阻障層 502…墊 904…種基層 504…陽極 908…導電電鍍層 506…陽極 910…晶粒 510…軸 958…電鍍層 512…軸 9 6 0…晶粒 530···腔 600…陽極總成 968…電鑛層 ίί!!·.·------- 丨tr------— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 18
Claims (1)
- 506022- Α*· ν i^4 *y*/ Α» Β8 C8 D8申請專利範園 第0891G6166號專利巾請案巾請專利範圍修正本 (請先閲讀背面之注意事項再填寫本頁) 修正日期:91年8月 1.種用以錢覆及研磨半導體物件的表面的裝置,其包括 第腔,其具有一用以鐘覆物件表面的鍵覆 裝置; 一第二腔,其具有一用以研磨物件表面的研磨裝 置;以及 一隔板,其將該第一腔與該第二腔分隔。 2·如申請專利範圍第1項之裝置,其中該鍍覆裝置包括一 墊銜接於一柱狀陽極上。 3·如申請專利範圍第2項之裝置,其中該柱狀陽極可繞一 第一軸旋轉。 4·如申請專利範圍第1項之裝置,其中該鍍覆裝置包括一 陽極板銜接於鄰近該第一腔之底面處。 - 5. 如申請專利範圍第1項之裝置,其中該研磨裝置‘括一 墊銜接於一柱狀陽極上。 6. 如申請專利範圍第5項之裝置,其中該柱狀陽極可繞一 第一軸旋轉。 7·如申請專利範圍第1項之裝置,其中該研磨裝置包括一 化學機械研磨裝置。 8·如申請專利範圍第7項之裝置,其中該化學機械研磨裝 置包括一墊銜接於一柱狀滾筒上。 9·如申請專利範圍第8項之裝置,其中該柱狀滾筒可繞一省 Α8 Β8 C8 D8 、申請專利範圍 第一軸旋轉。 10·如申請專利範圍第1項之裝置,其更包括一電解液置於 該第一與第二腔中。 u·如申請專利範圍第丨項之裝置,其更包括一物件支撐, 其可在鍍覆及研磨時支持物件,其中該物件支撐可繞 一第二軸及可從一邊移至另一邊。 12·如申請專利範圍第丨項之裝置,其中該物件包括一晶圓 、一平面顯示器及一磁帶頭。 13· —種用以鍍覆及研磨半導體物件的表面的方法,該方 法包括以下步驟: 利用一置於物件表面上的電解液鍍覆一導電材 料至一半導體物件表面上,該物件置於鄰近一陽極處 (請先閲讀背面之注意事項再填窝本頁) 、可| 次 在不進行錢覆時研磨該物件表面達至少特定 幾 如申請專利範圍第13項的方法,其中該鍍覆步碱係於 一第一腔中進行而該研磨步驟係於一第二腔中進行。 15. 如申請專利範圍第14項的方法,其中該第一腔與該第 一腔以一隔板隔開。 16. 如申請專利範圍第13項的方法,其中該錄覆步驟係利 用刷鍍與電化學機械沉積中之一方法進行。 17·如申請專利範圍.第13項的方法,其中該研磨步驟係利 用電研磨與化學機械研磨中之一方法進行。 W如申請專利範圍第13.項的方法,其中該鐘覆步驟係在 A4規格(210 X 297公釐) ;線· 本紙張尺度適财國國家標準(CNS) 20 A8 B8 C8 D8 申請專利範圍 研磨步驟前進行。 19·如申請專利範圍第13項的方法,其中該物件包括一晶 圓、一平面顯示器及一磁帶頭。 2〇· —種用於鍍覆與研磨一半導體物件之墊總成,包括: 一具有外表面之柱狀陽極;及 數條塾束銜接於該柱狀陽極以使該數條塾束自 该柱狀陽極的外表面凸出。 21·如申請專利範圍第2〇項之墊總成,其中該柱狀陽極可 繞一第一軸旋轉。 22·如申請專利範圍第2〇項之墊總成,其中該鍍覆在墊束 不與該物件接觸下進行,且研磨係在該墊束與該物件 接觸下進行。 23·如申請專利範圍第2〇項的墊總成,其中該物件包括一 平面顯示器及一磁帶頭 •種用於鍍覆與研磨一半導體物件之墊總成,包括·· 一具有上表面之環形或甜甜圈形陽極;及 數條墊束銜接於該陽極之上表面以使該數條墊 束自該陽極的上表面凸出。 25·如申凊專利範圍第24項之墊總成,其中該陽極可繞一 第一軸旋轉。 26.如申請專利範圍第24項之墊總成,其中該鍍覆在墊束 不與該物件接觸.下進行,且研磨係在該墊束與談物件 接觸下進行。 27·如申請專利範圍第24項之墊總成,其中該物件包括一 (請先¾讀背面之注意事項再填窝本頁)圓 曰曰 24. 本紙張尺度適用中國國家標準(⑽)M規格(2獻297公董) 218 8 8 8 A BCD 晶圓、一平面顯示器及一磁帶頭。 28.—種自電解液沉積一導電材料至一物件之預定區域的 方法,包括以下步驟·· 一 利用一置於物件表面上的電解液間歇施加一導 電材料至一半導體物件表.面上,該物件置於鄰近一 極處; 在不進行間歇施加時研磨該物件表面達至少特 定幾次。 29·如申請專利範圍第28項的方法,其中該物件包括一晶 圓、一平面顯示器及一磁帶頭。 3〇.-種用於鐘覆-半導體物件之陽極總《,包括: 一具有外表面之陽極;及 數條墊束或固定物銜接於該陽極上以使該數條 墊束自該陽極的外表面凸出。 31·如申請專利範圍第3〇項之陽極總成,其中該陽極可繞 一第一軸旋轉。 士申明專利範圍第30項之陽極總成,其中該錢覆在該 塾束或固定物不與該物件接觸下進行。 33.如申請專利範圍第32項的陽極總成,其中該塾束或固 定物距離該物件〇-5釐米内。 34· —種自電解液鍍覆一導電材料至一物件表面的方法, 包括以下步驟:. 連續施加該電解液於該物件表面上,該電解液 利用繞一第一軸旋轉之陽極在該陽極與該物件間產生 本紙張尺度適用中國國豕標準(CNS) A4規格(210X297公發)•訂· :線丨 (請先閲讀背面之注意事^再填寫本頁) 22 申請專利範圍 35· 36. 一封閉電流時施加至該表面上;及 提供一電動勢於該陽極與該物件間。 如申請專㈣圍第34項的方法,纟中該陽極包 有數條墊束或固定物附接其上之外表面。 括,、 2請專利範圍第35項的.方法,其中該連續施加步驟 更〇括利用數條塾東或固定㈣__靠近表面之 37.如f请專利範圍第35項的方法,其中該數條塾束或固 定物十分鄰近該物件之表面。 38· -種自電解液沉積-導電材料至一具有種基層沉積其 上的物件預定區域之方法,包括以下步驟·· 利用一置於物件表面上的電解液施加該導電材 料至該物件之種基層上,該物件置於鄰近一陽極處; 在進行施加時研磨該物件表面達至少特定幾次 ,以改變所施加之導電材料的材質。 39.如申請專利範圍第38項之方法,其中所施加之導電材 料的材質變得更為不規則。 本紙張尺度適用中國國家標準(q^S) A4規格(21〇X297公釐) 23
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CN1268470C (zh) | 2006-08-09 |
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KR100778131B1 (ko) | 2007-11-21 |
ATE281277T1 (de) | 2004-11-15 |
AU3929200A (en) | 2000-10-23 |
CN1351531A (zh) | 2002-05-29 |
EP1169162B1 (en) | 2004-11-03 |
JP2002541655A (ja) | 2002-12-03 |
US6328872B1 (en) | 2001-12-11 |
WO2000059682A1 (en) | 2000-10-12 |
US20020011417A1 (en) | 2002-01-31 |
DE60015513D1 (de) | 2004-12-09 |
EP1169162A1 (en) | 2002-01-09 |
US20050034976A1 (en) | 2005-02-17 |
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