TW471077B - Bump forming method, bump forming bonding tool, semiconductor wafer, semiconductor chip, semiconductor device, manufacture thereof, circuit board and electronic machine - Google Patents
Bump forming method, bump forming bonding tool, semiconductor wafer, semiconductor chip, semiconductor device, manufacture thereof, circuit board and electronic machine Download PDFInfo
- Publication number
- TW471077B TW471077B TW088118161A TW88118161A TW471077B TW 471077 B TW471077 B TW 471077B TW 088118161 A TW088118161 A TW 088118161A TW 88118161 A TW88118161 A TW 88118161A TW 471077 B TW471077 B TW 471077B
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- Prior art keywords
- end portion
- electrodes
- electrode
- protruding electrode
- lead
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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Description
471077 A7 B7 五、發明說明(1 ) 本發明之領域 本發明係有關於突起電極形成方法及突起電極形成用 接合工具’半導體晶圓,半導體晶片及半導體裝置以及此 1之製造方法,電路基板以及電子機器。 相關技術之說明 應用線接合技術’在半導體元件的電極形成突起電極 的方法爲周知的。例如記載於日本開昭第5 7 -1 6 3 9 1 9號公報,使用毛細管’在電極接合金屬線, 拉斷金屬線,並在電極殘留下金屬線的殘片,將此作爲突 起電極的方法。按此方法,即可較堆積電鍍更快的形成突 起電極。 但拉斷金屬線所形成的突起電極,並無法保證會有平 1控.端..面..,因此當半導體元件被接合在基板時是不會有 問題的,但在突起電極接引線時,接合精度差就會有問、,題 ^-----------... 、 。亦即,突起電極的上端面爲山狀,或者即使有、、平坦的區 域也只是小面積,因此與引線的接合面積不夠,、丨線會從
V™ H 突起電極脫落開。 本發明係爲解決此問題點之發明,其目的在於提供一 能容易的形成保證有廣大接合區域的突起電極之突起電極 形成方法及突起電極形成用接合工具,半導體晶圓,半導 體晶片及半導體裝置以及此等之製造方法,電路基板以及 電子機器。 (1 )有關本發明之突起電極形成方法,係包括:將 (請先閱讀背面之注意事項寫本頁) 寫士 訂---------線私 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -4- 經濟部智慧財產局員工消費合作社印製 471077 A7 --- B7 五、發明說明(2 ) 具有形成球狀的前端部的導電線的前述前端部’利用第1 工具接合在電極的同時,在導出前述前端部的前述導電線 的中央部周圍,將避開外周端部的部分’利用前述第1工 ’具來推壓並塑性變形之第1工程、和 將前述前端部殘留在前述電極並切斷前述導電線之第 2工程、和 將前述前端部的至少前述中央部,利用第2工具來推 壓並塑性變形之第3工程。 按本發明,使用前端部形成球狀的導電線,且令其前 端部接合在電極,並推壓那部分使之塑性變形。推壓的部 分係在球狀的前端部的中央部周圍,並避開外周端部的部 分。因而,塑性變形後的前端部,可在中央部周圍形成凹 部,但因外周端部不會被推壓,故不會被壓碎。然後,切 斷導電線,殘留塑性變形的前端部,且進一步的推壓前端 部的至少中央部,使之塑性變形。其結果,前端部的中央 部會被壓碎而擴大,多半情形爲平整的。按此所形成.的突 y 起電極,在第1工程,球狀的前端部的外周端部不會被壓 碎,所以外周端部的上面也能利用作爲接合區域。如此一 來,按本發明,即可簡單的形成保證有廣乏接合區域的突 起電極。 (2 )有關本發明之半導體晶圓之製造方法,係包括 :在形成集體電路與複數個電極之後,將具有形成球狀的 前端部的導電線之前述前端部,利用第1工具,接$在前 述複數個電極的任一電極之同時,在導出前述前端部的導 (請先閱讀背面之注意事項本頁) 訂/--------線; 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -5- 471077 A7 _ B7 五、發明說明(3 ) 電線的中央部周圍,並避開外周端部的部分,利用前述第 1工具來推壓,使之塑性變形之第1工程、和 將前述前端部殘留在前述電極,並切斷前述導電線之 •第2工程、和 將前述前端部的至少前述中央部,利用第2工具來推 壓,使之塑性變形,形成突起電極之第3工程。 按本發明,使用前端部形成球狀的導電線,且令其前 端部接合在電極,並推壓那部分使之塑性變形。推壓的部 分係在球狀的前端部的中央部周圍,並避開外周端部的部 分。因而,塑性變形後的前端部,可在中央部周圍形成凹 部,但因外周端部不會被推壓,故不會被壓碎。然後,切 斷導電線,殘留塑性變形的前端部,且進一步的推壓前端 部的至少中央部,使之塑性變形。其結果,前端部的中央 .部會被壓碎而擴大,多半情形爲平整的。按此所形成的突 起電極,在第1工程,球狀的前端部的外周端部不會被壓 碎,所以外周端部的上面也能利用作爲接合區域。如此一 來,按本發明,即可簡單的形成保證有廣乏接合區域的突 起電極之半導體晶圓。 (3 )於此半導體晶圓之製造方法中, 在前述第3工程前,重覆前述第1工程及第2工程’ 並在每個複數電極殘留前述導電線的前端部, 前述第3工程係同時的推壓殘留在複數電極的前述導 電線的前端部,並同時的形成前述複數個電極上的突起電 極亦可。 (請先閱讀背面之注意事項 -------訂.'-----III 寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -6 - 471077 Α7 Β7 五、發明說明(4 ) 按此,即可同時的形成複數個突起電極,因此能縮短 其工程。 (4 )有關本發明之半導體晶片之製造方法,將形成 .集體電路與複數個電極的半導體晶圓’一片片切斷成具有 前述複數個電極中的一群電極之後,將具有形成球狀的前 端部的導電線的前述前端部,利用第1工具,接合在前述 一群電極的任一電極之同時’在導出前述前端部的前述導 電線的中央部周圍,並避開外周端部的部分,利用前述第 1工具來推壓使之塑性變形之第1工程、和 將前述前端部殘留在前述電極,並切斷前述導電線之 第2工程、和 將前述前端部的至少前述中央部,利用第2工具來推 壓,並使之塑性變形,形成突起電極之第3工程。‘ 按本發明,使用前端部形成球狀的導電線,且令其前 端部接合在電極,並推壓那部分使之塑性變形。推壓的部 分係在球狀的前端部的中央部周圍,並避開外周端部的部 分。因而,塑性變形後的前端部,可在中央部周圍形成凹 部,但因外周端部不會被推壓,故不會被壓碎。然後,切 斷導電線,殘留塑性變形的前端部,且進一步的推壓前端 部的至少中央部,使之塑性變形。其結果,前端部的中央 部會被壓碎而擴大,多半情形爲平整的。按此所形成的突 起電極,在第1工程,蜜ϋ的前端部的外周端部不會被壓 碎,所以!周端部的上面也能利用作爲接合區域。如此一 來,按本發明,即可簡單的形成保證有廣乏接合區域的突 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項寫本頁)
—訂---------線 經濟部智慧財產局員工消費合作社印製 471077 A7 B7 五、發明說明(5 ) 起電極之半導體晶片。 (5 )於此半導體晶片之製造方法中, 於前述第3工程前,重覆前述第1工程及第2工程, •並在每個複數電極殘留前述導電線的前端部, 前述第3工程係同時的推壓殘留在複數電極的前述導 電線的前端部,並同時的形成前述複數個電極上的突起電 極亦可。 按此,即可同時的形成複數個突起電極,因此能縮短 其工程。 (6 )有關本發明之半導體晶片之製造方法,將形成 集體電路與複數個電極的半導體晶圓,一片片切斷成具有 前述複數個電極中的一群電極之後,將具有形成球狀的^ 端部的導電線的前述前端部,利用第1工具,接合在前述 一群電極的任一電極之同時,在導出前述前端部的前述_ 電線的中央部周圍,並避開外周端部的部分,利用前述胃 1工具來推壓使之塑性變形之第1工程、和 將前述前端部殘留在前述電極,並切斷前述導電線2 第2工程、和 將前述前端部的至少前述中央部,利用第2工具來推 壓,並使之塑性變形,形成突起電極之第3工程、和 接合前述突起電極與引線之第4工程。 按本發明,使用前端部形成球狀的導電線,且令其前 端部接合在電極,並推壓那部分使之塑性變形。推壓的音15 分係在球狀的前端部的中央部周圍,並避開外周端部的音15 (請^閱讀背面之注意事項 寫. I 1 丨丨·--訂----------, ,寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -8- 經濟部智慧財產局員工消費合作社印製 471077 A7 B7 五、發明說明(6 ) 分。因而,塑性變形後的前端部,可在中央部周圍形成凹 部,但因外周端部不會被推壓,故不會被壓碎。然後,切 斷導電線,殘留塑性變形的前端部,且進一步的推壓前端 •部的至少中央部,使之塑性變形。其結果,前端部的中央 部會被壓碎而擴大,多半情形爲平整的。按此所形成的突 起電極,在第1工程,球狀的前端部的外周端部不會被壓 碎,所以外周端部的上面也能利用作爲接合區域。亦即, 可簡單的形成保證有廣乏接合區域的突起電極。並可在此 突起電極接合引線,並得到半導體裝置。 (7 )於此半導體晶片之製造方法中, 於前述第3工程前,重覆前述第1工程及第2工程, 並在每個複數電極殘留前述導電線的前端部, 前述第3工程係同時的推壓殘留在複數電極的前述導 電線的前端部,並同時的形成前述複數個電極上的突起電 極亦可° 按此’即可同時的形成複數個突起電極,因此能縮短 其工程。 (8)於此半導體裝置之製造方法中, 前述引線係突出的形成在形成於基板的開口部的內側 在前述第4工程,前述突起電極係被配置在前述開口 部內,在前述開口部內,將前述引線接合在前述突起電極 亦可。 (9 )於此半導體裝置之製造方法中, 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -9 - (請先閱讀背面之注意事項寫本頁) β
----訂----------線I 471077 A7 ___ B7 五、發明說明(7 ) 前述引線係形成在基板上, 在前述第4工程,使前述引線的前述基板上的部分相 對於前述突起電極,並將前述半導體元件做面朝下接合亦 •可° (1 〇 )於此半導體裝置之製造方法中, 在前述第4工程,透過在接著劑分散導電粒子的各向 異性導電材料,來接合前述突起電極與前述引線亦可。 (1 1 )有關本發明之突起電極形成用接合工具,係 形成插通具有形成球狀的前端部的導電線的孔,在前述孔 的周圍具有推壓前述導電線的前端部的推壓部.,前述推壓 部係做成避開前述前端部的外周端部的形狀。 按本發明,將前端部形成球狀的導電線插通到孔,且 利用推壓部來推壓前端部。推壓的部分係在插通導電線的 孔之周圍,並避開導電線的前端部的部分。推壓此部分, 不壓碎球狀的前端部的外周端部,即可使之塑性變形。然 後,切斷導電線,殘留塑性變形的前端部,且進一步的推 壓前端部的至少中央部,使之塑性變形,並壓碎前端部的 中央部,外周端部的上面也能形成利用作爲接合區域的突 起電極。如此一來,按本發明,即可簡單的形成保證有廣 乏接合區域的突起電極。 (1 2 )有關本發明之半導體晶圓,係具有:集體電 路、和複數個電極、和形成在每個電極上之突起電極’ 於前述突起電極的上面,是在中央部與外周端部之間 形成溝,前述中央部與外周端部的高度約相等。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -1 〇 _ (請先閱讀背面之注意事項寫本頁) 寫士 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 471077 A7 B7 五、發明說明(8) 按本發明,在突起電極的中央部的外側形成溝,但溝 外側的外周端部則略與中央部等高。因而,突起電極的上 面的整體爲接合區域,以確保廣大的接合區域。 , (1 3 )有關本發明之半導體晶片,係具有:集體電 路、和複數個電極、和形成在每個前述電極上之突起電極 於前述突起電極的上面,是在中央部與外周端部之間 形成溝,前述中央部與外周端部的高度約相等。 按本發明,在突起電極的中央部的外側形成溝,但溝 外側的外周端部則略與中央部等高。因而,突起電極的上 面的整體爲接合區域,以確保廣大的接合區域。 (1 4 )有關本發明之半導體裝置,係包括:具有複 數電極之半導體元件、和 設在每個電極,且於上面的中央部與外周端部之間形 成溝,前述中央部與外周端部的高度約相等之突起電極、 和 接合在前述突起電極之引線、和. 形成前述引線之基板。 按本發明,在突起電極的中央部的外側形成溝,但溝 外側的外周端部則略與中央部等高。因而,突起電極的上 面的整體爲接合區域,以確保廣大的接合區域,故可與引 線做良好的接合。 (15)於此半導體裝置中, 於前述基板形成開口部, 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) _ 11 _ (請先閱讀背面之注意事項HI寫本頁) i n —i HI n n n n · 471077 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(9 ) 前述引線係突出的形成在形成於前述基板的前述開口 部的內側, 前述突起電極與前述引線被接合在前述開口部內亦可 , 〇 (16) 於此半導體裝置中, 前述引線係形成在基板, 在前述第4工程,使前述引線的前述基板上的部分相 對於_述突起電極,並令前述半導體元件做面朝下接合亦 可。 (17) 於此半導體裝置中, 則述突起電極與即述引線係透過在接著劑分散導電粒 子的各向異性導電材料來接合亦可。 (1 8 )於有關本發明之電路基板,係實裝有上述半 導體裝置。 (1 9 )有關本發明之電子機器,係具有上述半導體 裝置。 〔最佳具體例之詳細說明〕 以下,參照圖面來說明本發明之實施形態。 (第1實施形態) 本實施形態係使用有關本發明之突起電極形成用接合 工具,在半導體元件(半導體晶片)形成突起電極,製造 有關本發明之半導體晶片,且用此半導體晶片來製造半導 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -12- I I n I— n n^δ、 ϋ ϋ n n n (請先閱讀背面之注意事項ml寫本頁)
471077 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(10) 體裝置。 有關本發明之半導體裝置之製造方法中,不顧引線與 突起電極的接合方法。作爲接合方法例如試舉包括T A B • ( Tape Automated Bonding ) '倒裝接合之面朝下接合、使 用各向異性導電材料之接合等。而有關本發明之半導體裝 置之封裝形態,也適用包括T — B G A ( Tape Ball Grid Array )之 B GA ( Ball GridArray )、包括 T — C S P ( Tape Chip Size/Scale Package )之 C S P ( Chip Size/Scale Package) ’ 或是包括 C〇F ( ChipOnFilm)及 COG ( Chip 〇n Glass )之 T C P ( Tape Carrier Package )等之任 —'手审 。 第1圖至第7圖係說明適用本發明之第1實施形態圖 。有關本實施形態之半導體裝置之製造方法,係適用 T A B技術。且製造適用T — B GA封裝之半導體裝置。 第1圖至第4圖係表示於半導體元件的電極形成突起 電極之工程圖。此工程係有關本發明之突起電極形成方法 之實施形態,有關本發明之半導體晶片之製造方法之實施 形態’有關本發明之半導體裝置之製造方法之一部分實施 形態。 首先,如第1圖所示’準備形成一個或複數個電極 1 2之半導體元件(半導體晶片)1 〇。各電極1 2例如 半多以鋁等在半導體元件1 0的能動元件之形成面形成薄 平狀,但只要做成突起電極的形狀,就不特別的加以限制 側面或縱斷面的形狀,可成爲與半導體元件1 〇的面等齊 (蝽先閱讀背面之注意事項 寫本頁)
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本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -13- 經濟部智慧財產局員工消費合作社印製 471077 Α7 __ Β7 五、發明說明(11 ) 。而電極1 2的平面形狀也不特別的加以限制’可爲圓形 或矩形。再者,半導體元件1 0可切斷而得到形成集體電 路及複數個電極1 2的半導體晶圓。 _ 於形成此種半導體元件1 0的電極1 2的面,配置第 1工具(突起電極形成用接合工具)2 0。工具2 0係具 有插通金屬線等的導電線1 6之孔2 2。孔2 2爲導管孔 ,可引導導電線1 6。導電線1 6多半爲金、銅或銘等戶斤 構成的,但只要是導電性材料就不特別加以限定。導電線 1 6的前端部1 4爲工具2 0的前端部的外側,並形成球 狀。球狀的前端部1 4只要是塊狀就不管其形狀。前端部 1 4係例如因電子火花而進行高電壓放電所形成的。 、ΐ具2 0係構成以孔2 2作爲開口的端部之推壓部 2 4,但爲推壓導電線1 6的前端部1 4。推壓部2 4爲 工具2 0的前端部。孔2 2也可在推壓部2 4的中央部做 開口。形成在推壓部2 4的孔2 2 ,其開口徑可較除此以 外的部分的直徑大。亦即,也可在推壓部2 4形成錐狀的 孔2 3。錐狀的孔2 3係向著導出前端部1 4的導電線 1 6的中央部1 3而做開口。因而,推壓部2 4是位於前 端部1 4中央部1 3的周圍部分的上方。而推壓部2 4的 外形例如可做成圓錐台形狀。此圓錐台的上面爲推壓部 2 4的前端面。推壓部2 4的前端面是以前端部1 4的中 央部1 3爲基準’避開並推壓前端部1 4的外周端部1 5 ,將前端部1 4做成塑性變形的形狀。例如推壓部2 4的 前端面寬度或直徑W 1 ,可較導電線1 6的前端部1 4的 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -14- (請先閱讀背面之注意事項ml寫本頁)
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471077 A7 經濟部智慧財產局員工消費合作社印製 ___B7___五、發明說明(12) 寬度或直徑W 2小。或是,塑性變形的前端部1 4的外周 端部1 5只要較推壓部2 4外側寬大,推壓部2 4的前端 面的寬度或直徑W 1就可與導電線1 6的前端部1 4的寬 •度或直徑W2相同,或是超過此。 將工具2 0配置在任一個電極1 2的上方’並將前端 部1 4配置在任一個電極1 2的上方。打開夾具1 8 ,使 工具2 0下降,在電極1 2推壓前端部1 4。以一定的壓 力來推壓前端部1 4,對電極1 2進行壓固的期間,施加 超首波和熱%。 / 如此一來,如讀圖所示,導電線1 6的前端部1 4 就會接合在電極1 2。於同圖中,前端部1 4的中央部 1 3 ,係深入形成在工具2 0的推壓部2 4的孔2 3 ,並 對應此孔2 3的形狀做塑性變形。於孔2 3成爲錐狀時, 中央部1 3就會成爲圓錐台形狀。而前端部1 4的中央部 1 3與外周端部1 5之間,因用推壓部2 4推壓,而形成 溝1 7。接近溝1 7的外周端部1 5的側面,則是當推壓 部2 4成爲圓錐台的形狀時,即成爲錐狀。前端部1 4的 外周端部1 5則做塑性變形而位於溝1 7的外側。 其次,關上夾具1 8 ,來夾持導電線1 6 ,如每/β圖 所示,同時令工具2 0及夾具1 8上昇。如此一來,導電 線1 6就會被拉斷,而包括前端部1 4的部分就會殘留在 電極1 2上。在具有複數個需要形成突起電極的電極1 2 的場合,針對複數個極1 2重覆進行以上的工程即可。 其次,如第/4 A圖所示,令殘留有接合在電極1 2上 I VW I I ΗΗΗ ^ —r I tn n n n n n I ***55^、 唁 矣l (請先閱讀背面之注意事項寫本頁)
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本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -15- 471077 A7 B7 五、發明說明(彳3) 的導電線1 6的一部分(包括前端部1 4 )的半導體元件 1 〇放置在台3 0上,如第4B圖所示,利用第2工具‘ 3 2來推壓前端部1 4的至少中央部1 3。第2工具3 2 •也可具有平坦面。此場合,平坦面是推壓前端部1 4的至 少中央部1 3而使之塑性變形的。而前端部1 4的外周端 部1 5也可推壓而使之塑性變形。再者,本實施形態,是 同時推壓殘留在複數個電極1 2上的導電線1 6的前端部 1 4,但也可推壓每一個電極1 2的導電線1 6的前端部 14。 如此一來,如放大第d B圖所示,在各電極1 2形成 突起電極4 0。在突起電極4 0,於上面的中央部4 2與 外周端部4 4之間形成溝4 6。突起電極4 0係由導電線 1 6的一部分(包括前端部1 4 )所構成的。前端部1 4 的中央部1 3是利用第2工具3 2來推壓的,因此可對應 此第2工具3 2的形狀來做塑性變形。第2工具3 2具有 平坦面,在此平坦面推壓前端部1 4的中央部1 3的場合 ,突起電極4 0的中央部4 2的上面爲平坦狀。在前端部 1 4的外周端部1 5也是利用第2工具3 2的平坦面來推 壓的場合,突起電極4 0的外周端部1 5的上面也爲平坦 狀。特別是同時以第2工具3 2的平坦面來推壓前端部 1 4的中央部1 3及外周端部1 5 ,即可使突起電極4 0 的中央部4 2及外周端部4 4的高度相同。 按突起電極4 0,不光是中央部4 2的上面,就連外 周端部4 4的上面也爲接合區域,因此能確保寬大的接合 (請先閱讀背面之注意事項HI寫本頁)
--------訂---------線I 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -16- 471077 A7 _______ B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(14) 區域。 其次,如第^A圖及第5 B圖所示,將引線5 2接合 在突起電極40。亦即,如第5A圖所示,在台6 0上載 •置丰導體兀件(半導體晶片)1 0,在其上方配置形成在 基板5 0的引線5 2 ,在其上配置推壓治具6 2。再者, 台6 0及推壓治具6 2係也可使用做推壓殘留在電極丄2 上的導電線1 6的前端部1 4時所使用的台3 0及第2工 具3 2。 基板5 0係可由有機系或無機系之任何材料所形成的 ’也可由此等複合構造所形成的。作爲由有機系材料所形 成的基板5 0 ,例如試舉由聚醯亞胺樹脂製成的可撓性基 板。作爲可撓性基板可也使用以T A B技術所使用的黏貼 w。而作爲由無機系材料所形成的基板5 0,例如試舉陶 瓷基板和玻璃基板。作爲有機系及無機系材料複合構造, 例如試舉玻璃環氧基板。 基板5 0形成配線圖案5 4。配線圖案5 4係形成在 基板5 0的其中一面。而在基板5 0形成開口部(設備窗 )5 6 ,在開口部5 6的內側突出一個或複數個引線5 2 。引線5 2則被導電連接在配線圖案5 4。 此種基板5 0 ,係如第5 A圖所示,向著與半導胃% 件1 0相反側來配置引線5 2及配線圖案5 4。而_丰反 5 〇則以半導體元件1 〇的突起電極4 0位於開□ 5 6 的內側方式做配置。進而,形成在基板5 0的各個弓丨,線 5 2係位於任一個突起電極4 0上。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) _ 17 _ (請先閱讀背面之注意事項寫本頁) 寫士 —:—訂---------線一
471077 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(15) 且如第5\X圖所示’利用推壓治具6 2 ,將引線5 2 接合在突起電極4 0。詳細而言,則是利用推壓治具6 2 來彎曲引線5 2而壓固在突起電極4 〇 ,且施加超音波振 動和熱等來接合兩者。再者’若接合,利用振動和熱來溶 解構成引線5 2及突起電極4 0的材料。此例,突起電極 4 0是用金,在用銅形成引線5 2的表面塗鍚的場合,成 爲金-鍚的共晶。而本實施形態則是進行同時接合複數個 引線5 2的同步接合,但也可進行單點接合。 再者,於使用引線未突出開口部內側的構成之基板的 場合’則是透過基板讓引線被推壓至突起電極。 本實施形態則因引線5 2是位於與半導體元件1 〇相 反側,因此引線5 2會在開口部5 6的內側做彎曲。或者 ’將引線5 2配置在半導體元件1 〇這邊而進行接合時, 引線5 2可以不做彎曲。 引線5 2係如第6 p所示,在其前端爲從突起電極 4 0突出的狀態而接¥。如此一來,即使引線5 2與突起 電極4 0的位置有誤差,至少不光是突起電極4 0的中央 部4 2上面,就連引線5 2也會橫切過外周端部4 4的上 面,因此可確保寬大的引線5 2與突起電極4 0的接合面 積。 按本實施形態,將導電線1 6接合在電極1 2 ,將其 前端部1 4殘留在電極1 2並予以切斷’且推壓這裡,並 只要將上端面作爲平坦就可形成突起電極。此工程能使用 比利用電鍍來形成突起電極的工程短的時間來進行° (請先閱讀背面之注意事
寫本頁) -n n I n n n n 一 δ、1 n flu n n n n 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) -18- 471077 A7 ______ B7 五、發明說明(16 ) 其次,根據以往所進的工程,得到第7圖所示的半導 體裝置。第7零/fe示的半導體裝置,係爲適用B GA封裝 者。亦即,同圖所示的半導體裝置係具有:基扳5 〇、和 •形成在基板5 0之配線圖案5 4、和設在配線圖案5 4之 複數個外部電極7 0、和半導體元件1 〇 ,且能利用外部 電極7 0完成面實裝。 外部電極7 0係爲例如焊球,透過被導電連接在配線 圖案5 4的引線5 2 ’而被導電連接在半導體元件1 〇的 電極1 2。再者,外部電極7 0也可用焊鍚以外,例如用 銅等來形成的。而在基板5 0的配線圖案5 4的形成面, 則是避開外部電極7 0 ’來塗佈光蝕刻劑7 2。光蝕刻劑 7 2是特別以覆蓋配線圖案5 4的表面而予保護的。 在作爲基板5 0所使用可撓性基板的場合,則是在與 外部電極7 0相反側設置板狀的加強板7 4。加強板7 4 是用銅、不銹鋼和銅系合金等所形成的,並具有可維持平 面形狀的強度,且透過絕緣接著劑7 6而黏貼在基板5 0 上。再者,絕緣接著劑7 6係作成熱硬化性或熱可塑性的 薄膜而形成的。而加強板7 4,則是避開半導體元件1 〇 ,而黏貼在整個基板5 0。如此一來,基板5 0就不會有 應變、彎曲,外部電極7 0的高度成爲一定,而平面穩定 性會提升’且對電路基板的實裝良品率也提高。 進而’在與形成半導體元件1 〇的電極1 2的面之相 反面,透過銀糊等熱傳導接著劑7 8來黏固散熱板8〇。 藉此’即可提高半導體元件1 〇的散熱性。散熱板8 0係 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事 寫本頁) 經濟部智慧財產局員工消費合作社印製 -19- 471077 Α7 ___ Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明(17) 形成較半導體元件1 〇大’亦被黏固在加強板7 4上。再 者’加強板7 4與散熱板8 0之間也以熱傳導接著劑7 8 來黏固而完成氣密狀。熱傳導接著劑7 8會根據半導體元 •件1 0的散熱量’而由通常的絕緣接著劑或是上述的絕緣 薄膜來取代。 半導體元件1 0與基板5 0之間,則是利用接合的環 氧樹脂等之樹脂8 2來予以密封。而樹脂8 2也會回流到 開口部5 6及半導體元件1 0的外周。 (第2實施形態) 圖係表示有關適用本發明之第2實施形態之半導 體裝置圖。連本實施形態也是使用形成電極1 2的半導體 元件1 0,在電極1 2上形成突起電極4 0。突起電極 4 0的構成及形成方法係如第1實施形態所做的說明。 在基板1 0 0形成引線1 0 2。基板1 〇 〇的材料, 可由作爲第1實施形態的基板5 0所使用的材料來選擇。 作爲基板1 0 0,也可使用透過接著1 0 4來黏貼引線 1 0 2的3層基板。或是,引線係利用濺射等在基板被覆 銅等導電性膜,且蝕刻這裡而形成的。此場合,係直接於 基板形成引線,成爲未透過接著劑的2層基板。或是,也 適用利用電鍍形成引線的加法。或者,也可使用在基板積 層絕緣樹脂與配線圖案所構成的合成多層構造的基板、和 積層複數個基板的多層基板。 半導體元件1 0係針對基板1 〇 0而被面朝下接合或 (請先閱讀背面之注意事項寫本頁) 寫夫 —訂-----------線j
本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -20 - 經濟部智慧財產局員工消費合作社印製 471077 A7 _ B7 五、發明說明(18) 倒裝接合。亦即,使突起電極4 0接觸到引線1 0 2上, 透過圖未表示的工具,對兩者間施加熱及壓力。如此一來 ’突起電極4 0與引線1 0 2就會被金屬接合。 ' 連本實施形態也與第1實施形態相同,包括突起電極 4〇,相關於此即可達成相同效果。 (第$實施形態) \ / v第9圖係表示有關適用本發明之第3實施形態之半導 體裝置圖。連本實施形態也是使用形成電極1 2的半導體 元件1 0,在電極1 2上形成突起電極4 0。突起電極 4 0的構成及形成方法,係如第1實施形態所做的說明。 有關基板1 0 0及引線1 0 2則如第2實施形態所做的說 明。 半導體元件1 〇係透過各向異性導電材料1 1 〇 ’而 被面朝下接合或倒裝接合在基板1 0 0。各向異性導電材 料1 1 0則是讓導電粒子(導電墊片)分散在接著劑(黏 合劑),也有添加分散劑的場合。各向異性導電材料 1 1 〇也可在預先成甜甜圈狀後貼在基板1 〇 〇或半導體 元件1 0的至少一方,或是仍可成爲液狀。再者’作爲各 向異性導電材料1 1 0的接著劑,可使用熱硬化性的接著 劑。各向異性導電材料1 1 〇,至少會被設在與引線 1 0 2的突起電極4 0的接合部上。或者,以覆蓋整個基 板1 0 0的方式,只要設有各向異性導電材料1 1 0 ’就 可簡單地進行其工程。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) -21 - ---------訂----- ---- (請先閱讀背面之注意事項ns寫本頁) ft 寫太
471077 A7 ---- --B7___ 五、發明說明(19 ) 各向異性導電材料丨1 〇係在突起電極4 〇與引線 1 0 2之間被推壓的,利用導電粒子達到在兩者間的導電 連通。且使接著劑硬化,來保持導電連通。在接著劑爲熱 ‘硬化性樹脂的場合’則是加熱使之硬化。 連本實施f態也與第1實施形態相同,包括突起電極 4 0,相關於此即可達成相同效果。 (實施形態) 第1 0圖係表示有關適用本發明之第4實施形態之半 導體晶圓圖。同圖所示之半導體晶圓,係具有集體電路及 複數個電極,且在各電極上爲突起電極4 0。突起電極 4 0係如第1實施形態所做的說明,其形成方法也相同。 具有突起電極4 0的半導體晶圓則是在包括複數個電極中 的一群電極的區域而被切斷,取得複數個半導體晶片。 於第ll/圖 表示實裝有適用本發明之半導體裝置 1 1 0 0之電路基板1 0 0 0。一般是在電路基板例如使 用玻璃環氧基板等之有機系基板。於電路基板形成例如以 所期望的電路之方式形成由銅製成的配線圖案,將此等配 線圖案與半導體裝置的外部電極做機械連接,達到此等的 導電連接。 且作爲具備有此電路基板1 〇 〇 0的電子機器,則爲 第1 ^&7圖所示的筆記型電腦1 2 0 0。 再者,將上述本發明之構成要件「半導體元件」置換 爲「電子元件」,與半導體元件同樣的可在電子元件(能 本紙張尺度適用中國國i標準(CNS)A4規格(210 X 297 - 22- (請先閱讀背面之注意事項 C一 i 本頁 訂--------- 經濟部智慧財產局員工消費合作社印製 471077 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(20) 動元件則不管受動元件)的電極形成突起電極。作爲由此 種電子元件所製造的電子零件,例如有電阻器、電容器、 線圈、振盪器、過濾器、溫度感應器、熱敏電阻、可變電 •阻、電位器或保險絲等。 〔圖面之簡單說明〕 1圖係說明本發明之第1實施形態之突起電極形成 工程圖。 / 2圖係說明本發明之第1實施形態之突起電極形成工 程圖。 /. 3圖係說明本發明之第1實施形態之突起電極形成 工程圖。 \第4 A圖及第4 B圖係說明本發明之第1實施形態之 突起電極形成工程圖。 ' / 5 A圖及第5 B圖係表示本發明之第1實施形態之 引線接合工程圖。 I第6圖係表示本發明之第1實施形態之引線與突起電 極之關係圖。 \第7圖係表示有關本發明之第1實施形態之半導體裝 置圖。 8圖係表示有關應用本發明之第2實施形態之半導 體裝置圖。 9圖係表示有關應用本發明之第3實施形態之半導 體裝置圖。 (請先閱讀背面之注意事項.¾寫本頁) I*裝 •HI寫士
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本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -23- 471077 A7 B7 五、發明說明(21) # 1 0圖係表示有關應用本發明之第4實施形態之半 導體晶圓圖。 1 1圖係表示有關本發明之實施形態之電路基板圖 f 〇 2圖係表示具備有應用有關本發明之方法所製造 經濟部智慧財產局員工消費合作社印製 的半導體裝置之電子機器 〔符號之說明 ] 10 半導體元件 12 電極 13 中央部 14 前端部 15 外周_部 16 導電線 17 溝 2 0 第1工具 2 2 孔 2 4 推壓部 3 2 第2工具 4 0 突起電極 4 2 中央部 4 4 外周端部 4 6 溝 5〇 基板 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項 II裝 寫丄 ^^1 flu HI i l n-1^ ft ^1· n n n _ 4口 寫本頁) -24- 471077 A7 _B7 五、發明說明(22 ) 5 2 引線 5 4 配線圖案 5 6 開口部 (請先閱讀背面之注意事項本頁) I. 訂r--------線i 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -25-
Claims (1)
- 471077 /、、申清專利範圍 第88H8161號專利申請案 中文申請專利範圍修正本 民國90年6月修正 1 、一種突起電極形成方法,係包括:將具有形成球 狀的則端部的導電線的前述前端部,利用第1工具接合在 電極的同時’在導出前述前端部的前述導電線的中央部周 圍’並避開外周端部的部分,利用前述第1工具來推壓使 之塑性變形之第1工程、和 料前則端邰殘留在前述電極並切斷前述導電線之第 2工程、和 將前述前端部的至少前述中央部,利用第2工具來推 壓使之塑性變形之第3工程。 2、 種-卜導體晶圓之製造方法,係包括:在形成集 體電路與複數個電極之後,將具有形成球狀的前端部的導 電線之前池时端部’利用第1工具,接合在前述複數個電 極的任一電極之同時,在導出前述前端部的導電線的中央 部周圍’並避開外周端部的部分,利用前述第1工具來推 壓’使之塑性變形之第1工程、和 將前述前端部殘留在前述電極,並切斷前述導電線之 第2工程、和 將則述前端部的至少前述中央部,利用第2工鸟來推 壓,使之塑性變形,形成突起電極之第3工程。 3、 如申請專利範圍第2項所述之半導體晶圓之製造 方法’其中’在前述第3工程前,重覆前述第]工程及第 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 〇請先閱讀背面之注意事.¾填寫本頁) 裝經濟部智慧財產局員工消費合作社印制衣 471077 Λ8 R8 C8 D8 六、申請專利範圍 2工程,並在每個複數電極殘留前述導電線的前端部; 在前述第3工程同時的推壓殘留在複數電極的前述導 電線的前端部,並同時的形成前述複數個電極上的突起電 極。 4、 一種半導體晶片之製造方法,係包括:將形成集 體電路與複數個電極的半導體晶圓,一片片切斷成具有前 述複數個電極中的一群電極之後,將具有形成球狀的前端 部的導電線的前述前端部,利用第1工具,接合在前述-一 群電極的任一電極之同時,在導出前述前端部的前述導電 線的中央部周圍,並避開外周端部的部分,利用前述第1 工具來推壓使之塑性變形之第1工程、和 將前述前端部殘留在前述電極,並切斷前述導電線之 第2工程、和 將前述前端部的至少前述中央部,利用第2工具來推 壓,並使之塑性變形,形成突起電極之第3工程。 5、 如申請專利範圍第4項所述之半導體晶片之製造 方法,其中,於前述第3工程前,重覆前述第1工程及第 2工程,並在每個複數電極殘留前述導電線的前端部; 在前述第3工程同時的推壓殘留在複數電極的前述導 電線的前端部,並同時的形成前述複數個電極上的突起電 極。 6、 一種半導體裝置之製造方法,係包括:將具有形 成球狀的前端部的導電線的前述前端部,利用第1工具, 接合在前述一群電極的任一電極之同時,在導出前述前端 本E張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ΓΤΓ S丨裝 填寫本頁) 訂-------經濟部智慧財產局員工消費合作社印製六、申請專利範圍 部的則述導電線的中央部周圍,並避開外周端部的部分, 利用前述第1工具來推壓使之塑性變形之第1工程、和 (請先閱讀背面之注意事 填寫本頁) 將前述前端部殘留在前述電極,並切斷前述導電線之 第2工程 '和 將前述前端部的至少前述中央部,利用第2工具來推 Ιβ ’並使之塑性變形,形成突起電極之第3工程、和 接合前述突起電極與引線之第4工程。 了、如申請專利範圍第6項所述之半導體裝置之製造 方法’其中,於前述第3工程前,重覆前述第1工程及第 2工程,並在每個複數電極殘留前述導電線的前端部; 在前述第3工程同時的推壓殘留在複數電極的前述導 電線的前端部,並同時的形成前述複數個電極上的突起電 極。8、如申請專利範圍第6項或第7項所述之半導體裝 ®之製造方法,其中,前述引線係突出的形成在形成於基 板的開口部的內側; 在前述第4工程,前述突起電極係被配置在前述開口 經濟部智慧財產局員工消費合作社印制私 部內,在前述開口部內,將前述引線接合在前述突起電極 0 .9、如申請專利範圍第6項或第7項所述之半導體裝 置之製造方法,其中,前述引線係形成在基板上; 在前述第4工程,使前述引線的前述基板上的部分相 對於前述突起電極,並將前述半導體元件做面朝下接合。 k 0、如申請專利範圍第9項所述之半導體裝置之製 適用中國國家標準(CNS)A4規格(_210: 297公釐) ~ 471077經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 造方法,其中,在前述第4工程,透過在接著劑分散導電 粒子的各向異性導電材料’來接合前述突起電極與前述引 線。 、1 1 、一種突起電極形成用接合工具,係形成插通具 有形成球狀的前端部的導電線的孔,在前述孔的周圍具有 推壓前述導電線的前端部的推壓部,前述推壓部係做成避 開前述前端部的外周端部的形狀。 .1 2、一種半導體晶圓,係具有:集體電路、和複數 個電極、和形成在每個電極上之突起電極; 於前述突起電極的上面,是在中央部與外周端部之間 形成溝,前述中央部與外周端部的高度約相等。 、1 3、一種半導體晶片,係具有:集體電路、和複數 個電極、和形成在每個前述電極上之突起電極; 於前述突起電極的上面’是在中央部與外周端部之間 形成溝,前述中央部與外周端部的高度約相等° 1 4、一種半導體裝置,係包括:具有複數電極之半 導體元件、和 設在每個電極,且於上面的中央部與外周端部之間形 成溝,前述中央部與外周端部的高度約相等之突起電極、 和 接合在前述突起電極之引線、和 形成前述引線之基板。 1 5、如申請專利範圍第1 4項所述之半導體裝置’ 其中,於前述基板形成開口部; 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -4 - —-------1 —裝·----^—tj"-------I (請先閱讀t-面之注音填寫本頁) 471077 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 前述引線係突出的形成在形成於前述基板的前述開口 部的內側, 前述突起電極與前述引線被接合在前述開口部內。 1 6、如申請專利範圍第1 4項或第1 5項之半導體 裝置,其中,前述引線係形成在基板; 在前述第4工程,使前述引線的前述基板上的部分相 對於前述突起電極,並令前述半導體元件做面朝下接合。 1 7、如申請專利範圍第1 6項之半導體裝置,其中 ,前述突起電極與前述引線係透過在接著劑分散導電粒子 的各向異性導電材料來接合。 8、 一種電路基板,其特徵係安裝包含 具有複數之電極的半導體元件, 和設於各電極,於上面之中央部和外周端部間形成溝 ’前述中央部和外周端部之高度幾近相等之突起電極, 和於前述突起電極加以接合之導線, 和形成前述導線之基板的半導體裝置者。 9、 一種電子機器,其特徵係具有包含 具有複數之電極的半導體元件, 和設於各電極,於上面之中央部和外周端部間形成溝 ’前述中央部和外周端部之高度幾近相等之突起電極, 和於前述突起電極加以接合之導線, 和形成前述導線之基板的半導體裝置者。 (請先閱讀背面之注意事TIP:填寫本頁) 裝 訂·本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -5-
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JP10341110A JP2000150560A (ja) | 1998-11-13 | 1998-11-13 | バンプ形成方法及びバンプ形成用ボンディングツール、半導体ウエーハ、半導体チップ及び半導体装置並びにこれらの製造方法、回路基板並びに電子機器 |
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TW471077B true TW471077B (en) | 2002-01-01 |
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TW088118161A TW471077B (en) | 1998-11-13 | 1999-10-20 | Bump forming method, bump forming bonding tool, semiconductor wafer, semiconductor chip, semiconductor device, manufacture thereof, circuit board and electronic machine |
Country Status (4)
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US (2) | US6323552B1 (zh) |
JP (1) | JP2000150560A (zh) |
KR (1) | KR100501018B1 (zh) |
TW (1) | TW471077B (zh) |
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-
1998
- 1998-11-13 JP JP10341110A patent/JP2000150560A/ja active Pending
-
1999
- 1999-10-19 US US09/420,566 patent/US6323552B1/en not_active Expired - Lifetime
- 1999-10-20 TW TW088118161A patent/TW471077B/zh not_active IP Right Cessation
- 1999-11-09 KR KR10-1999-0049373A patent/KR100501018B1/ko not_active IP Right Cessation
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2001
- 2001-08-20 US US09/932,031 patent/US6689679B2/en not_active Expired - Fee Related
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JP2000150560A (ja) | 2000-05-30 |
KR20000035318A (ko) | 2000-06-26 |
US6689679B2 (en) | 2004-02-10 |
US6323552B1 (en) | 2001-11-27 |
KR100501018B1 (ko) | 2005-07-18 |
US20010053598A1 (en) | 2001-12-20 |
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