TW459245B - Clock synchronous delay control circuit - Google Patents

Clock synchronous delay control circuit Download PDF

Info

Publication number
TW459245B
TW459245B TW089102417A TW89102417A TW459245B TW 459245 B TW459245 B TW 459245B TW 089102417 A TW089102417 A TW 089102417A TW 89102417 A TW89102417 A TW 89102417A TW 459245 B TW459245 B TW 459245B
Authority
TW
Taiwan
Prior art keywords
delay
pulse
circuit
clock
output
Prior art date
Application number
TW089102417A
Other languages
English (en)
Chinese (zh)
Inventor
Koji Kato
Masahiro Kamoshida
Shigeo Ohshima
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW459245B publication Critical patent/TW459245B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
TW089102417A 1999-02-15 2000-02-14 Clock synchronous delay control circuit TW459245B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11035946A JP2000235791A (ja) 1999-02-15 1999-02-15 クロック同期遅延制御回路

Publications (1)

Publication Number Publication Date
TW459245B true TW459245B (en) 2001-10-11

Family

ID=12456167

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089102417A TW459245B (en) 1999-02-15 2000-02-14 Clock synchronous delay control circuit

Country Status (3)

Country Link
US (1) US6198690B1 (OSRAM)
JP (1) JP2000235791A (OSRAM)
TW (1) TW459245B (OSRAM)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000286386A (ja) * 1999-03-30 2000-10-13 Toshiba Corp クロック同期遅延制御回路
KR100326809B1 (ko) * 1999-04-09 2002-03-04 박종섭 딜레이 동기회로
US6323705B1 (en) * 2000-04-25 2001-11-27 Winbond Electronics Corporation Double cycle lock approach in delay lock loop circuit
KR100527402B1 (ko) * 2000-05-31 2005-11-15 주식회사 하이닉스반도체 디디알 동기식메모리의 지연고정루프 장치
JP4005779B2 (ja) * 2001-07-03 2007-11-14 株式会社東芝 クロック同期回路
JP3699920B2 (ja) * 2001-10-25 2005-09-28 株式会社東芝 遅延回路および同期型遅延装置
US6711092B1 (en) * 2002-04-30 2004-03-23 Virage Logic Corp. Semiconductor memory with multiple timing loops
US7095261B2 (en) 2004-05-05 2006-08-22 Micron Technology, Inc. Clock capture in clock synchronization circuitry
US7276946B2 (en) * 2004-07-16 2007-10-02 Micron Technology, Inc. Measure-controlled delay circuits with reduced phase error
JP2019053444A (ja) * 2017-09-13 2019-04-04 東芝メモリ株式会社 半導体集積回路及び半導体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0558079B1 (en) * 1992-02-28 1998-04-15 Sony Corporation Semiconductor memory device with address transition detector
JP2771464B2 (ja) * 1994-09-29 1998-07-02 日本電気アイシーマイコンシステム株式会社 ディジタルｐｌｌ回路
US5870445A (en) 1995-12-27 1999-02-09 Raytheon Company Frequency independent clock synchronizer
JP3410922B2 (ja) * 1996-04-23 2003-05-26 株式会社東芝 クロック制御回路
US5923613A (en) 1998-03-18 1999-07-13 Etron Technology, Inc. Latched type clock synchronizer with additional 180°-phase shift clock

Also Published As

Publication number Publication date
US6198690B1 (en) 2001-03-06
JP2000235791A (ja) 2000-08-29

Similar Documents

Publication Publication Date Title
US7404018B2 (en) Read latency control circuit
TW459245B (en) Clock synchronous delay control circuit
KR100987359B1 (ko) 데이터 입출력 회로
CN111435602A (zh) 与时钟信号同步的信号生成电路及使用其的半导体装置
US10026462B1 (en) Apparatuses and methods for providing constant DQS-DQ delay in a memory device
JPH1069326A (ja) クロック制御回路
US9325330B2 (en) Semiconductor device including a clock adjustment circuit
TW440862B (en) Reference signal generating circuit of synchronous integrated circuit memory device
TWI395220B (zh) 半導體記憶體裝置及其操作方法
US10636461B2 (en) Apparatuses and methods for providing multiphase clock signals
CN112017707A (zh) 时钟发生电路及包括其的存储器件
JP4627286B2 (ja) 半導体記憶装置及び半導体装置
US9467144B2 (en) Radiation hardened digital circuit
JP5656179B2 (ja) 複合データのレベルシフタおよびデスキュー装置
CN117769805A (zh) 老化减轻
KR100292127B1 (ko) 클록 동기 지연 제어 회로
KR101847543B1 (ko) 반도체 메모리 장치 및 그의 동작 방법
KR101747885B1 (ko) 시프트 회로
TW420905B (en) Clock monitor circuit and syncuronous semiconductor memory device using this circuit
US8520466B2 (en) Internal command generation circuit
KR100761401B1 (ko) 반도체 메모리 장치 및 그 구동 방법
JP3880206B2 (ja) 集積回路装置
JP2002300009A (ja) Ｄ型フリップフロップ回路装置
TWI900008B (zh) 訊號恢復系統以及儲存裝置
KR100949272B1 (ko) 반도체 소자와 그의 구동 방법

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees