TW449898B - Hydrogen silsesquioxane thin films for low capacitance structures in integrated circuits - Google Patents

Hydrogen silsesquioxane thin films for low capacitance structures in integrated circuits Download PDF

Info

Publication number
TW449898B
TW449898B TW086111042A TW86111042A TW449898B TW 449898 B TW449898 B TW 449898B TW 086111042 A TW086111042 A TW 086111042A TW 86111042 A TW86111042 A TW 86111042A TW 449898 B TW449898 B TW 449898B
Authority
TW
Taiwan
Prior art keywords
hsq
layer
item
patent application
scope
Prior art date
Application number
TW086111042A
Other languages
English (en)
Inventor
Shin-Pun Jeng
Kelly J Taylor
Amitava Chatterjee
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW449898B publication Critical patent/TW449898B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H01L21/3122—Layers comprising organo-silicon compounds layers comprising polysiloxane compounds
    • H01L21/3124—Layers comprising organo-silicon compounds layers comprising polysiloxane compounds layers comprising hydrogen silsesquioxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/902—Capping layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Description

44989 8 A7 B7 五、發明说明（1 ) 相關申請案的參考文獻 下列共同讓與之先前提申的申請案係與本申請案相關且併入此處 供參考。 申請案 TI案號 申請曰期 名稱 序號 08/137,658 TM8509 10/15/93 線間電容降低的平面化結構 序號 08/298,807 TI-19532 08/03/94 改善金屬接線間的連結電容 序號 08/455,765 TI-18929AA 05/31/95 一有低介電常數絕緣體的平 面化多重連結結構 序號 60/005,132 TI-20784 10/12/95 積體電路中低電容連結結構 序號60/ TI-21907 10/25/95 高熱傳導率連結結構 序號60/ TI-21909 12/04/95 使用分解聚合物低電容連結 結構的積體電路 序號 60/013,866 TI-21880 03/22/96 使用低電容材料堆積低電容 連結結構的積體電路 序號60/ TI-19738 07/30/96 絕緣層上長矽技術中使用流 動性氧化物當作填入材料的 Mesa絕緣重填過程 (請先聞讀背面之注$項再填寫本頁} 裝 .丁， 經濟部中央標準局員工消費合作社印製 .發明領域 本發明與降低積體電路之電容，例如互相靠近的互連接線或矽 溝槽絕緣相關。尤其是，相關於氫倍半氧矽烷(HSQ)薄膜固化期間的 的裂缝抑制方法來獲得不受高溫程序的影響並增加多孔性及降低HSQ 的介電常數。
-3- 本紙張从通用中國國家標率（CMS } A4跋（21GX297公釐） 4 4989 8 A7 B7 五、發明説明（2) 發明背景 積體電路漸漸地需要非常靠近的互連接線且現在需要許多層金屬 化，有七層那麼多來連結元件的不同電路。因為較近的距離會增加鄰 近線之間的電容，故當元件幾何縮小且密度增加時，鄰近線之間的電 容及干擾成為較多問題。 連結電容在金屬化中為分配量。然而，主要是兩種元件：線到基 板，或線到地端電容以及線到線電容。對於〇·25微米設計規則的超大 性積體電路，效率主要是由連結RC延遲，其線與線之間的電容為貢獻 全部電容來決定。例如，理論模型証明當寬度/間距的尺度降到0.3微 米，交互作用的電容是如此的小以至於全部電容是由線到線之間的電 容來指示，其包含比90%還多的全部連結電容。 先前技術金屬間電介質（_)一般為Si02，其介電常數大約為 4.0。最理想的情況為以較低的介電常數的材料取代此材料。如這裹所 用的，低介電常數或低k意指一材料有比3.5還低的介電常數且最好是 比3還低且更佳的情況是大約2或更低。 不幸的是，有較低介電常數的材料有其特色使其難以積體化成已 存在的積體電路結構及程序。許多聚合物材料，例如 polysilsesquioxane、二甲苯塑勝、polyimide、benzocyclobutene及非晶 矽鐵氟龍有較低的介電常數(較低介電常數）。其它較佳的材料為 Aerogel 及Xerogd，可從tetraethoxysilane (TEOS)儲存的溶液產生。 經濟部中央標準局貝工消費合作社印製 -----------策— (請先閲讀背面之注意事項再填寫本頁> 與Si〇2比較，這些較佳的低k材料一般有低的機械強度，差的尺寸不穩 定，差的溫度穩定性、高溼度吸收及滲透、差的黏著力、大的熱膨脹 係數以及一不穩定的應力位準。由於這些性質，聚合物或其它低電介 質為在積體電路過程或是結構中標準地取代Si〇2是相當有問題。 一較早申請案，藉由在此申請人，SN60/013，866(TI-21880)揭示 一積體化HSQ及其它低介電常數材料之方法及結構。此申請案揭示創 4 _±__美 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）
經濟部中央橾準局貝工消費合作社印裝 立一另一層低k村料及傳統介電質之多層介電堆積。更易碎的低k材料 可藉由在低k材料之間插入穩定層來強化。 另一先前共同讓與的申請案，SN60/(TI-19738)揭示將HSQ整合至 平頂(mesa)絕緣結構的方法及結構。 發明概要 本發明提供一稹蟫化取介電常數材料的方法，有如前所述在積 體電路結構及程序中不適當的特質，特別是那些需要多層的連接線。 本發明特別有關於改進低k薄膜例如氫倍半氧矽烷(HSQ)的機； 蜱哮度及裂縫抗力 先前曾經觀察到在HSQ中形成的裂缝可由固化溫度、固化環境、 在固化之前的設定時間及薄膜厚度等因素影響。可藉由控制這些條件 來成功地整抑這些裂缝。在此揭示的方法更可藉由先前技術的重新安' 排程序步驟來達到更強固的製程及較厚的本質上無裂缝的HSQ層。一 般説來，本發明的程序就是要在固化之前於HSQ上鍍上一層可滲透及 機械穩定的薄膜。 在較佳實施例中，連接線首先被圖形化及蝕刻。一低k材料例如氫 倍半氧矽烷(HSQ)可旋塗在晶圓表面以填滿連接線之間的區域。此 HSQ可以為比先前技術結構可獲得的還要有利的厚度。一介電性質穩 定的帽狀層例如別02可施加在HSQ之上。HSQ接著在熱烤盤上加熱來 固化。一厚的3丨02平面層可施加及平面化。在其它實施例中，HSQ及 SiCb程序步驟在多層HSQ上是可重覆的。 本發明的一項優點就是與目前既存的HSQ程序比較，不須額外 的程序步驟。這些程序步驟順序本質上重新排列，因此在新程序所附 加價値中不須額外花費。 5 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） _ I _ I_______ · : ^W I---j— ..... -- - - - A* - I --f. (請先閱讀背面之注意事項再填寫本頁) 經濟部中央樣準局貝工消费合作社印製 44989 8 at _ B7 五、發明説明（4. ) 本發明的另一項優點就是可於施加HSQ後使用高溫(>450。〇) 程序。例如，可使用高溫爐固化例如氧化物緻密及回流以改進介 電質的積體 另一優點係可使用氧氣及水氣固化以於後續程序之前, 癒合(heal)氧化物。 另外，如果有必要，可使用氧電漿去灰而不造成損 害，因為HSQ可被帽狀層保護不受電漿侵蝕。另外，本發明可 結合上述參考申請案的方法。 圖式簡單説明 此發明新奇且可信的特色在附#的申請專利範園中發表。然而， 此發明本身及其它特色優點可參考以下的詳細描述以及附圖而得到更 近一步的了解。其中： 圖1係本發明較佳實施例的側面圖； 圖2a-c係圖1較佳實施例的製程步辟； 圖3係本發明較佳實施例多重連接線的側面圖； 圖4係本發明另一較佳實施例在絕緣渠溝狀使用帽狀hSq層的側面 圖； 圖5係本發明另一較佳實施例使用多晶金屬介電層之HSQ層的側面 圖0 圖式詳細説明 本發明較佳實施例可參考圊1到圖4而得到更佳的了解。相同的 數字對應於不同圖式相同的部分。 參考圖1，為目前本發明的較佳實施例，其中HSQ18沈積在半導體 基板10的連接線丨4之間。HSq可由前述參考申請案已知技術中的方法 之一來施加。一層薄的介質帽狀廣吟是穩定層扣復蓋住層。接著 i 6 — 本紙張尺度:樣IMCNSM4胁（公釐) (請先閲讀背面之注意事項再填寫本頁)
在4989 8 經濟部中央橾準局員Η消費合作社印製 A7 B7 五、發明説明（5 ) 在帽狀層上成長一層低k材料22。 參考圖2a~2b，為形成本發明實施例圖丨顯示整個結構的程序步 驟。圖2a描述一半導體基板1〇覆蓋一層介電質12。目前發明描述的實 施例可直接降低積體電路連結線之間的電容。因為這些連結線一般可 位於半導體材料，例如矽單晶晶片表面製造的主動元件。半導體基板 10 —般可包括好幾層不同的半導體材料來製造半導體元件的主動成 份。為簡化起見，這些層及元件並沒有在此顯示。介電層12可以是任 何能將金屬連結線14與層内成份或其它底下材料以及半導體基板10突 起的部分絕緣化的任何適當金屬材料。 連結線最好是藉由在較平面介質層12上沈積鋁來形成。鋁可以光 阻來圖案化並由己知技術的方法來蝕刻。此程序可產生如圖2a所示的 金屬連結線14。目前發明所使用的方法考慮使用高縱寬比乖的金屬， 其連結金屬的厚度比寬度大。高縱寬比乖的金屬可在維持高密度電路 緊密間隔時降低線電阻。連結線與下面之間的連結可由通道及插頭16 表示。通道的數字及位置可由以下的電路設計決定。 圖2b顯示HSQ18可施加在晶片表面連接線Μ之間。如圖2b所示， HSQ18最好以旋塗程序到足夠的厚度以填滿金屬連接線14之間的重要 區域。最佳的材料為多晶氫倍半氧矽烷(HSQ)，其介電常數大約小於 3。此材料可由Dow-Corning出售，其商標名為FOX，也可透過Allied Signal，其商標名為HSSO。HSQ接著最好在旋塗儀熱烤盤上以溫度 固化。 再HSQ18之後’成長一層如圖2c所示的穩定帽狀層2〇。此帽狀層 可避免微裂縫的集結或傳播，並允許氧氣及水氣的爐烤固化，在沒有 裂縫之下’允許較厚的HSQ層並改善平面化。帽狀層的厚度可根據 HSQ層的強度及厚度來最佳化。帽狀層可由電漿方式產生的緻密沿〇2 及&凡’氟基Si〇2或其它適合的介電質。最好是由電漿增進化學氣相 本紙張尺度適用中國國家標準（CNS ) A4規格（2】〇Χ297公釐） ^^1. : ί —^9 I —^1 ιι·3 11— · ^^1 I...... I^i ^^1 Ms <請先M讀背面之注意事項再填寫本頁) 經濟部中央棣準局員工消费合作社印製 44989 8 A7 B7____五、發明説明（6 ) 沈積法成長Si02，因為它使用相同的CF基化學來作蝕刻就如同通道蝕 刻一般。帽狀層的厚度最好在1000埃到3000埃左右，且最好是2000 埃。 在帽狀層20施加之後，HSQ層可固化。此帽狀層可避免微裂缝的 集結或傳播，並允許氧氣及水氣的爐烤固化，在沒有裂縫之下，允許 較厚的HSQ層並改善平面化。 帽狀層20之後，可成長一厚約16,000埃的Si02介質層22來平面 化。在介質層平面化之後，結構如圖1所示。在較佳實施例中，介質 層可由電漿增進化學氣相沈積法(PECVD)來成長並由化學機械式研磨 (CMP)來平面化。接下來會討論到，目前發明藉由將傳統介電材料之 間放入低介電材料來結合Si02及低介電常數材料的優點。結構穩定、 熱傳導等都可由Si02或其它適合的介電質來增進。 目前發明的方法可重覆使用以形成多重連接線堆疊在其它上面。 多重連接線的例子可參見圖3。一般多重連接線必須要有通道及接觸 16從這一層連接到另一層。這些通道一般在連接介層完成及以先前已 知技術平面化以後才製作。 圖3也顯示一襯料24。襯料24的使用可使HSQ與連接線14接觸。襯 料24可為一蝕刻停止或像是CVD氧化矽的外保護層。HSQ層接著旋塗 在晶片表面的襯料上。 然而圖1顯示的結構類似先前技術的結構，有一項特色須要注意。 目前發明的方法允許施加的HSQ厚度比先前可能的還要大。增加的厚 度可藉由金屬連接層之間的低介電常數材料來降低連接層的電容，並 降低相同金層連接處的邊緣電容。在使用先前技術方法的結構中，最 大的平面範園厚度26大约4000埃且在連結線28之上的HSQ厚度大約 1000埃。使用先前技術的方法，HSQ厚度施加到最大値會有嚴重的裂 縫問題。目前發明的較佳實施例包括範圍26厚度大於4000埃，且在連 ^^^1· —If— —1 tm «n n —a^i —^if ms ^ ， (請先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家梯準（CNS ) A4規格（2丨〇><297公釐） 44989 8 A7 ____B7_ 五、發明説明（7 ) 結線28之上的HSQ厚度大約1〇〇〇埃。 目前發明另一個較佳實施例如圖4所描述。此實施例將目前發明之 方法應用到S/N 60/ (TI-19738)的結構。此申請案揭示一申請案，其中 HSQ放置於絕緣構隙來提供高溫電阻渠溝重填。發現到在火爐固化之 前施一帽狀層在HSQ上也有利於結構。特別是，帽狀層可在無害效應 下允許較厚的HSQ層，增加可能的層厚度到大於1微米。一帽狀層也允 許HSQ層在氧氣及水氣中烘烤固化並降低HSQ層的收縮。 如圖4所示，矽基板10有絕緣渠溝30以絕緣鄰近的主動元件，例如 電晶體32。此氤化的帽狀層22可當作形成蝕刻渠溝的hardmask以及氧 化物平面化化學機械蝕刻的終止判斷。基板的表面最好接著旋塗一層 HSQ18 ° HSQ18最好能在旋塗儀的熱盤烘烤上部份地固化。一帽狀層 20，最好是PETEOS接著可如前所述地施加在其上。在帽狀層施加 後，HSQ可安全地在1050。<：的氮、氧或850°C的水氣中烘烤固化。烘烤 固化的時間最好在15到100分鐘且最佳狀況是大約30分鐘。 經濟部中央標準局—工消費合作社印製 ^^1- 1^1 Hi ρ—^1 1--ί- n— 1 I « ^^1 - 1^1 ,IS«J (請先閲讀背面之注意事項再填寫本頁) 本發明另一實施例可如圖5所示。此實施例使用一HSQ層當作多晶 金層介質層。如圖5所示，矽基板10有一個或多個閘極34。此閘極可 包括絕緣渠溝30來絕緣鄰近的主動元件。基板的表面最好是旋塗 HSQ18在其上。接著，HSQ18最好能在旋塗儀的熱盤烘烤上部份地固 化。一帽狀層20，最好是PETEOS接著可如前所述地施加在其上。在 帽狀層施加後，HSQ可安全地在1050°C的氮、氧或850°C的水氣中烘烤 固化。烘烤固化的時間最好在15到100分鐘且最佳狀況是大約3〇分 鐘。此實施例可結合其它前述之實施例來使用。 目前發明也考慮使用一穩態層來結合先前共同申請案所指定的結 構或技術。
本紙張尺度適用中國國家標準（CNS } A4規格（2丨0X297公釐） 449898 A7 ~______ B7_ 五、發明説明（8 ) 以下為唯-的表格，提供—些實施例及圖式的全貌 表格 圖式元件 較佳或特殊的例早 一般術語 其它替代的例子 10 基板或晶圓 GaAs 12 氧化矽 緩衝層 14 互連接線 TiN/Al/TiN， Cu,W 16 通道 鋁 18 HSQ 低介電常數材料 Xeroge，有機 SOG，低介電常 數聚合物 20 TE0S~~ 帽狀層 氟基Si〇2， Si3N4，雄石或其 它有良好機械強 度的介電質 22 Si02 金層間介電質 氟基Si〇2， Si3N4，鑽石或其 它有良好機械強 度的介電質 24 氧化矽 襯料 氟基Si02 30 渠溝 32 氮化物 研磨擋 34 氧化矽 氧化墊 -----^--.----,衣-- <請先閲讀背面之注意事項再填寫本頁) ,ιτ 經濟部中央榇丰局員工消費合作社印製 雖然此發明已以一較佳實施例描述如上，然而其描述並非用以限 定本發明。任何熟習此技術者，皆可參考此描述而更清楚了解此描述 實施例之不同的改良及結合及其它發明之實施例。因此，所附的申請 專利範圍可包含任何的改良或實施例。 本紙張尺度適用中國圉家榇準（CNS ) A4规格（210X2.97公嫠）

Claims (1)

  1. 449898 A8 B8 C8 D8 經濟部中央捸率局員工消費合作社印製 六、申請專利範團 1. 一種形成微電子結構的方法，此方法包括步騾： (a) 提供一半導體基板； (b) 施加一層氫倍半氧矽烷(HSQ)在此基板； (c) 施加一帽狀層至氫倍半氧矽烷(HSQ); (d) 爐烤固化此氫倍半氧矽烷(HSQ)層。 2. —種形成微電子結構的方法，此方法包括步驟： (a) 提供一有金屬連結的半導體基板，· (b) 施加一層氫倍半氧矽烷(HSQ)在此有金屬連結的基板； (c) 施加一帽狀層到此氫倍半氧矽烷(HSQ)層； (d) 爐烤固化此氫倍半氧矽烷(HSQ)層。 3. 根據申請專利範圍第1或2項之方法，其中氫倍半氧碎燒(hsq)可施 加在此基板上連接線之間。 4. 根據申請專利範圍第3項之方法，還包括额外的步驟可在施加氫倍 半氧矽烷(HSQ)之前提供一襯料在此導電的連結線。 5. 根據申請專利範圍第1或2項之方法，其中氫倍半氧矽烷(HSQ)可施 加在此基板上的絕緣渠溝之間。 6. 根據申請專利範圍第1或2項之方法，其中此帽狀層可選自Si02， Si3N4及氟基Si〇2之群。 7. 根據申請專利範圍第1或2項之方法，其中爐烤固化之週園係來自 CxHy，CxFy，A ’ 〇2，氏0以及形成氣體田2及叫混合物)之群。
    標 冢 * < u 1 - j I ^1 ^1— n I . · _ n «n It {k _ T n n m n i I 浲 i 销 (請先閲讀背面之注意事項再填寫本頁) 449898 A8 B8 g _ ， 六、申請4利範目 一 8·根據申請專利範圍第7項之方法，斧中爐烤固化的溫度超過4〇〇〇c。 9. 根據申請專利範圍第7項之方法，其中爐烤固化的溫度超過8〇〇〇c。 10. 根據申請專利範圍第丨或2項之方法，包括額外步騾為在沈積後平 面化弟一介電質並接著重覆步驟(a)到（d)以建立一多屠互連結構 造0 11. 一微電子結構，包括： (a)半導體基板；以及 ⑹基板上之實質無裂缝的已固化氫倍丰氧秒燒(HSQ)層，其厚度大 約大於4000埃。 12. 根據申請專利範圍第11項之結構，其中此氫倍半氧珍燒(hsq)層 可施加在基板上的連結線之間。 13_根射請專利細第11項之結構，其中此氫倍半氧摊(HSQ)層 可施加在基板上的絕緣渠溝之間。 14. 根據申叫專利範圍弟11項之結構，其中此帽狀層可選自免〇2， Si3N4及氟基Si02之群。 15. 根據巾#專利第11項之結構’其中氫倍半氧^^(HSq)層可 施加在半導體基板上的元件閘極當作多晶金屬介電質。 本紙張尺度適用中國國家樣準（CNS > A4規格（210X297公嫠） ---：--^----^------1T------4 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標率局員工消費合作社印製
TW086111042A 1996-07-30 1997-10-06 Hydrogen silsesquioxane thin films for low capacitance structures in integrated circuits TW449898B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US2313396P 1996-07-30 1996-07-30

Publications (1)

Publication Number Publication Date
TW449898B true TW449898B (en) 2001-08-11

Family

ID=21813302

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086111042A TW449898B (en) 1996-07-30 1997-10-06 Hydrogen silsesquioxane thin films for low capacitance structures in integrated circuits

Country Status (5)

Country Link
US (1) US6114186A (zh)
EP (1) EP0822586A3 (zh)
JP (1) JPH1074755A (zh)
KR (1) KR980012470A (zh)
TW (1) TW449898B (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2350931B (en) * 1997-06-27 2001-03-14 Nec Corp Method of manufacturing semiconductor device having multilayer wiring
JP3390329B2 (ja) * 1997-06-27 2003-03-24 日本電気株式会社 半導体装置およびその製造方法
US6376893B1 (en) * 1997-12-13 2002-04-23 Hyundai Electronics Industries Co., Ltd. Trench isolation structure and fabrication method thereof
JP3175691B2 (ja) * 1998-05-08 2001-06-11 日本電気株式会社 多層配線半導体装置の製造方法
US6239026B1 (en) 1998-09-28 2001-05-29 Conexant Systems, Inc. Nitride etch stop for poisoned unlanded vias
JP3125781B2 (ja) * 1999-03-03 2001-01-22 ヤマハ株式会社 半導体装置の製法
JP2000286254A (ja) * 1999-03-31 2000-10-13 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6228780B1 (en) * 1999-05-26 2001-05-08 Taiwan Semiconductor Manufacturing Company Non-shrinkable passivation scheme for metal em improvement
US6660618B1 (en) * 1999-08-18 2003-12-09 Advanced Micro Devices, Inc. Reverse mask and oxide layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems
US6318124B1 (en) * 1999-08-23 2001-11-20 Alliedsignal Inc. Nanoporous silica treated with siloxane polymers for ULSI applications
GB2358285A (en) * 1999-08-30 2001-07-18 Lucent Technologies Inc Interlevel dielectrics
US6638358B1 (en) * 2000-01-13 2003-10-28 Advanced Micro Devices, Inc. Method and system for processing a semiconductor device
KR20020002732A (ko) * 2000-06-30 2002-01-10 박종섭 반도체 소자의 절연막 형성 방법
KR100486333B1 (ko) * 2000-07-21 2005-04-29 가부시끼가이샤 한도따이 프로세스 켄큐쇼 반도체 장치 및 그 제조 방법
KR100397372B1 (ko) * 2000-09-09 2003-09-13 학교법인 포항공과대학교 다면체 구조의 실세시퀴옥산을 포함하는 저유전재료 및이를 이용한 초저유전박막의 제조방법
US6489242B1 (en) * 2000-09-13 2002-12-03 Lsi Logic Corporation Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures
US6780499B2 (en) * 2001-05-03 2004-08-24 International Business Machines Corporation Ordered two-phase dielectric film, and semiconductor device containing the same
US6670717B2 (en) * 2001-10-15 2003-12-30 International Business Machines Corporation Structure and method for charge sensitive electrical devices
US7083991B2 (en) * 2002-01-24 2006-08-01 Novellus Systems, Inc. Method of in-situ treatment of low-k films with a silylating agent after exposure to oxidizing environments
US7541200B1 (en) 2002-01-24 2009-06-02 Novellus Systems, Inc. Treatment of low k films with a silylating agent for damage repair
DE10237787A1 (de) * 2002-08-17 2004-03-04 Robert Bosch Gmbh Schichtsystem mit einer Siliziumschicht und einer Passivierschicht, Verfahren zur Erzeugung einer Passivierschicht auf einer Siliziumschicht und deren Verwendung
US7015582B2 (en) * 2003-04-01 2006-03-21 International Business Machines Corporation Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics
TWI349343B (en) * 2003-07-11 2011-09-21 Koninkl Philips Electronics Nv Encapsulation structure for display devices
US7557035B1 (en) 2004-04-06 2009-07-07 Advanced Micro Devices, Inc. Method of forming semiconductor devices by microwave curing of low-k dielectric films
US7285503B2 (en) * 2004-06-21 2007-10-23 Applied Materials, Inc. Hermetic cap layers formed on low-k films by plasma enhanced chemical vapor deposition
KR100702122B1 (ko) * 2005-01-04 2007-03-30 주식회사 하이닉스반도체 반도체 기판 상에 금속 층간 절연층을 형성하는 방법
US8283899B2 (en) 2008-11-04 2012-10-09 Broadcom Corporation Reducing current leakage and improving shelf life time of battery-based-devices

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4756977A (en) * 1986-12-03 1988-07-12 Dow Corning Corporation Multilayer ceramics from hydrogen silsesquioxane
CA2017720C (en) * 1990-05-29 1999-01-19 Luc Ouellet Sog with moisture-resistant protective capping layer
JPH04107831A (ja) * 1990-08-27 1992-04-09 Sharp Corp 半導体装置の製造方法
US5145723A (en) * 1991-06-05 1992-09-08 Dow Corning Corporation Process for coating a substrate with silica
US5874367A (en) * 1992-07-04 1999-02-23 Trikon Technologies Limited Method of treating a semi-conductor wafer
JP3214186B2 (ja) * 1993-10-07 2001-10-02 三菱電機株式会社 半導体装置の製造方法
JP2751820B2 (ja) * 1994-02-28 1998-05-18 日本電気株式会社 半導体装置の製造方法
US5456952A (en) * 1994-05-17 1995-10-10 Lsi Logic Corporation Process of curing hydrogen silsesquioxane coating to form silicon oxide layer
US5530293A (en) * 1994-11-28 1996-06-25 International Business Machines Corporation Carbon-free hydrogen silsesquioxane with dielectric constant less than 3.2 annealed in hydrogen for integrated circuits
JP3070450B2 (ja) * 1995-07-14 2000-07-31 ヤマハ株式会社 多層配線形成法
US5567660A (en) * 1995-09-13 1996-10-22 Taiwan Semiconductor Manufacturing Company Ltd Spin-on-glass planarization by a new stagnant coating method

Also Published As

Publication number Publication date
EP0822586A2 (en) 1998-02-04
US6114186A (en) 2000-09-05
KR980012470A (ko) 1998-04-30
JPH1074755A (ja) 1998-03-17
EP0822586A3 (en) 1998-12-09

Similar Documents

Publication Publication Date Title
TW449898B (en) Hydrogen silsesquioxane thin films for low capacitance structures in integrated circuits
US6159842A (en) Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections
TWI278962B (en) Semiconductor device
US7332428B2 (en) Metal interconnect structure and method
JP4018596B2 (ja) 半導体装置の製造方法
US6214719B1 (en) Method of implementing air-gap technology for low capacitance ILD in the damascene scheme
US5818111A (en) Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials
US6933586B2 (en) Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens
EP0657925B1 (en) Planarization technique for an integrated circuit
US20040251549A1 (en) Hybrid copper/low k dielectric interconnect integration method and device
US6187662B1 (en) Semiconductor device with low permittivity interlayer insulating film and method of manufacturing the same
CN1319148C (zh) 具有改进的层间界面强度的半导体器件及其制备方法
KR100612064B1 (ko) 구리/저유전율의 상호 접속 구조를 위한 개선된 화학적 평탄화 성능
US6258715B1 (en) Process for low-k dielectric with dummy plugs
KR20000074613A (ko) 실리콘-메틸 결합을 함유하는 절연층을 포함하는 다층 구조의 절연막 및 그 형성방법
KR100684905B1 (ko) 다마신 공정의 방법
TWI251896B (en) Semiconductor device and the manufacturing device thereof
JP2003303880A (ja) 積層層間絶縁膜構造を利用した配線構造およびその製造方法
JP2001118928A (ja) 集積回路の製造方法
TW304297B (zh)
JP3371576B2 (ja) 半導体集積回路装置の製法
US7674390B2 (en) Zeolite—sol gel nano-composite low k dielectric
KR100588636B1 (ko) 반도체 소자의 층간 절연막 제조 방법
TW486779B (en) Method to prevent crack in inter metal dielectric layer
JP2002134610A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent