GB2358285A - Interlevel dielectrics - Google Patents

Interlevel dielectrics Download PDF

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Publication number
GB2358285A
GB2358285A GB0019966A GB0019966A GB2358285A GB 2358285 A GB2358285 A GB 2358285A GB 0019966 A GB0019966 A GB 0019966A GB 0019966 A GB0019966 A GB 0019966A GB 2358285 A GB2358285 A GB 2358285A
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United Kingdom
Prior art keywords
layer
dielectric
conductor
material layer
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0019966A
Other versions
GB0019966D0 (en
Inventor
Xiaojun Deng
Jia Sheng Huang
Anthony Stephen Oates
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
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Lucent Technologies Inc
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Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of GB0019966D0 publication Critical patent/GB0019966D0/en
Publication of GB2358285A publication Critical patent/GB2358285A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The device comprises a silicon nitride layer <B>30</B> between a first dielectric layer <B>40</B> and a planarising layer <B>45</B>. The SiN layer <B>30</B> has a Young's modulus greater than that of the dielectric material so that it provides greater constraint for plastic relaxation of the conductor and improves the electromigration characteristics of the conductive structure.

Description

2358285 A Method Of Manufacturing An Integrated Circuit And An Integrated
Circuit
Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to conductive structures in integrated circuits.
B ackeround of the Invention Integrated circuits have long used metal layers for interconnects.
Subsequent complexity has added more layers of metallization separated by dielectric layers, and has shrunk the size of the intercomects."A'1he physical dimensions of these interconnections have shrunk, the reliability problels associated with electromigration of the interconnects has increased. Accordingly, it would be desirable to provide an integrated circuit and process for manu Facturing the integrated circuit that reduces electromigration.
Summary of the Inventio
The present invention provides an integrated circuit including a is material layer formed on a structure including a conductor formed in a dielectric layer. The material layer may be formed on the conductor or on the dielectric wherein the structure is other than the uppermost conductive layer in an integrated circuit. The - material layer has a Young's modulus greater than the Young's modulus of the dielectric material. The material layer improves the electromigration characteristics of the conductive structure. In one embodiment, the material layer is a passivation layer. In another embodiment, the material layer is SK The present invention also provides a process of forming the material layer on a structure including a conductor and a dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
Brief Descdpt jon of the Drawin The invention is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, according to common practice in the semiconductor industry, th various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in th(t drp,-w-ing are the following figures:
Fig. 1 is a schematic diagram of an integrated circuit according to an illustrative embodiment of the present invention; Fig. 2 is a flowchart diagram for manufacturing the integrated circuffi shown in Fig. 1; Fig. 3 is a schematic diagram of an integrated circuit according to another illustrative embodiment of the present invention; Fig. 4 is a top view of a via chain structure useful for illustrating the present invention; Figs. Sa and 5b are schematic diagrams illustrating electromigratio a first conductive layer M1 and a second conductive layer M2, respectively, within integrated circuit; Fig. 6 a diagram illustrating the cumulative failure distributions of,, conductor layers M1 and M2 stressed with a current density of 2 MA/cm 2 at 250 C Fig. 7 is a diagram illustrating the cumulative failure distributions ol conductor layers M2, M3 and M4 of vial, via2 and via3 structures stressed with a, current density of 2 MA/cm.2 at 250 'C; 1 i 1 1 Fig. 8 is a diagram illustrating the depletion distance of AI M i conductor layers M3 and M4 from the via3 structure after various resistance increases; Fig. 9a is a diagram illustrating the median time to failure (MTF) of conductor layers Ml, M2, M3 of four-level structures with current densities 2.5, 2 and 1.5 MA/cm at 250'C; Fig. 9b is a diagram illustrating the median time to failure (MTF) of conductor layers M2, M3, M4 of four-level structures with current densities 2.5, 2 and 1.5 MA/cm2 at 250 'C; and Figs. 10a and 10b are schematic diagram of conductor layers M1 and M2 encapsulated by dielectrics in a two-level structure.
Detailed Descdption of the Inventio Referring now to the drawing, wherein like reference numerals refer to like elements throughout, Fig. I is a schematic diagram of an illustrative integrated circuit according to the present invention. Fig. 2 is a flowchart diagram describing the process for manufacturing the integrated circuit shown in Fig. 1.
At step 100, a first patterned conductor 20 is formed on a substrate 10.
The first patterned conductor 20 is a metal such as tungsten, aluminum, copper, nickel, aluminum/copper alloy or other conducting material suitable for use as a conductor as is known to those skilled in this art. Typically, the first patterned conductor 20 is blanket deposited above the substrate 10. The first patterned - conductor 20 may be patterned by: 1) applying a layer of resist material on the blanket deposited material; 2) exposing the resist material to an energy source which passes through a reticle; 3) removing areas of resist to form the pattern in the resist; and 4) etching the blanket deposited material The energy source may be an e-beam, light source, or other suitable energy source.
The substrate 10 is, for example, a semiconductor such as silicon or Z5 compound semiconductor such as GaAs or SiGe. Alternatively, the substrate 10 may be an intermediate layer in an integrated circuit such as a dielectric, conductor, or other material. In addition, the upper surface 11 of the substrate 10 may not be planar. In addition, the upper surface 11 may be planarized using, for example, chemical mechanical polishing (CUIP) as is well known.
At step 110, the first dielectric layer 40 is formed on the first pattenied conductor 20. The first dielectric layer 40 may be blanket deposited using conventional techniques. The first dielectric layer 40 is, for example, a dielectric; S acb as a high-density deposited silicon oxide.(e.g.,SiO2) - Alternatively, the first insulating layer may be a borophosphosilicate glass, a phosphosilicate glass, a gi4s' formed from phosphorous and/or boron-doped tetraethyl orthosilicate, spin- on gW xerogels, aerogels, or other low dielectric constant films such as polymer, fluorin4t, d oxide and hydrogen silsesquioxane.
At step 120, a first material layer 30 is formed on the first dieleC layer 40. The first material layer 30 may be blanket deposited using conventional 1 techniques. The thickness of the first material layer 30 may be I OOOA to 2000A about 1500A_ The first material layer 30 may be selected to have a Young's mo kplus greater than the Young's modulus of the first dielectric layer 40. By providing thp first material layer, the rate of electromigration of the first patterned conductor 2d may be reduced which enhances integrated circuit lifetime. The rate of electromigration depletion is related to the maximum stress difference that the conductor can sustain without plastic deformation between the cathode and anode.
The inventors theorize that the first material layer 30 may provide greater constraint than the first dielectric layer 40 for plastic relaxation of the firstl patterned conductor 20 because the first material layer 30 has a greater Young's modulus. In other words, the material layer may inhibit the extrusion of the first patterned conductor 20 by providing greater mechanical constraint.
At step 130, a first planari ati n layer 45 is formed. The first planarization layer 45 may be formed by blanket depositing a layer of silicon oxide! which may be deposited from tetraethyl orthosilicate with plasma- assistance (PETEOS) and then planarizing the blanket deposited layer using chemical mechanical polishing. The first planarization layer may be another dielectric as discussed above with regard to the first dielectric layer 40.
At step 140, vias and plugs may be formed in the first dielectric laye 40, the planarization layer 45, and the material layer 30 using convention techniq4e 1 0.
The vias are filled with a conductive material 60 such as an aluminum/copper allo,y tungsten, aluminum, or other conventional material. A liner layer 50 may also be! formed in the via. This layer may function as a barrier layer, an adhesion layer, and/or a nucleation layer. For example, the liner layer 50 may be layers of (1) Ti and TiN or (2) Ti and TiN and Ti. Alternatively, the liner layer may be WSi, TiW, Ta, TaN, Ti, TiN, Cr, Cu, Au, WN, TaSiN, or WSiN.
At step 150, a second patterned conductor 70 is formed on the first planarization layer 45. The second patterned conductor 70 may be formed using the same process and materials used to form the first patterned conductor 20.
At step 160, the second dielectric layer 90 is formed on the patterned conductor 70. The second dielectric layer 90 may be formed using the same process and materials used to form the first dielectric layer 40. At step 170, a second material layer 80 is formed on the second dielectric layer 90. The second material layer 80 may be formed using the same process and materials used to form the first material layer 30. In an alternative embodiment, the second material layer 80 may not be formed on the second patterned conductor 70. At step 180, a second planarization layer 95 is formed on the material layer 80. The second planarization layer 95 may be formed using the same processes and materials used to form the first planarization layer 45.
Subsequently, the integrated circuit is completed by adding, if necessary, additional metal levels that may including interconnects formed using the process above and conventional processes to complete an integrated circuit. Tlie integrated circuit also includes transistors and other components necessary for a particular integrated circuit design. Ile processes for manufacturing an integrated circuit including these structures are described in 1-3 Wolf, Silicon Processing for the 3aLl Er (1986), which is incorporated herein by reference.
Fig. 3 illustrates an alternative embodiment of the present invention.
This embodiment is the same as the embodiment shown in Fig. I except that the material layer is formed on the patterned conductors. Further, in this embodiment, the first dielectric layer 40 may include multiple layers including different dielectric, materials. For example, the dielectric layer 40 may include a layer of plasma enhanced. TEOS (the same as layers 45, 95) formed on a layer of high- density deposited silicon oxide.
In an alternative embodiment, the patterned conductor may be forn4c d in a dielectric layer forming a dual'damascene structure. In this case, the material layer is formed above a further dielectric that is formed above the patterned conductor. Alternatively, the material layer may be formed on the patterned conductor. Further, the grooves and vias of the dual damascene structure may be lined with the material layer so that the material layer(s) may be formed above and below the conductor in the dual dama cene structure.
Experiment The experimental data below describes the experiments for two and four-level structures that have two and four layers of conductors, respectively. Fiore 4 illustrates a test structure that includes 5 tungsten-plug vias in series, connectino different conductor layers. The two-level structure includes conductor layers MI land M2 and the four-level structure includes conductor layers Ml, M2, M3, and M4.
Each via has a diameter of 0.36 pm. The conductor layers M1 andl 142 include identical interconnects (runners). The interconnects are stacks of 250A of., TiN formed on 4500A of AlCu formed on 600A of TiN formed on 300A of Ti. The st4c ks have a width of 0.36 pm. For the two-level structure, conductor layer M2, as is. 1 I! shown in Figs. 10a and 10b, is passivated with high-density plasma (HDP) oxide SiN and the via to via separation is 240 Lm. For the four-level structure, conducijj layer M4 is passivated with high-density plasma (HDP) oxide and SiN, and the V via separation is 125 pm. For the four-level structure, vial connects MI and M2.;-vj'a2 connects M2 and M3; via3 connects M3 and M4.
The via chains were stressed with constant stripe current densities ranging from 0.5 to 2.5 MA/cm at 250 C with a typical sample size of 20. i Resistance variations due to electromigration were studied independently for the lower and upper conductor layers. For the lower conductor layers, voltage was measured between VL+ and VL- to monitor the resistance variation of the lower conductor layers as is shown in Fig. 5a. For the upper conductor layers, voltage I across Vu+ and Vu was recorded for resistance change in the upper conductor 1#(rs as is shown in Fig. 5b. As a simple approximation to compensate the sheet resis.ce of the shunting layers, the failure criteria of 20% and 4.5% are used for the upper.
conductor layers and the lower conductor layers. The sheet resistance of the shunting layers are 40 and 9 LVsquare for upper and lower conductor layers, respectively.
Fig. 6 illustrates the cumulative failure distributions of conductor layers M I and M2 of the two-level structures stressed with 2 MA/cm at 250 C. The conductor layer M1 exhibits shorter failure times than the conductor layer M2, despite sheet resistance compensation. The asymmetry of electromigration lifetimes is also observed at different stress current densities. Cross-section scanning electron microscopy (SEW shows that conductor layer M2 generally exhibits less depletion than conductor layer MI after a given electromigration stress time.
Fig. 7 illustrates, for the four-level structure, the fOure distributions of the upper conductor layers M2, M3 and M4 of vial, via2 and via3 stressed with 2 MA/cm.2 at 250 'C. The lifetime increases for the higher conductor layers. In particular, the conductor layer M4, which is adjacent to the passivation layers, exhibits significantly longer electromigration lifetimes than those of the conductor layers M3 and M2. SEM reveals that the amount of depletion in the upper conductor layers is less than that in the lower conductor layers, which is simil to the data derived from the two-level structure.
Fig. 8 summarizes the total depletion distance for conductor layers M3 and M4 for various resistance increases. Fig. 9a illustrates the mean time between failures of the conductor layers Ml, M2 and M3 of vial, via2 and via3 at current densities of 2.5, 2 and 1.5 MA/cm2 using a failure criterion of a 20% resistance increase. Fig. 9b illustrates the mean time between failures of the conductor layers M29 M3 -and M4 using a failure criterion of a 4.5% resistance increase. In both cases, the lifetimes are greater at the upper conductor layers. The lifetime enhancement is particularly distinct for conductor layer M4.
The rate of electromigration depletion is related to the maximum stress difference that the conductor can sustain without plastic deformation between the cathode and anode. The increasing lifetime at the upper conductor layer may suggest an increasing influence from the passivation. The inventors theorize that the SiN may provide greater constraint than the oxide for plastic relaxation of the conductor layers formed from Al, as a result of a larger Young's modulus. As is shown in Fig. 10a for the two-level structure, the Al of conductor layer M1 may extrude into the multiple layers of oxide during electromigration. As is shown in Fig. 10b, the SiN layer formed on the high-density plasma oxide may provide greater mechanical constrajn for Al extrusion of the conductor layer M2 to occur. As a result, the mechanical 1 confinement is greater in conductor layer. M2 than in conductor layer Ml. In add#ipn, the topography of the SiN layer may influence the mechanical constraint of the conductor layer M2.
Although the invention has been described with reference to exemp Y embodiments, it is not limited to those embodiments. Rather, the appended clamis should be construed to include other variants and embodiments of the invention, which may be made by those skilled in the art without departing from the true spirill, and scope of the present invention.

Claims (12)

What is Claimed:
1. An integrated circuit comprising:
2 a first interlevel dielectric; and 3 a second interlevel dielectric formed above the first interlevel 4 dielectric; the first interlevel dielectric including:
6 a first dielectric layer, 7 a first conductive element formed in the first dielectric layer, and 8 a first material layer formed on the first dielectric layer.
1
2. The integrated circuit of claim 1 wherein the second interlevel 2 dielectric comprises:
3 a second dielectric layer; 4 a second conductive element formed m the first dielectnc layer; and a second material layer formed on the second dielectric layer.
1
3. The integrated circuit of claim 1 wherein the first material layer 2 has a Young's modulus greater than a Young's modulus of the first dielectric layer.
1
4. The integrated circuit of claim 1 wherein the first material layer 2 is a passivation layer.
1
5. The integrated circuit of claim 1 wherein the first material layer 2 is SW.
1
6. The integrated circuit of claim 1 wherein a second dielectric 2 layer is formed on the first material layer.
1
7. A process for ni anu facturing an integrated circuit comprising:
2 forming a first interlevel dielectric by:
3 forming a first dielectric layer, 4 forming a first conductive element in the first dielectric layer, and forming a first material layer on the first dielectric layer, and 6 forming a second interlevel dielectric above the first interlevel 7 dielectric.
1
8. The process of claim 7 further comprising forming the secon 2 interlevel dielectric by:
3 forming a second dielectric layer; 4 forming a second conductive element in the first dielectric layer; -a( forming a second material layer on the dielectric layer.
1
9. The process of claim 7 wherein the first material layer has g 2 Young's modulus greater than a Young's modulus of the first dielectric layer.
1
10. The process of claim 7 wherein the first material layer is a 2 passivation layer.
1
11. The process of claim 7 wherein the first material layer is SiN 1
12. The process of claim 7 further comprising forming a second 2 dielectric layer on the first material layer.
GB0019966A 1999-08-30 2000-08-14 Interlevel dielectrics Withdrawn GB2358285A (en)

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GB2358285A true GB2358285A (en) 2001-07-18

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3046146A1 (en) * 2015-01-14 2016-07-20 Fuji Electric Co. Ltd. High breakdown voltage passive element and high breakdown voltage passive element manufacturing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100703971B1 (en) * 2005-06-08 2007-04-06 삼성전자주식회사 Semiconductor integrated circuit device and method for fabricating the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5641581A (en) * 1992-07-17 1997-06-24 Kabushiki Kaisha Toshiba Semiconductor device
EP0822586A2 (en) * 1996-07-30 1998-02-04 Texas Instruments Inc. Improvements in or relating to integrated circuits
EP0849796A2 (en) * 1996-12-17 1998-06-24 Texas Instruments Incorporated Improvements in or relating to integrated circuits
EP0851480A2 (en) * 1996-12-25 1998-07-01 Canon Sales Co., Inc. Stress-adjusted insulating film forming method, semiconductor device and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5641581A (en) * 1992-07-17 1997-06-24 Kabushiki Kaisha Toshiba Semiconductor device
EP0822586A2 (en) * 1996-07-30 1998-02-04 Texas Instruments Inc. Improvements in or relating to integrated circuits
EP0849796A2 (en) * 1996-12-17 1998-06-24 Texas Instruments Incorporated Improvements in or relating to integrated circuits
EP0851480A2 (en) * 1996-12-25 1998-07-01 Canon Sales Co., Inc. Stress-adjusted insulating film forming method, semiconductor device and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3046146A1 (en) * 2015-01-14 2016-07-20 Fuji Electric Co. Ltd. High breakdown voltage passive element and high breakdown voltage passive element manufacturing method
US10224390B2 (en) 2015-01-14 2019-03-05 Fuji Electric Co., Ltd. High breakdown voltage passive element and high breakdown voltage passive element manufacturing method
US10566410B2 (en) 2015-01-14 2020-02-18 Fuji Electric Co., Ltd. High breakdown voltage passive element

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KR20010021456A (en) 2001-03-15
GB0019966D0 (en) 2000-09-27
JP2001102454A (en) 2001-04-13

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