KR20010021456A - A method of manufacturing an integrated circuit and an integrated circuit - Google Patents

Abstract

PURPOSE: An integrated circuit is provided together with its manufacturing method where electro-migration property of the conductive structure is improved. CONSTITUTION: The integrated circuit substrate(10) comprises a first dielectrics formed in a first dielectrics layer(40) and a first flattened layer(45) formed of a material different from a first material layer (30) and the first dielectrics layer(40) formed over it. By the same process, another layers including the second dielectrics layer(90), material layer(80) and flattened layer(95) are formed. Here, the material of the first material layer(30) has a larger Young's modulus than that of the first dielectrics layer(40).

Description

A method of manufacturing an integrated circuit and an integrated circuit

Field of invention

The present invention relates generally to integrated circuits and, more particularly, to conductive structures in integrated circuits.

Background of the Invention

Integrated circuits have long used metal layers for interconnection. The following complexity added many metallization layers separated by dielectric layers, reducing the size of the interconnects. As the physical dimensions of these interconnects have been reduced, reliability problems associated with the electromigration of the interconnects have increased. Therefore, it is desirable to provide an integrated circuit and a process for manufacturing an integrated circuit that reduces electromigration.

The present invention provides an integrated circuit comprising a layer of material formed on a structure that includes a conductor formed in a dielectric layer. The material layer may be formed on a conductor or dielectric and its structure is different from the topmost conductive layer in an integrated circuit. The material layer has a Young's modulus greater than the Young's modulus of the dielectric material. The material layer improves the electromigration characteristics of the conductive structure. In one embodiment, the material layer is a passivation layer. In yet another embodiment, the material layer is SiN. The invention also provides a process for forming a material layer on a structure comprising a conductive layer and a dielectric layer.

It will be appreciated that both the foregoing general description and the following detailed description are typical, and do not limit the invention.

The invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. In accordance with common practice in the semiconductor industry, it is emphasized that the various features in the figures are not made to scale. In contrast, the dimensions of the various features have been arbitrarily enlarged or reduced for clarity. The drawings include the following drawings.

1 is a schematic diagram of an integrated circuit according to an exemplary embodiment of the present invention.

FIG. 2 is a flow chart of manufacturing the integrated circuit shown in FIG. 1.

3 is a schematic diagram of an integrated circuit according to another exemplary embodiment of the present invention.

4 is a top view of a via chain structure useful for illustrating the present invention.

5A and 5B are schematic diagrams showing electromigration for each of the first conductive layer M1 and the second conductive layer M2 in an integrated circuit.

FIG. 6 shows the cumulative failure distribution of conductive layers M1 and M2 pressurized at a current density of 2MA / cm 2 at 250 ° C. FIG.

7 shows the cumulative failure distribution of conductive layers M2, M3 and M4 of via 1, via 2 and via 3 structures pressurized at a current density of 2MA / cm 2 at 250 ° C. .

8 shows the deflation distance of Al in the conductive layers M3 and M4 from the via 3 after various resistances have increased.

FIG. 9A shows the median time to failure (MTF) of the conductive layers M1, M2, M3 of four-level structures having current densities 2.5, 2 and 1.5 MA / cm 2 at 250 ° C. FIG.

9B shows the median time to failure (MTF) of the conductive layers M2, M3, M4 of four-level structures having current densities 2.5, 2 and 1.5 MA / cm 2 at 250 ° C.

10A and 10B are schematic views of conductive layers M1 and M2 encapsulated with dielectrics in a two-level structure.

Explanation of symbols on the main parts of the drawings

1, 2, 3: Via 10: Substrate

20: first patterned conductor 30: first material layer

40: first dielectric layer 45: first planarization layer

50: liner layer 60: conductive material

70 second patterned conductor 80 second material layer

90 second dielectric layer 95 second planarization layer

M1, M2, M3, M4: conductive layer

Referring now to the drawings, like reference numerals refer to like elements throughout, and FIG. 1 is a schematic diagram of an exemplary integrated circuit according to the present invention. 2 is a flow chart describing a process of manufacturing the integrated circuit shown in FIG.

In step 100, a first patterned conductor 20 is formed on the substrate 10. The first patterned conductor 20 is a metal such as tungsten, aluminum, copper, nickel, aluminum / copper alloy or other conductive material suitable for use as a conductor as known by those skilled in the art. Typically, the first patterned conductor 20 is a blanket deposited on the substrate 10. The first patterned conductor 20 comprises: 1) applying a layer of resist material on the material on which the blanket is deposited; 2) exposing the resist material to an energy source passing through the reticle; 3) removing the area of the resist to form a pattern in the resist; 4) The blanket may be patterned by etching the deposited material. The energy source may be an e-beam, light source or other suitable energy source.

The substrate 10 is, for example, a compound semiconductor such as GaAs or SiGe or a semiconductor such as silicon. Alternatively, the substrate 10 may be an intermediate layer in an integrated circuit such as a dielectric, conductor or other material. In addition, the upper surface 11 of the substrate 10 may not be planarized. In addition, the upper surface 11 may be planarized using, for example, chemical mechanical polishing (CMP), as is already known.

In step 110, a first dielectric layer 40 is formed on the first patterned conductor 20. The first dielectric layer 40 may be a blanket deposited using conventional techniques. The first dielectric layer 40 is, for example, a dielectric such as silicon oxide (eg, SiO ₂ ) deposited at high density. Alternatively, the first insulating layer may comprise borophosphosilicate glass, phosphosilicate glass, phosphorus formed glass and / or boron-doped tetraethyl orthosilicate, spin on glass ( It may also be spin-on glass, xerogels, aerosols or another low dielectric constant film such as polymers, fluorinated oxides and hydrogen silsesquioxanes.

In step 120, a first layer of material 30 is formed on the first dielectric layer 40. The first material layer 30 may be a blanket deposited using conventional techniques. The thickness of the first material layer 30 may be 1000 kPa to 2000 kPa or about 1500 kPa. The first material layer 30 may be selected to have a Young's modulus greater than the Young's modulus of the first dielectric layer 40. By providing a first layer of material, the electromigration rate of the first patterned conductor 20 may reduce the increase in integrated circuit life. The electromigration depletion rate is related to the maximum stress difference that the conductor can maintain without plastic deformation between the cathode and the anode.

The inventors believe that the first material layer 30 is larger than the first dielectric layer 40 for plastic relaxation of the first patterned conductor 20 because the first material layer 30 has a higher Young's modulus. Theorize that pressure may be provided. In other words, the material layer may prevent the protrusion of the first patterned conductor 20 by providing greater mechanical pressure.

In step 130, a first planarization layer 45 is formed. The first planarization layer 45 may be formed by blanket depositing a layer of silicon oxide that may be deposited on tetraethyl regular acid having plasma-assistance (PETOS), followed by blanket deposition using mechanical chemical polishing. Planarize the layer. The first planarization layer may be another dielectric as described above with respect to the first dielectric layer 40.

In step 140 vias and plugs may be formed in first dielectric layer 40, planarization layer 45, and material layer 30 using conventional techniques. Vias are filled with a conductive material 60, such as aluminum / copper alloy, tungsten, aluminum or other conventional material. Liner layer 50 may also be formed in the vias. This layer may function as a barrier layer, an adhesive layer and / or a nucleation layer. For example, the liner layer 50 may be a layer of (1) Ti and TiN or (2) Ti and TiN and Ti. Alternatively, the liner layer may be WSi, TiW, Ta, TaN, Ti, TiN, Cr, Cu, Au, WN, TaSiN or WSiN.

In step 150, a second patterned conductor 70 is formed on the first planarization layer 45. The second patterned conductor 70 may be formed using the same process and the material used to form the first patterned conductor 20.

In step 160, a second dielectric layer 90 is formed on the patterned conductor 70. The second dielectric layer 90 may be formed using the same process and the materials used to form the first dielectric layer 40. In step 170, a second material layer 80 is formed on the second dielectric layer 90. The second material layer 80 may be formed using the same process and the materials used to form the first material layer 30. In alternative embodiments, the second material layer 80 may not be formed on the second patterned conductor 70. In step 180, a second planarization layer 95 is formed on the material layer 80. The second planarization layer 95 may be formed using the same process and the material used to form the first planarization layer 45.

Next, the integrated circuit is completed by adding additional metal levels, if necessary, that may include interconnects formed using the process of the above and conventional processes to complete the integrated circuit. The integrated circuit also includes transistors and other components needed for a particular integrated circuit design. Processes for fabricating integrated circuits containing these structures are described in Silicon Processing for the VLSI Era, (1986), 1-3 Wolf, incorporated herein by reference.

3 illustrates an alternative embodiment of the present invention. This embodiment is the same as the embodiment shown in FIG. 1 except that the material layer is formed on the patterned conductor. Also in this embodiment, the first dielectric layer 40 may include multiple layers that include different dielectric materials. For example, dielectric layer 40 may include a layer of plasma enhanced TEOS (such as layers 45 and 49) formed on a layer of high density deposited silicon oxide.

In alternative embodiments, the patterned conductors may be formed in a dielectric layer forming a dual damascene structure. In this case, a layer of material is formed over the additional dielectric formed over the patterned conductor. Alternatively, the material layer may be formed on the patterned conductor. Grooves and vias of the dual damascene structure may also draw lines in the material layer such that the material layer (s) may be formed above and below the conductors in the dual damascene structure.

Experiment

The experimental data are described below for experiments with two and four level structures with two and four layers of conductors respectively. 4 illustrates a test structure comprising five contiguous tungsten-plug vias, connecting different conductive layers. The two-level structure includes conductive layers M1 and M2 and the four-level structure includes conductive layers M1, M2, M3, and M4.

Each via has a diameter of 0.36 μm. The conductive layers M1 and M2 comprise the same interconnects (runners). The interconnects are a stack of 250 ns TiN formed on 4500 ns AlCu formed on 600 ns TiN formed on 300 ns Ti. The laminates have a width of 0.36 μm. For the two-level structure, as shown in FIGS. 10A and 10B, the conductive layer M2 is passivated with high-density plasma (HDP) oxide and SiN and the via to via spacing is 240 μm. For the four-level structure, the conductive layer M4 is passivated with high-density plasma (HDP) oxide and SiN and the via to via spacing is 125 μm. For a four-level structure, via 1 connects to M1 and M2; Via 2 connects to M2 and M3; Via 3 connects to M3 and M4.

Via chains have a typical sample size of 20 and are pressurized at 250 ° C. in a constant stripe current density range from 0.5 to 2.5 MA / cm 2. Resistance fluctuations due to electromigration are studied independently for the lower and upper conductive layers. For the lower conductive layers, the voltage is measured between V _L + and V _L − to monitor the resistance variation of the lower conductive layers as shown in FIG. 5A. For the top conductive layers, voltage across V _U + and V _U − are recorded for the resistance change in the top conductive layers as shown in FIG. 5B. As a simple approach to compensating sheet resistance of shunting layers, failure criteria of 20% and 4.5% are used for the top and bottom conductive layers. The sheet resistance of the fractionation layers is 40 and 9 m 3 / square for the upper and lower conductive layers, respectively.

6 illustrates the cumulative failure distribution of the conductive layers M1 and M2 of two-level structures pressurized at 250 ° C. at 2MA / cm 2. The conductive layer M1 exhibits a shorter failure time than the conductive layer M2 despite the sheet resistance compensation. Asymmetry of electromigration life is also observed at different pressure current densities. The cross-sectional scanning electron microscopy (SEM) shows that the conductive layer M2 generally exhibits a smaller deflection than the conductive layer M1 after a predetermined electromigration pressure time.

FIG. 7 shows the failure distribution of vias 1, vias 2 and top conductive layers M2, M3 and M4 of the pressurized vias 2MA / cm 2 at 250 ° C. for a four-level structure. Explain. Lifespan increases for higher conductive layers. In particular, the conductive layer M4, adjacent to the passivation layer, exhibits a significantly longer electrophoresis lifetime than the electromagnetization lifetimes of the conductive layers M3 and M2. The SEM shows that the amount of deflation in the upper conductive layer is smaller than that in the lower conductive layer, similar to the data derived from the two-level structure.

8 briefly shows the total deplication distance for the conductive layers M3 and M4 for various resistance increases. 9A shows conductive layers M1, M2 and M3 of via 1, via 2 and via 3 at current densities of 2.5, 2 and 1.5 MA / cm 2 using a failure standard of 20% resistance increase. Describes the average failure interval time. 9B illustrates the average failure interval time of the conductive layers M2, M3 and M4 using a failure standard of 4.5% resistance increase. In both cases, the lifetime is greater than in the upper conductive layers. The increase in life is particularly pronounced for the conductive layer M4.

The rate of electromigration deflation is related to the maximum pressure difference that the conductor can maintain without plastic deformation between the cathode and the anode. Increased lifespan in the upper conductive layer may imply an increasing effect from passivation. The inventors theorize that, as a result of higher Young's modulus, SiN can provide greater pressure than oxide on the plastic relaxation of conductive layers formed from Al. As shown in FIG. 10A for the two-level structure, Al of the conductive layer M1 may protrude into multiple layers of oxide during electromigration. As shown in FIG. 10B, a SiN layer formed on a high density plasma oxide may be provided to generate greater mechanical stress on Al protrusion of the conductive layer M2. As a result, the mechanical limit is greater in the conductive layer M2 than in the conductive layer M1. In addition, the topography of the SiN layer may affect the mechanical stress of the conductive layer M2.

Although the present invention has been described with reference to exemplary embodiments, it is not limited only to the embodiments. Rather, the appended claims are intended to cover other modifications and embodiments of the present invention, which may be made by those skilled in the art without departing from the true spirit and scope of the present invention.

The present invention provides an integrated circuit comprising a layer of material formed on a structure comprising a conductor formed in a dielectric layer. The material layer may be formed on a conductor or dielectric and its structure is different from the topmost conductive layer in an integrated circuit. The material layer has a Young's modulus greater than the Young's modulus of the dielectric material. The material layer improves the electromigration characteristics of the conductive structure. The invention also provides a process for forming a material layer on a structure comprising a conductive layer and a dielectric layer.

Claims (12)

A first midlevel dielectric, and An integrated circuit comprising a second midlevel dielectric formed over the first midlevel dielectric, The first mid-level dielectric, The first dielectric layer, A first conductive component formed in said first dielectric layer, and And a first layer of material formed on the first dielectric layer. The method of claim 1, wherein the second mid-level dielectric, A second dielectric layer, A second conductive component formed in said first dielectric layer, and And a second layer of material formed on said second dielectric layer. The integrated circuit of claim 1, wherein the first material layer has a Young's modulus greater than the Young's modulus of the first dielectric layer. The integrated circuit of claim 1, wherein the first layer of material is a passivation layer. The integrated circuit of claim 1, wherein the first material layer is SiN. The integrated circuit of claim 1, wherein a second dielectric layer is formed on the first material layer. In the process of manufacturing an integrated circuit, Forming a first dielectric layer, Forming a first conductive component on the first dielectric layer, and Forming a first midlevel dielectric by forming a first layer of material on the first dielectric layer, and Forming a second midlevel dielectric on the first midlevel dielectric. 8. The method of claim 7, further comprising forming a second dielectric layer; Forming a second conductive component in the first dielectric layer, and Forming the second midlevel dielectric by forming a second layer of material on the dielectric layer. 8. The process of claim 7, wherein the first material layer has a Young's modulus greater than the Young's modulus of the first dielectric layer. 8. The process of claim 7, wherein the first layer of material is a passivation layer. 8. The process of claim 7 wherein the first layer of material is SiN. 8. The process of claim 7, further comprising forming a second dielectric layer on the first material layer.