TW430977B - Buffer using dynamic threshold-voltage MOS transistor - Google Patents

Buffer using dynamic threshold-voltage MOS transistor

Info

Publication number
TW430977B
TW430977B TW087118154A TW87118154A TW430977B TW 430977 B TW430977 B TW 430977B TW 087118154 A TW087118154 A TW 087118154A TW 87118154 A TW87118154 A TW 87118154A TW 430977 B TW430977 B TW 430977B
Authority
TW
Taiwan
Prior art keywords
transistor
input signal
voltage
variance
buffer
Prior art date
Application number
TW087118154A
Other languages
English (en)
Chinese (zh)
Inventor
Yuuichi Hirano
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of TW430977B publication Critical patent/TW430977B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
TW087118154A 1998-06-11 1998-11-02 Buffer using dynamic threshold-voltage MOS transistor TW430977B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10163440A JPH11355123A (ja) 1998-06-11 1998-06-11 動的しきい値ｍｏｓトランジスタを用いたバッファ

Publications (1)

Publication Number Publication Date
TW430977B true TW430977B (en) 2001-04-21

Family

ID=15773943

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087118154A TW430977B (en) 1998-06-11 1998-11-02 Buffer using dynamic threshold-voltage MOS transistor

Country Status (6)

Country Link
US (1) US6304110B1 (enExample)
JP (1) JPH11355123A (enExample)
KR (1) KR100302251B1 (enExample)
DE (1) DE19855602C2 (enExample)
FR (1) FR2779886B1 (enExample)
TW (1) TW430977B (enExample)

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JP4659826B2 (ja) 2004-06-23 2011-03-30 ペレグリン セミコンダクター コーポレーション Ｒｆフロントエンド集積回路
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US7910993B2 (en) 2005-07-11 2011-03-22 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink
US7890891B2 (en) 2005-07-11 2011-02-15 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US9653601B2 (en) 2005-07-11 2017-05-16 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US8742502B2 (en) 2005-07-11 2014-06-03 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
KR100691108B1 (ko) * 2005-12-28 2007-03-12 동부일렉트로닉스 주식회사 입출력 시차가 감소한 지연 회로
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JP2009171552A (ja) * 2007-12-21 2009-07-30 Nec Electronics Corp 半導体出力回路
US8207784B2 (en) * 2008-02-12 2012-06-26 Semi Solutions, Llc Method and apparatus for MOSFET drain-source leakage reduction
EP2760136B1 (en) 2008-02-28 2018-05-09 Peregrine Semiconductor Corporation Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device
US7924087B2 (en) * 2008-05-20 2011-04-12 Mediatek Inc. Reference buffer circuit
JP5181893B2 (ja) * 2008-07-17 2013-04-10 株式会社リコー インバータ回路
US20100102872A1 (en) * 2008-10-29 2010-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Dynamic Substrate Bias for PMOS Transistors to Alleviate NBTI Degradation
KR101140347B1 (ko) * 2008-11-19 2012-05-03 한국전자통신연구원 동적 문턱 전압 소자를 이용한 스위칭 회로 및 이를 포함하는 휴대기기용 ｄｃ-ｄｃ 변환기
JP5338387B2 (ja) * 2009-03-05 2013-11-13 ミツミ電機株式会社 電源切換え装置
US8723260B1 (en) 2009-03-12 2014-05-13 Rf Micro Devices, Inc. Semiconductor radio frequency switch with body contact
JP5529450B2 (ja) * 2009-07-15 2014-06-25 スパンション エルエルシー ボディバイアス制御回路及びボディバイアス制御方法
US20100321094A1 (en) * 2010-08-29 2010-12-23 Hao Luo Method and circuit implementation for reducing the parameter fluctuations in integrated circuits
US8547166B2 (en) * 2011-07-29 2013-10-01 Macronix International Co., Ltd. Temperature compensation circuit and temperature compensated metal oxide semiconductor transistor using the same
US9590674B2 (en) 2012-12-14 2017-03-07 Peregrine Semiconductor Corporation Semiconductor devices with switchable ground-body connection
WO2014141800A1 (ja) * 2013-03-12 2014-09-18 シャープ株式会社 シフトレジスタ回路、駆動回路、及び表示装置
US20150236748A1 (en) 2013-03-14 2015-08-20 Peregrine Semiconductor Corporation Devices and Methods for Duplexer Loss Reduction
US8803591B1 (en) 2013-11-06 2014-08-12 Freescale Semiconductor, Inc. MOS transistor with forward bulk-biasing circuit
US9406695B2 (en) 2013-11-20 2016-08-02 Peregrine Semiconductor Corporation Circuit and method for improving ESD tolerance and switching speed
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US9831857B2 (en) 2015-03-11 2017-11-28 Peregrine Semiconductor Corporation Power splitter with programmable output phase shift
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US10505530B2 (en) 2018-03-28 2019-12-10 Psemi Corporation Positive logic switch with selectable DC blocking circuit
US10886911B2 (en) 2018-03-28 2021-01-05 Psemi Corporation Stacked FET switch bias ladders
US10236872B1 (en) 2018-03-28 2019-03-19 Psemi Corporation AC coupling modules for bias ladders
US11476849B2 (en) 2020-01-06 2022-10-18 Psemi Corporation High power positive logic switch

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US5422591A (en) 1994-01-03 1995-06-06 Sgs-Thomson Microelectronics, Inc. Output driver circuit with body bias control for multiple power supply operation
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JP3205185B2 (ja) 1994-08-16 2001-09-04 株式会社 沖マイクロデザイン レベル変換回路
US5559368A (en) * 1994-08-30 1996-09-24 The Regents Of The University Of California Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation
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US5644266A (en) 1995-11-13 1997-07-01 Chen; Ming-Jer Dynamic threshold voltage scheme for low voltage CMOS inverter
KR970072681A (ko) * 1996-04-03 1997-11-07 김광호 기판 바이어스가 분리된 회로에서의 정전기 보호회로

Also Published As

Publication number Publication date
KR20000004876A (ko) 2000-01-25
KR100302251B1 (ko) 2001-11-02
DE19855602A1 (de) 1999-12-16
JPH11355123A (ja) 1999-12-24
FR2779886A1 (fr) 1999-12-17
FR2779886B1 (fr) 2001-05-04
US6304110B1 (en) 2001-10-16
DE19855602C2 (de) 2003-01-09

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Legal Events

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GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees