TW429476B - A semiconductor device and a method of making thereof - Google Patents
A semiconductor device and a method of making thereofInfo
- Publication number
- TW429476B TW429476B TW088117151A TW88117151A TW429476B TW 429476 B TW429476 B TW 429476B TW 088117151 A TW088117151 A TW 088117151A TW 88117151 A TW88117151 A TW 88117151A TW 429476 B TW429476 B TW 429476B
- Authority
- TW
- Taiwan
- Prior art keywords
- amorphous silicon
- interconnection
- formation part
- silicon film
- making
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract 4
- 230000015572 biosynthetic process Effects 0.000 abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- 229910021332 silicide Inorganic materials 0.000 abstract 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10282616A JP2000114262A (ja) | 1998-10-05 | 1998-10-05 | 半導体装置及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW429476B true TW429476B (en) | 2001-04-11 |
Family
ID=17654849
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW088117151A TW429476B (en) | 1998-10-05 | 1999-10-05 | A semiconductor device and a method of making thereof |
Country Status (4)
Country | Link |
---|---|
US (1) | US6335250B1 (zh) |
JP (1) | JP2000114262A (zh) |
KR (1) | KR100370331B1 (zh) |
TW (1) | TW429476B (zh) |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1005092A1 (en) * | 1998-11-26 | 2000-05-31 | STMicroelectronics S.r.l. | High breakdown voltage PN junction structure and related manufacturing process |
KR100396698B1 (ko) * | 2001-03-15 | 2003-09-03 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 구조 |
US6489206B2 (en) * | 2001-03-22 | 2002-12-03 | United Microelectronics Corp. | Method for forming self-aligned local-halo metal-oxide-semiconductor device |
US20040207011A1 (en) * | 2001-07-19 | 2004-10-21 | Hiroshi Iwata | Semiconductor device, semiconductor storage device and production methods therefor |
US6455383B1 (en) * | 2001-10-25 | 2002-09-24 | Silicon-Based Technology Corp. | Methods of fabricating scaled MOSFETs |
JP3828419B2 (ja) | 2001-12-25 | 2006-10-04 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR100485690B1 (ko) * | 2002-10-26 | 2005-04-27 | 삼성전자주식회사 | 모스 트랜지스터 및 그 제조방법 |
JP2004221204A (ja) * | 2003-01-10 | 2004-08-05 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
KR100493047B1 (ko) | 2003-02-13 | 2005-06-07 | 삼성전자주식회사 | 선택적 에피택셜 성장을 이용한 반도체 소자의 국부 배선형성 방법 |
US9563733B2 (en) * | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US8247846B2 (en) * | 2006-03-09 | 2012-08-21 | Tela Innovations, Inc. | Oversized contacts and vias in semiconductor chip defined by linearly constrained topology |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US7932545B2 (en) | 2006-03-09 | 2011-04-26 | Tela Innovations, Inc. | Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers |
US7908578B2 (en) * | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US8541879B2 (en) * | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US8225261B2 (en) * | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining contact grid in dynamic array architecture |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US8245180B2 (en) * | 2006-03-09 | 2012-08-14 | Tela Innovations, Inc. | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US8225239B2 (en) * | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining and utilizing sub-resolution features in linear topology |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US8448102B2 (en) * | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US7446352B2 (en) * | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US7943967B2 (en) * | 2006-03-09 | 2011-05-17 | Tela Innovations, Inc. | Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments |
US7763534B2 (en) * | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US20070221959A1 (en) * | 2006-03-22 | 2007-09-27 | International Business Machines Corporation | Structure and method for fabricating recessed channel mosfet with fanned out tapered surface raised source/drain |
US8286107B2 (en) * | 2007-02-20 | 2012-10-09 | Tela Innovations, Inc. | Methods and systems for process compensation technique acceleration |
US7979829B2 (en) | 2007-02-20 | 2011-07-12 | Tela Innovations, Inc. | Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US8453094B2 (en) * | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
KR101749351B1 (ko) | 2008-07-16 | 2017-06-20 | 텔라 이노베이션스, 인코포레이티드 | 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현 |
US9122832B2 (en) * | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US8138554B2 (en) * | 2008-09-17 | 2012-03-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with local interconnects |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
JP2012064854A (ja) * | 2010-09-17 | 2012-03-29 | Toshiba Corp | 半導体装置 |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
CN103730468B (zh) * | 2012-10-16 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法、sram存储单元、sram存储器 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5121186A (en) | 1984-06-15 | 1992-06-09 | Hewlett-Packard Company | Integrated circuit device having improved junction connections |
JPS63229746A (ja) * | 1987-03-19 | 1988-09-26 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JPH03141645A (ja) | 1989-07-10 | 1991-06-17 | Texas Instr Inc <Ti> | ポリサイドによる局所的相互接続方法とその方法により製造された半導体素子 |
US5691212A (en) | 1996-09-27 | 1997-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS device structure and integration method |
US6071783A (en) * | 1998-08-13 | 2000-06-06 | Taiwan Semiconductor Manufacturing Company | Pseudo silicon on insulator MOSFET device |
US6140191A (en) * | 1998-09-21 | 2000-10-31 | Advanced Micro Devices, Inc. | Method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions |
-
1998
- 1998-10-05 JP JP10282616A patent/JP2000114262A/ja active Pending
-
1999
- 1999-10-04 US US09/411,371 patent/US6335250B1/en not_active Expired - Fee Related
- 1999-10-05 TW TW088117151A patent/TW429476B/zh not_active IP Right Cessation
- 1999-10-05 KR KR10-1999-0042744A patent/KR100370331B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US6335250B1 (en) | 2002-01-01 |
KR20000028830A (ko) | 2000-05-25 |
JP2000114262A (ja) | 2000-04-21 |
KR100370331B1 (ko) | 2003-01-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |