TW411619B - Crown capacitor using a tapered etch of a damascene lower electrode - Google Patents
Crown capacitor using a tapered etch of a damascene lower electrode Download PDFInfo
- Publication number
- TW411619B TW411619B TW086116354A TW86116354A TW411619B TW 411619 B TW411619 B TW 411619B TW 086116354 A TW086116354 A TW 086116354A TW 86116354 A TW86116354 A TW 86116354A TW 411619 B TW411619 B TW 411619B
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- TW
- Taiwan
- Prior art keywords
- dielectric material
- bottom electrode
- contact hole
- etching
- patent application
- Prior art date
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- 239000003990 capacitor Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 claims abstract description 67
- 239000004020 conductor Substances 0.000 claims abstract description 30
- 239000000126 substance Substances 0.000 claims abstract description 29
- 238000005498 polishing Methods 0.000 claims abstract description 6
- 239000003989 dielectric material Substances 0.000 claims description 79
- 239000004065 semiconductor Substances 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 37
- 238000000151 deposition Methods 0.000 claims description 34
- 239000011229 interlayer Substances 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 31
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- 238000001312 dry etching Methods 0.000 claims description 9
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- 239000010937 tungsten Substances 0.000 description 1
- AKJVMGQSGCSQBU-UHFFFAOYSA-N zinc azanidylidenezinc Chemical compound [Zn++].[N-]=[Zn].[N-]=[Zn] AKJVMGQSGCSQBU-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Description
_<inu ^ 五、發明説明(1 ) 發明領域. 本發明關於製造一冠狀電容器之處理方法,其使用步帮 包括錐形蝕刻與化學機械式刨光於電容器内,以形成一底 部電極與一冠狀結構β如先前技術所需之無侧壁間隔係用 於本發明之製造方法中。 根據本發明,一錐形蝕刻係在一半導體結構之平坦化層 間電介體材質’例如糝雜之二氧化矽’内用以形成一凹槽 ,且執行在形成一“類似冠狀結構,,之接觸孔上。接觸孔與 選擇性冠狀則係以一導體材質覆蓋,其係藉化學機械式刨 光出圖案’以形成電容器之底部電極。本發明之處理方法 係簡單的’無需額外的處理步騾或如先前技術處理方法所 ft之侧壁間隔’且在平板電極形成之後,提供一大致平坦 表面。 經濟部中央梂準扃員工消費合作社印製 (請先W讀背面之注意事項再浐本頁) 線 含一金屬鑲崁底部電極之冠狀電容器結構亦由本發明提 供,其強調本發明之冠狀電容器結構具有比較傳統堆疊式 電容器之增加電極面積,而且,本發明之冠狀電容器具有 一大致平坦拓樸’其消除在先前技術内大致需要以製造具 有一平坦表面之冠狀電容器之額外的處理步驟需要, 先前技術 大致上,一半導體記憶裝置,例如一動態隨機存取記憶 體(DRAM)細胞包含多個憶體細胞,其用以儲存大量資訊 ,每一個憶體細胞包括儲存電荷之電容器與開啟與關閉電 -Ml I . 谷器之充電與放電之場效電晶體。在動態隨機存取記憶體 (DRAM)上之位元數以每三年約四倍增加,此已藉減少細 -4- 本紙張尺度通用中國國家標準(CNS Μ姑t格(2丨Ο X 297公慶) 經濟部中央樣準局貞工消費合作社印製 411619 A7 ___B7_ 五、發明説明(2 ) 胞尺寸達成’不幸的是較小的細胞尺寸亦較少面積可供製 造電容器。 大致上在動態隨機存取記憶體(DRAM)產生且構成每一 記憶細胞之每一電容器儲存電極,係與每一個相當的場效 電晶體在一起’其以一平坦的平板形狀形成在場效電晶體 上。因為此平坦的平板形狀,儲存電極表面積係因細胞尺 寸減少而驟然地減少,在此情況中,製造記憶細胞之傳統 式方法具有增加儲存電極表面積之困難,因為它們解決具 有一平坦的平板形狀之儲存電極形成。 為了增加電極面積與動態隨機存取記憶體(DRAM)室之 電容,已使用堆疊式電容器,例如描述在編號〇7_45718與 編號06- 224385之日本專利中,與冠狀電容器,例如描述 在 1991 年 T . Kaga f 人之 IEEE Trans. E〗ec. Dev.,第 38 章,第 255頁中與Ttseng之美國專利5,552,234號中。 傳統堆疊式電容器使用包括一底部電極之沉積與蝕刻之 簡單的處理步驟,以提供增加之電極面積,由先前技術處 理方法製造之傳統堆疊式電容器係顯示在圖i中,特別是 圖1顯示一半導體基板〗、形成在半導體基板丨表面上之 電介體材質2、一底部電極3、一節點電介體材質4及一 平板電極5。電介體材質2包含字元線6、位元線8與位 元線接觸7 β因為藉底部電極侧壁提供之額外的面積,此 傳統堆疊式電容器具有比較平坦電容器之增益面積。 惟,對一已知電介體材質而言,增加傳統堆疊式電容器 面積又唯—方法係使底部電極較高,其導引隔離形勢在陣 -5- ϋ張尺£適用中國規格(21〇謂公.一-- ----------^^-------訂------線 {請先閱讀背面之注意事項再"〜本頁) 41161^
五、發明説明(3) 經濟部中央榡準局男工消費合作社印製 歹J與支撐電路之間。此隔離形勢減少石版印刷技術之處理 窗’且可能需要一額外的化學機械式刨光步驟以再平坦化 而且當増加堆®電容器向度時,平坦化步驟逐漸 地變成昂貴的^ 對已知堆叠式電容器高度而言,冠狀電容器可提供比 簡單的堆疊式電容器更多的電極面積(8〇%以上)。雖然此 %極面積増加,先前技術冠狀電容器需要額外的處理步騾 ,其結果增加它們的製造費用。例如,在形成一簡單的冠 狀之處理方法,如揭示在Kaga等人上述參考,至少需要5 個額外的處理步驟。這些额外的處理步驟包括:心軸氧化 物/儿積與蝕刻,栓塞氧化物沉積與蝕刻與心軸氧化物/栓 塞氧化物移除。另外,拓樸(雖然比傳統堆疊式電容器較 少)係依然藉冠狀產生,其可在它們的製造中增加額外的 平坦化步騾。 在觀察上述有關傳統堆疊式電容器與傳統冠狀電容器之 缺點,其具有改進新處理方法之需要,其提供增加電極面 積與一大致平坦的拓樸至一電容器’而無需許多額外的處 理步驟。 發明摘要 本發明义一目地係提供製造含一金屬鑲崁底部電極之冠 狀電容器之處理方法,其具有如比較無使用無側壁間隔之 傳統式堆疊電容器之增加面積g 本發明之另一目地係提供製造一冠狀電容器之處理方法 ,其具有大致如標準冠狀電容器之同等的電極面積,但不 -6 - 本纸張尺度適用中國國家標準(CNS ) Α4規格(210 X 29了公瘦) _____ ---;-- J---'- ^------Ί ^-------蛛 (婧先Ή讀背希之注意事項^本育> A7 B7 411619 五、發明説明(4 ) 需要使用額外的處理步驟,如比較製造冠狀電容器之傳統 式處理方法。 本發明之又一目地係提供直接地造成一平坦化拓樸之方 .法,為了消除在先前技術處理方法内大致需要製造冠狀電 容器或堆疊式電容器之額外的處理步驟需要d 這些和其他目地一樣係藉本發明完成,其使用包括錐形 蚀刻與化學機械式刨光以形成底部電極與冠狀之步驟。 特別是,在本發明之實例中,提供製造含—金屬鑲崁底 部電極之冠狀電容器之處理方法,其包含以下步驟: (a) 提供一半導體結構,包含具有適當的擴散與隔離區域 之一半導體基板、至少一字元線、至少—位元線、至少一 連接該位元線至該半導體基板之位元線接觸、與一平坦化 層間電介體材質,其中該平坦化層間電介體材質係在該半 導體基板頂部,且圍繞該位元線、該位元線接觸與該字元 線; (b) 形成一接觸孔在介於該字元線間之該平坦化層間電 介體材質内以曝露該半導體基板之面積; (c) 形成一凹槽在該接觸孔之該平坦化層間電介體材質内 ’其中該凹槽不完全延伸過該接觸孔; (d) 沉積一底部電極材質進入該接觸孔與該凹槽其中 該底部電極材質包含一導體; (e) 將化學機械式刨光之步驟⑷提供之底部電極材質製 成圖案; (f) 沉積一節點電介體材質在該圖案底部電極材質上,且 -7- 本紙張尺度適用中國國家標準(CNS ) A4規格(2丨0X297公釐) n n<n n *^i - I il. - .n n n I ΙΓ 丁 _? _ u ……. 4 i 招 f請先聞讀背面之注意事項再^萬本頁) 經濟部中央標準局貝工消費合作社印« — 41Ϊ619 五、發明説明(5) 在該平坦化層間電介體材質上; (g) 在有效地擴散氧進入該節點電介體材質條件之下,選 擇地將步驟(f)内提供之結構熱氧化;及 (h) 沉積一平板電極在該節點電介體材質或該熱式氡化 的節點電介體材質上。 其強調在本發明步驟(c)内,形成園繞接觸孔之“冠狀” 或“類似冠狀”結構。“冠狀”或“類似冠狀,,一詞在此係用 以表示具有“w”文字之形狀結構,即中間尖峰係錐形,大 致從約80纟約88度谷底,注意此錐形可藉本發明步螺⑷ 或步驟(b)提供。必要時冠狀頂部亦可為凹陷。 本發明另一内容係關於一冠狀電容器,其係使用本發明 之處理方法製造。因此’本發明之電容器包含一金屬鑲崁 的底部電極,其比傳統式堆叠電容器具有較大的表面。 _圖式簡單說明 圖1係藉傳統式方法製成之先前技術堆疊式電容 圖。 經濟部中央標準局貝工消費合作社印装 ------------^—裝'-- ί請先閲讀背面之注意事項再t本頁) 線丨·^--- 。圖2⑷·⑷係含一摻雜之多碎元素底部電極之冠狀電容 器剖面圖,其係依據本發明各式處理步驟製造。 圖3係含一複合式電極之冠狀電容器剖面圖。 圖4係含藉使用本發明各式處理步驟之化學機械式削光 製造之複合底部電極之冠狀電容器剖面圖。 圖5係含藉化學機械式削光製造之底部電極與藉 乾燥蝕刻製造之矽接觸線之冠狀電容器剖面圖。 ^ i明詳細說明 -8 - 本紙張尺歧財關家料 經濟部中央樣準局負工消費合作社印裝 411619 A7 ____B7 五、發明説明(6 ) 本發明現將參考隨附圖式詳細描述,其中相同參考數字 係用於圖中相同的元件。特別是,本發明提供製造一冠狀 電容器之處理方法’而非係太致先前技術處理方法需要以 獲得一平坦的結構之任何侧壁間隔或額外的處理步驟之需 要。 首先參考圖2 (a),其顯示一半導體結構,本發明係用以 製造冠狀電容器。特別是根據本發明提供一半導體結構, 其包含一半導體基板12、至少一字元線14、至少一位元 線16、至少一連接位元線16至半導體基板12之位元線接 觸線18、與一平坦化層間電介體材質2〇 ,其係在半導體 基板12頂部且圍繞字元線14、位元線16與位元線接觸線 18。製造此半導體之方法係習於此技者所熟知,因此將不 在此詳細討論,例如,參看T Kaga等人在上文描述之參考 資料’其内容係在此供作參考。 半導體基板12包含適當的擴散與隔離區域,其係埋入 基板12中。為圖面清潔,這些區域和其他一樣未顯示在本 發明圖式。可用在本發明之半導體基板包括但不限定的有 矽、鍺化矽或砷化鎵》以半導體基板而言’矽在本發明中 最佳。 根據製造之冠狀電容器,用在本發明之半導體基板可為 P型或N型,半導體基板可使用習於此技者所熟知技術製 造。 如習於此技者所知,位元線16係藉位元線接觸線丨8連 接至一擴散區域。用在本發明之位元線接觸線係由包括但 -9- 本紙張尺度適用中國國家橾隼(CNS > A4規格(210X297公ft )---- ---------裝------訂-------線 (請先W讀背*之注意事項再填贫‘本頁) 經濟部中夬棣準局貝工消费合作社印製 A7 _____B7 _ 五、發明説明(7 )
不限之聚合攻、碎酸與例如鎮、路、銘 '銅、欽、氮化敛 等金屬之傳統傳導性材質組成。以這些傳導性材質而言, 位元線接觸線18係大致由聚合珍組成D 字元線14包含由傳導性材質例如聚合矽組成之一基底 22 ’與由一傳統式絕緣材質例如四氮化三矽構成之層24在 該基底頂部。 用在本發明之平坦層間電介體材質包括但不限定的有二 氧化梦、硼-及/或鱗-摻雜之二氧化矽、金屬氧化物例如 二氧化鈦、五氧化二钽、三氧化鈦(部、锶)等,與其混合 物。這些電介體材質可藉習於此技者所熟知之技術增加、 沉積或反應。在此描述之層間電介體材質中,二氧化矽、 硼-及/或磷-摻雜之二氧化矽係極佳的。 根據本發明處理之下一個步驟,其係顯示在圖2(b)中, 一接觸孔26係形成在介於字元線μ間之層間電介體材質 2〇内,以曝露該半導體基板12之面積28。接觸孔26係藉· 使用標準石版印刷技術與各向異性蝕刻技術之圖案式層間 電介體材質20形成,其以比較半導體基板之高選擇性蝕刻 層間電介鱧材質。例如’當電介體材質係由矽元素組成, 各向異性蝕刻技術必須有一選擇性以蝕刻至少1〇:丨之二氧 化石夕。可用於形成接觸孔26適宜的各向異性蝕刻技術係離 子束姓刻(IBE)、反應離子蝕刻(RIE)、電漿蝕刻或雷射刻 製。每一個前述之各向異性蝕刻技術係習於此技者所熟知 。上述之各向異性蝕刻技術中’ rIE係最適合用在本發明 以形成接觸孔26。接觸孔26可為正交的,即垂直的,至 -10- 中圉ϋ家標準(CNS > A4胁(21〇><297公着) --------厂裝_------^訂------線 (請先W讀背面之注$項再填/、本頁) 411619 A7 B7 五、發明説明(8 ) 層間電介體材質20之平面或,在本發明另一實例中其可 呈—錐形。當接觸孔係錐形時,錐形大致係從約乃至防 度。本發明實例係顯示在圖2(b) _與2(c)1中。 在本發明之下一個步驟,其係顯示在圖2(c)中,一凹槽 30係藉使用標準石版印刷技術與上述之各向異性蝕刻技術 之一形成在層間電介體材質20内。當接觸孔係非錐形時, 用在本發明此步驟之各向異性姓刻技術應在凹槽内產生一 些錐體32 ^理想是錐形蝕刻應在層間電介體材質2〇内提 供從約75至89度之角度,其提供圍繞接觸孔26之“冠狀” 或“類似冠狀’,結構。當接觸孔26係錐形時,其必須使凹 槽成錐形,參閱圖2(c) ·所示實例。 大致上’ RIE係用在本發明之此步驟中,其造成增加電 極面積。本發明此步驟之蝕刻深度依據所需的電容器之電 容’但其大致係形成約1〇〇至約10 〇〇() nm。較好是蝕刻深 度係約200奈米(nm)。應注意在位元線16上之層間電介體 材質20厚度必須大於凹槽3〇深度,以確保位元線16係隔 離開電容器。 經濟部中央標準局負工消费合作社印製 (請先閲讀背面之注意事項再^ί本頁) 可用於形成錐體32之RIE —型式係一聚合蝕刻,其包含 使用含碳與氟之蝕刻氣體,例如三氟碳氫、八氟四碳,而 在層間電介體材質製成圖案。 在本發明另一實例中’冠狀之頂部可凹陷,若有必要, 使用濕式蝕刻或乾式蝕刻之簡易各向異性蝕刻。選擇蝕刻 時間以提供從約10至500 nm之凹陷範圍,更好是#刻時間 提供一約100 nm之凹陷,本發明此實例未顯示在圖式中》 -11 - 本紙張尺度通用中國國家標準(CNS ) Α4規潘(210Χ297公| ) 經濟部中央標準局貝工消費合作社印裂 411619 at — B7 五、發明説明(9 ) 當濕式蝕刻使用在本發明以提供凹陷表面時,化學蝕刻 係從由過氧化氫、鉻酸、磷酸、醋酸、氩氟酸等组成之群 組選擇這些單獨或含水之化學姓刻劑混合物亦係包含在 此°化學蝕刻劑亦可緩衝至使用已知緩衝劑之希望的pH 值。上述之化學蝕刻劑’稀釋或緩衝hf係極佳的。 a乾式蚀刻係用以提供在冠狀頂部内之凹陷時,大致係 使用四氟化碳氣體之化學乾式蝕刻劑。 本發明下一個步驟係顯示在圖2(d)中’根據本發明此步 驟,形成本發明電容器底部電極之導體材質34係沉積入接 觸孔且入凹槽且其後藉化學機械式刨光製成圖案。可沉積 以形成底部電極之適宜導體包括但不限定的有摻雜之聚合 矽、氮化欽、鈥鋁氮、赵碎氮、與碎化物例如二碎化鎢、 二砂化钻等。聚合矽導體係與包括磷、砷或銻、或一鱗_ 摻雜劑例如B之η -摻雜劑處理,這些材質,在本發明中 與坤或鱗摻雜之聚合矽係極佳的。 形成底部電極之,體係藉使用習於此技者所熟知之沉積 技術沉積’用在本發明極佳的沉積技術係低壓化學蒸發氣 沉積(LPCVD),其以約1〇至80 Pa之壓力範圍進行約5至 60分鐘之週期周週時間。 在以上沉積條件之下’導體之連續層係形成具有從約2〇 至500 nm之厚度’更好是’低壓化學蒸發氣沉積(lpcvd) 處理方法提供具有約1 〇〇 nm厚度之導體層。 沉積導體材質之後’沉積之導體係易於化學機械式刨光 ,其技術係習於此技者所熟知,以使一半導體裝置之表面 -12- 本紙張尺度適用中國國家標準(CNS ) A4規格(2I0X297公釐) .---— 装------1TI_-----.^ {請先聞讀背面之注意事項再Ϊ本頁) 411619 A7 經濟部中央標準局負工消費合作社印繁 B7五、發明説明(10) 平坦。像這樣的處理方法係描述在Jaso等人之美國專利 5,246,884號中,其内容在此供作參考。 平坦化底部電極3 4之後,一節點電介體材質36係沉積 在底部電極34表面與層間電介體材質20上,且然後選擇 在擴散氧進入節點電介體材質條件之做氧化處理。其應注 意當使用高電介體材質例如三氧化鈦(鋇、鳃)時,不會發 生此氧化步驟。本發明此步驟係顯示在圖2(e)中可用在 即發明之適宜節點電介體材質包括例如四氧化三矽、氧氮 化物、五氧化二艇、二氧化鈦之電介體材質,在本發明中 這些材質以四氧化三矽較佳。 節點電介體材質係使用習於此技者所熟知之傳統式沉積 技術,以極佳的化學蒸發氣沉積沉積。使用標準沉積條件 時,節點電介體材質大致具有從約2至15 nm之厚度,最 好是5 nm ° 沉積節點電介體材質之後,結構係選擇在約600 °至 1100 °C之溫度範圍下從約10秒至30分鐘之時間做熱氧化 ,其條件係有效以造成氧擴散進入節點電介體材質。例如 ,當四氧化三矽用為節點電介體材質時,以上之熱氧化條 件造成一氮氧矽(SiOxNy)層。 再參考圖2(e),其顯示一平板電極38,其係沉積在氧化 節點電介體材質36之表面上。可用在本發明如上部電極之 適宜平板材質包括聚合矽、矽化物與例如鎢、路、鋁、鉑 、鈀、氮化鈦等傳導性金屬,這些材質以聚矽為平板材質 較佳。 -13-' (請先閲讀背面之注意事項再^L,本頁) -裝 訂 本紙張尺度適用中國國家標準(CNS ) Μ規格U10X29·?公釐) 411619 at B7 五、發明説明(11) 平板電極係使用上述之沉積技術,例如低壓化學蒸發氣 沉積(LPCVD)、或物理蒸發氣沉積(PVD)沉積,在條件之下 其足以形成具有從約50至500 nm厚度之層。更好是,板 電極係沉積至一約100 nm之厚度。 平板電極與節點電介體然後可以包含依循節點電介體 RIE之平板電極RIE之石版印刷術步驟製成圖案。 藉本處理方法形成之最終冠狀電容器係顯示在圖2(e)中 ,其應注意本發明冠狀電容器可包括一或多個線狀層。這 些額外的線狀層惟未顯示在圖式中。 經濟部中央標準局員工消费合作社印製 (請先閲讀背面之注意事項再^ν-,本頁) 當高電介體系數材質用在本發明時,例如三氧化鈦(鋇 、锶),顯示在圖2 (a) - (e)之處理方法可如顯示修改如圖3 者。特別是,使用在此以上描述之條件,沉積導體材質進 入接觸孔26之後,一貴金屬,較佳是銥,係藉物理蒸發氣 沉積(PVD)沉積在底部電極34上。再者,結構係鍛煉在從 約500 °至700 °C之溫度於從約10秒至30分鐘之時間。這 些鍛煉條件足以造成在貴金屬與導體材質間之反應形成一 複合式電極40。例如,當多.梦元素係作為底部電極之導體 材質,且銥係作為貴金屬,以上鍛煉條件係足以形成二矽 化短在鍊與多矽元素接觸之區域内。 無反應之貴金屬則使用一濕式蝕刻移除,其蝕刻貴金屬 在一比複合式電極40非常高的比率。作為此目地之適宜蝕 刻包括:鹽酸:過氧化氫或硝酸:水。最終結構則藉沉積 節點電介體材質34在複合式電極40上選擇性提供熱式氧 化結構,且沉積一平板電極36在結構上,使用在此以上描 -14- 本紙張尺度適用中國國家標準(CNS > Α4規格(210Χ29?公釐) 經濟部中央橾準局員工消費合作社印装 411619 at • B7 五、發明説明(12) 述之程序。 本發明其他實例顯示在圖4與5中。當亦使用高電介體 系數材質時,這些實例亦可應用,且其包含多重導體層, 接觸攻之材質及/或一選擇性屏柵層材質,與一電極材質 。特別是,圖4顯示含藉化學機械式刨光製造之複合底部 電極之冠狀電容器剖面圖’然而圖5顯示含藉化學機械式 刨光製造之底部電極與藉化學式乾燥蝕刻製造之梦接觸之 冠狀電容器刻面圖。顯示在圖4與5之冠狀電容器製造係 在此以下描述。部分地或完全地沉積導體材質32在接觸孔 26與凹槽内之後,沉積之導體材質32則藉習於此技者所熟 知之方法製成圖案。特別是’圖4之導體材質32係藉化學 機械式削光製成圖案,然而圖5之導體材質,其係衹部分 地沉積進入接觸孔26 ’係在條件之下藉化學式乾燥蝕刻製 成圖案,其係有效地在接觸孔内造成導體之凹槽。再者, 一選擇性屏柵層42係藉習知技術例如pvd或CVD沉積, 用在本發明之選擇性屏柵層必須防止氧到達導體材質,以 及防止導禮材質進入與沉積在屏拇層上之金屬接觸。可用 在本發明之適宜屏柵材質包括:钽矽氮、鈦鋁氮、鈇氮、 與各種矽化物。其次’包含一金屬,例如鉑、鈀、釕與金 屬氧化物之電極材質44係藉使用技術習知條件之物理蒸發 氣沉積或CVD沉積在選擇性屏柵材質或導體之頂部上。電 極材質44則係化學機械式刨光製成圖案,節點電介體% 與平板電介體38材質則係使用上述之條件與技術沉積在電 極材質與平坦化層間電介體材質20之頂部上。 -15- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) ---------·1裝'------^訂I ------線—卜 <請先閲讀背面之注意事項再填VST本頁) 4ti619 A7 B7五、發明説明(13) ~ 如上述’本發明之處理方法比先前技術具有許多的優點 。例如’比較傳統堆疊式電容器,其不具額外的處理步騾 提供增加電極面積(30%或以上)。比較冠狀電容器,其提 供非常簡單之處理方法,雖然比—冠狀電容器具較少的電 極面積。另外’本發明之冠狀電容器結構對後序的處理過 程提供一大致平坦的表面。相反地, 本發明雖已特別地顯示與描述於有關較佳實例,習於此 技者應瞭解前文與在形式與細節之改變可在此製成,而皆 未離開本發明之精神與範圍。 ----,-------^—裝------:-訂 I.-----線 (請先閲讀背面之注意事項再填頁) 經濟部中央標準局貞工消费合作社印製 -16- 本紙張尺度適用中國國家標準(CNS > A4規格(210X297公釐)
Claims (8)
- «1101» «1101»須請委員明示,本衆修正扒是i^s;:吏原· 英文申請專利範圍蜂正本(88年5月) ROC (Taiwan) Patent Application No. 86116354 Amended Claims HVlavl 19991_ 1, A process for fabricating a crown capacitor comprising the steps of: (a) providing a semiconductor structure comprising a semiconductor substrate, at least one wordline^ at least one bitline, at least one bitline contact for connecting said bitline to said semiconductor substrate, and a planarized interlevel dielectric material, wherein said planarized interlevel dielectric material is on top of said semiconductor substrate and surrounds said bitline, said bitline contact and said wordline; (b) forming a contact hole in said planarized interlevel dielectric material between said wordlines to expose an area of said semiconductor substrate;- (c) forming a trough in said planarized interlevel dielectric material at said contact hole, said troughdoes not extend all the way through said contact hole, wherein either step (b) or {c) tapered sidewalls are provided, thereby forming a crown-shaped region in said planarized interlevel dielectric material; (d) depositing a bottom electrode material into said contact hole and said through; {e) patterning the bottom electrode material provided in step {d) by chemical mechanical polishing; {f) depositing a node dielectric material on said patterned bottom electrode material; U:\PTSUAN\86\86116354.DOC 經濟部中央標準局貝工消費合作社印裝 412619 S D8 六、申請專利範圍 1.—種製造一冠狀電容器之方法’包含以下步驟: (a) 提供一半導體結構,包含一半導體基板、至少一 字元線、至少一位元線、至少一連接該位元線至該半 導體基板之位元線接觸線、及一平坦化層間電介想材 質,其中該平坦化層間電介體材質係在該半導體基板 顶部,且圍繞該位元線、該位元線接觸線與該字元線; (b) 形成一接觸孔在介於該字元線間之該平坦化層間 電介體材質内,以曝露該半導體基板之面積; (c) 形成一凹槽於該接觸孔之該平坦化層間電介體材 質内’該凹槽不完全延伸過該接觸孔,其中在.步驟(b) 或步驟(c )中提供錐形侧壁,因而在該平坦化層間電介 體材質中形成一冠狀區域; (d) 沉積一底部電極材質進入該接觸孔與該凹槽; (e) 將化學機械式刨光步驟⑷提供之底部電極材質製 成圖案; (0 >儿積一卽點電介體材質在該製成圖案之底部電極 材質上; (g) 在有效地擴散氧進入該節點電介體材質條件之下 ’選擇地將步驟(f)内提供之結構熱氧化;及 (h) 沉積一平板電極在該節點電介體材質或該熱式氧 化的節點電介體材質上。 2 -如申請專利範圍第丨項之方法,其中步騾(b)内該接觸 孔係藉以石版印刷術在該層間電介體材質形成圖案, -17· 本紙張U適用t國因家標準(c叫从胁(2丨〇 χ Μ7公羞) -- (请先閲讀背面之注意事項再填玲本頁) V-」J J ,1Τ 經濟部t央捸隼局貝工消費合作社印製 朗I ---~_____D8 申請專利範圍 且令形成圖案之層間電介體材質做各向異性蝕刻。 如申請專利範圍第2項之方法’其中該各向異性蚀刻 係從離子束链刻、雷射刻製、電裝蚀刻及反應離子蚀 刻组成之群組選擇。 ’如申請專利範園第3項之方法’其中該各向異性蝕刻 係反應性離子蚀刻D 5. 如申請專利鹌圍第1項之方法,其中步驟(b)内提供之 該接觸孔相對該層間電介體層具有從約75至89度角度 之錐形。 6. 如申請專利範圍第1項之方法,其中該凹槽係藉以石 版印刷術而在該層間電介體材質形成圖案,且令該層 間電介體材質做各向異性蝕刻。 7 -如申請專利範圍第6項之方法,其中該各向異性蝕刻 係在有效地以產生一些錐形於電介體材質之該接觸孔 内條件下實施,以提供一冠狀結構。 8 ·如中請專利範圍第1項之方法’其中該錐形侧壁係約 75至89度之角度。 9 -如申請專利範圍第1項之方法,其中該錐形側壁係藉 使用含碳與氟蝕刻氣體之反應性離子蝕刻提供。 10. 如申請專利範圍第7項之方法,其中該蚀刻氣體係 CHF3、C4F8。 11. 如申請專利範圍第1項之方法,其中該凹槽係於步驟 (d)之前以一濕、式触刻或一乾式蚀刻凹陷。 -18- 本紙張ΛΑϋ财S ®家料(CNS ) A刪μ ( 210 X 297公釐)' ~ (請先閲讀背面之注^^項再填寫本頁) •1Τ φ 4li6j9 A8 B8 C8 D8 六、申請專利範圍 經濟部t央樣率局β:工消費合作社印製 12.如申$專利範圍帛1!項(方法,其中該濕式蚀刻係使 用由H2〇2、鉻酸、磷酸、醋酸、氫氟酸與其混合物 組成群組選擇之化學蝕刻劑進行。 13·如申請專利範圍第12項之方法 用前係稀釋在水中或緩衝。 14. 如申請專利範固第1S項之方法 稀釋的氫氟酸或緩衝的氫氟酸。 15. 如申請專利範圍第11項之方法 用CF4氣體。 16. 如申凊專利範園帛【項之方法’其中該底部電極係藉低 壓化學蒸發氣沉積(LPCVD)在約10至8〇Pa壓力進行約 5至約60分鐘之時間。 17·如申請專利範園第1項之方法,其中步騾(g)係在約600。 至1100 C之溫度範圍進行約10秒至3〇分鐘之時間。 18. 如申請專利範圍第i項之方法,其中在步騾⑷之後’ 以下額外的步驟係優先於步驟(f>(g)沉積一貴金屬至該 底部電極材質之前進行;在有效地形成一複合式電極 條件下鍛煉該貴金屬及該底部電極材質;以及濕式蝕刻 複合式電極以移除未反應之貴金屬。 19, 如申請專利範固第i項之方法’其中以下额外的步騾係 在步騾(f)之前執行,即選擇性沉積一屏柵層在該圖案 底部電極材質上;然後沉積從鉑、他、釕與氧化物組 成群組選擇之金屬於該選擇性屏柵層之頂部上或在該 其中該化學蝕刻劑使 其中該化學蝕刻劑係 其中該乾式蝕刻係使 -19(請先閏讀背面之注意事項再填寫本頁) 订 嗥. 經濟部中央標準局貝工消費合作社印製 4U619 Α8 Β8 C8 ------—08__ 六、申請專利範固 圖案底部電極材質上η 20. 如申請專利範圍第i项之方法,其中步驟⑷之該底部 電極材質係藉部分地沉積一導體進入接觸孔形成;在 有效地造成-凹陷於凹槽中之條件下,藉乾式蚀刻對 孩導體製成圖案;選擇性沉積一屏柵層在該圖案導體 上;沉積從舶、把、釘與氧化物组成群組選擇之金屬 於該選擇性屏栅層之頂部上或在該導體上;及進行步 驟(f) - (h)。 21. —種冠狀電容器結構,包含: (a)—半導體結構,包含一半導體基板、至少一字元 線、至少一位元線、至少一連接該位元線至該半導體 基板之位7G線接觸線、及一平坦化層間電介體材質, 其中該平坦化間層電介體材質係在該半導體墓板頂部 ,且圍繞遠位元線、該字元線與該位元線接觸線,且 包含具有冠狀之接觸孔與凹槽; 0) —圖案式底部電極材質’係部分地或完全地包含 在該接觸孔,及必要時在該凹槽内; (c) 選擇性之一屏柵層,形成在該圖案式底部電極上 > (d) 選擇性之金屬層,形成在選擇性屏柵層或圖案式 底部電極上,其中該金屬層係從鉑、鈀、釕與氧化物 組成群組選擇之金屬; (e) —節點電介體材質’係在(b)、(c)或⑷與該層間電 -20- 本紙張尺度璁用中國菌家梯準(CNS ) Α4規格(210Χ297公釐) (椅先閲讀背面之注意事項再填寫本頁) —訂 嗥 *. m. (—^1 I I ABCD 六、申請專利範圍 介體材質之頂部;及 (f) 一平板電極,沉積在該節點電介體材質上。 (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標隼局員工消費合作社印裝 -21 - 本紙張尺度逍用中國國家揉準(CNS > A4規格(210X297公釐) «1101» «1101»須請委員明示,本衆修正扒是i^s;:吏原· 英文申請專利範圍蜂正本(88年5月) ROC (Taiwan) Patent Application No. 86116354 Amended Claims HVlavl 19991_ 1, A process for fabricating a crown capacitor comprising the steps of: (a) providing a semiconductor structure comprising a semiconductor substrate, at least one wordline^ at least one bitline, at least one bitline contact for connecting said bitline to said semiconductor substrate, and a planarized interlevel dielectric material, wherein said planarized interlevel dielectric material is on top of said semiconductor substrate and surrounds said bitline, said bitline contact and said wordline; (b) forming a contact hole in said planarized interlevel dielectric material between said wordlines to expose an area of said semiconductor substrate;- (c) forming a trough in said planarized interlevel dielectric material at said contact hole, said troughdoes not extend all the way through said contact hole, wherein either step (b) or {c) tapered sidewalls are provided, thereby forming a crown-shaped region in said planarized interlevel dielectric material; (d) depositing a bottom electrode material into said contact hole and said through; {e) patterning the bottom electrode material provided in step {d) by chemical mechanical polishing; {f) depositing a node dielectric material on said patterned bottom electrode material; U:\PTSUAN\86\86116354.DOC 411619 (g) optionally, subjecting the structure provided in step (f) to thermal oxidation under conditions effective to diffuse oxygen into said node dielectric material; and (h) depositing a plate electrode on said node dielectric material or said thermally oxidized node dielectric material.
- 2- The process of Claim 1 wherein said contact hole in step (b) is formed by patterning said interlevel dielectric material by lithography and subjecting the patterned interlevel dielectric material to anisotropic etching. 3, The process of Claim 2 wherein said anisotropic etching is selected from the group consisting of ion beam etching, laser ablation, plasma etching and reactive ion etching.
- 4. The process of Claim 3 wherein said anisotropic etching is .reactive ion etching, 5· The process of Claim 1 wherein said contact hole provided in step (b) has a taper of from about 75 to about 89 degrees relative to said interlevel dielectric layer, 6 * The process of Claim 1 wherein said trough is formed by patterning the interlevel dielectric material by lithography and anisotropic etching said interlevel dielectric material. U:\PTS\JAN\86\86116354.DOC -2- 411619 Ί· The process of Claim 6 wherein said anisotropic etching is carried out under conditions effective to produce some tapering in the interlevel dielectric material at said contact hole to provide a crown structure. 8* The process of Claim 1 wherein said tapered sidewalls is at an angle from about 75 to about 89 degrees. 9· The process of claim 1 wherein said tapered sidewalls is provided by reactive ion etching utilizing an etchant gas that contains carbon and fluorine. 10* The process of Claim 9 wherein said etchant gas is CHF3 or C^Fe. 11* The process of Claim 1 wherein said trough is recessed with either a wet etch or a dry etch prior to step (d). 12· The process of Claim 11 wherein said wet etch is conducted using a chemical etchant selected from the group consisting of H202/ chromic acid, phosphoric acid, HF and mixtures thereof. 13· The process of Claim 12 wherein said chemical etchant is diluted in water or buffered prior to use·
- 14, The process of Claim 13 wherein said chemical etchant is diluted HF or buffered HF. U:\PTSUAN\86\86116354.DOC -3- 411619 15· The process of Claim 11 wherein said dry etch is conducted using CF4 gas. 16· The process of Claim 1 wherein said bottom electrode is deposited by Low Pressure Chemical Vapor Deposition (LPCVD) at a pressure from about 10 to about 80 Pa for a period of time from about 5 to about 60 minutes. 17· The process of Claim 1 wherein step (g) is conducted at a temperature of from about 600° to about 1100°C for about 10 seconds to about 30 minutes.
- 18. The process of Claim 1 wherein after step (e) the following additional steps are conducted prior to steps (f)-(g) depositing a noble metal to said bottom electrode material; annealing said noble metal and said bottom electrode material under conditions effective to from a compound electrode; and wet etching the compound electrode to remove unreacted noble metal.
- 19. The process of Claim 1 wherein prior to conducting step (f) the following additional steps are performed, optionally, deposition a barrier layer on said patterned bottom electrode material; and then depositing a metal selected from the group consisting of Ft/ Pd; Ru and oxides thereof on top of said optional barrier layer or on said patterned bottom electrode material*
- 20. The process of Claim 1 wherein said bottom electrode material or step (ά) is formed by partially depositing a conductor into said contact hole; patterning said conductor by dry etching under U:\PTS\JAN\86\86116354.DOC 411619 conditions effective to cause a recess in the trough; optionally, depositing a barrier layer on said patterned conductor; depositing a metal selected from the group consisting of Pt^ Pd, Ru and oxides thereof on top of said optional barrier layer or on said conductor; and then conducting steps (f)一(h)*
- 21, A crown capacitor structure comprising: (a) a semiconductor structure comprising a semiconductor substrate, at least one wordline, at least one bitline, at least one bitline contact for connecting said bitline to said semiconductor substrate, and a planarized interlevel dielectric material, wherein said interlevel dielectric material is on top of said semiconductor substrate and surrounds said bitline, wordline and bitline contact, and contains a contact hole and a trough having a crown-like shape; (b) a patterned bottom electrode material which is contained partially or fully in said contact hole and, if necessary, said trough; (c) optionally, a barrier layer formed on said patterned bottom electrode; (d) optionally, a metal layer formed on either the optional barrier layer or the patterned bottom electrode, wherein said metal layer is a metal selected from the group consisting of Pt, Pd, Ru and oxides thereof; (e) a node dielectric material which is on top of (b), (c) or (d) and said interlevel dielectric material; and {f) a plate electrode deposited on said node dielectric material. U:\mUAN\86\86116354.DOC -5-
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US08/827,339 US5879985A (en) | 1997-03-26 | 1997-03-26 | Crown capacitor using a tapered etch of a damascene lower electrode |
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US10497519B1 (en) | 2018-09-27 | 2019-12-03 | International Business Machines Corporation | Back-end-of-the line capacitor |
US10790001B2 (en) | 2019-01-04 | 2020-09-29 | International Business Machines Corporation | Tapered VA structure for increased alignment tolerance and reduced sputter redeposition in MTJ devices |
TWI720886B (zh) | 2020-05-08 | 2021-03-01 | 力晶積成電子製造股份有限公司 | 多層電容元件以及多層電容元件的設計方法 |
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US5235199A (en) * | 1988-03-25 | 1993-08-10 | Kabushiki Kaisha Toshiba | Semiconductor memory with pad electrode and bit line under stacked capacitor |
US5068707A (en) * | 1990-05-02 | 1991-11-26 | Nec Electronics Inc. | DRAM memory cell with tapered capacitor electrodes |
US5192703A (en) * | 1991-10-31 | 1993-03-09 | Micron Technology, Inc. | Method of making tungsten contact core stack capacitor |
US5150276A (en) * | 1992-01-24 | 1992-09-22 | Micron Technology, Inc. | Method of fabricating a vertical parallel cell capacitor having a storage node capacitor plate comprising a center fin effecting electrical communication between itself and parallel annular rings |
JPH0777237B2 (ja) * | 1993-01-04 | 1995-08-16 | 日本電気株式会社 | 半導体記憶装置及びその製造方法 |
JPH06224385A (ja) * | 1993-01-25 | 1994-08-12 | Mitsubishi Electric Corp | 半導体記憶装置とその製造方法 |
KR960006822B1 (ko) * | 1993-04-15 | 1996-05-23 | 삼성전자주식회사 | 반도체장치의 미세패턴 형성방법 |
JPH0730077A (ja) * | 1993-06-23 | 1995-01-31 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP3227919B2 (ja) * | 1993-07-30 | 2001-11-12 | ソニー株式会社 | スタック型dramおよびその製造方法 |
KR970000228B1 (ko) * | 1993-08-30 | 1997-01-06 | 현대전자산업 주식회사 | 디램 캐패시터의 제조방법 |
KR100231593B1 (ko) * | 1993-11-19 | 1999-11-15 | 김주용 | 반도체 소자의 캐패시터 제조방법 |
KR950014980A (ko) * | 1993-11-19 | 1995-06-16 | 김주용 | 반도체 소자의 캐패시터 형성방법 |
KR950021644A (ko) * | 1993-12-31 | 1995-07-26 | 김주용 | 반도체 기억장치 및 그 제조방법 |
US5521112A (en) * | 1994-10-05 | 1996-05-28 | Industrial Technology Research Institute | Method of making capacitor for stack dram cell |
KR0147655B1 (ko) * | 1995-07-13 | 1998-08-01 | 김광호 | 반도체 장치의 캐패시터 제조방법 |
US5550076A (en) * | 1995-09-11 | 1996-08-27 | Vanguard International Semiconductor Corp. | Method of manufacture of coaxial capacitor for dram memory cell and cell manufactured thereby |
US5552334A (en) * | 1996-01-22 | 1996-09-03 | Vanguard International Semiconductor Company | Method for fabricating a Y-shaped capacitor in a DRAM cell |
US5607874A (en) * | 1996-02-02 | 1997-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a DRAM cell with a T shaped storage capacitor |
-
1997
- 1997-03-26 US US08/827,339 patent/US5879985A/en not_active Expired - Fee Related
- 1997-11-04 TW TW086116354A patent/TW411619B/zh not_active IP Right Cessation
- 1997-12-02 KR KR1019970065341A patent/KR100286527B1/ko not_active IP Right Cessation
-
1998
- 1998-03-25 JP JP07674698A patent/JP3357599B2/ja not_active Expired - Fee Related
- 1998-10-30 US US09/183,416 patent/US6222219B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP3357599B2 (ja) | 2002-12-16 |
KR100286527B1 (ko) | 2001-04-16 |
JPH10275903A (ja) | 1998-10-13 |
US5879985A (en) | 1999-03-09 |
KR19980079505A (ko) | 1998-11-25 |
US6222219B1 (en) | 2001-04-24 |
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