TW387105B - Double-diffused MOS transistor and method of fabricating the same - Google Patents

Double-diffused MOS transistor and method of fabricating the same Download PDF

Info

Publication number
TW387105B
TW387105B TW087106901A TW87106901A TW387105B TW 387105 B TW387105 B TW 387105B TW 087106901 A TW087106901 A TW 087106901A TW 87106901 A TW87106901 A TW 87106901A TW 387105 B TW387105 B TW 387105B
Authority
TW
Taiwan
Prior art keywords
region
conductive type
layer
conductivity type
epitaxial layer
Prior art date
Application number
TW087106901A
Other languages
English (en)
Inventor
Sun-Hak Lee
Original Assignee
Fairchild Kr Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Kr Semiconductor Ltd filed Critical Fairchild Kr Semiconductor Ltd
Application granted granted Critical
Publication of TW387105B publication Critical patent/TW387105B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66696—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（1 ) 發明領域 本發明係關於半導體裝置及其製法，特別係關於可藉 縮小晶片大小減小接通電阻（Rd)之雙重擴散金屬氧化物半 導體（DMOS)電晶體及其製法。 相關技術之說明 半導體技術晚近對晶片上具高密度之積體功率裝置如 DMOS電晶體，IGFET(絕緣閘極場效電晶體）等開發。可 廣泛用作個別裝置及功率1C(積體電路）之功率裝置具有由 雙重擴散形成的通路。 特別藉雙重擴散所得DMOS電晶體具有經由循序擴散 不同導電型雜質通過孔口進入絕緣層形成的不同導電型雜 質區。DMOS電晶體之雙重擴散結構可形成高準確度短通 路及DMOS電晶體以高速作業。DMOS電晶體根據其電流 路徑分成立式DMOS(VDMOS)電晶體及橫式DMOS (LDMOS)電晶體。 第1圖為習知N通路DMOS電晶體之剖面圖。參照第1 圖，N+埋置層12形成於P型半導體基材10上，及N·外延層 14形成於已經形成有N+埋置層12之基材10上。裝置隔離 區17形成於N·外延層14上，N+槽區16經由擴散高濃度N型 雜質至N+埋置層12而形成於汲極接面形成區下方。 閘極電極20形成於1ST外延層14上方及插置閘極氧化 物膜18。P·本體區22形成於N·外延層14表面，N+源極區24 形成為經由與閘極電極20對正之本體區22包圍。N+汲極 區26形成於N_外延層14表面而由外側未自行對正閘極電極 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (讀先閱讀背面之-注意事項再填寫本頁)
G 、1' A7 B7 五、發明説明（2 ) 20。通路區（未顯示）形成於p-本體區22表面部分疊置閘極 電極20。 有一個接觸孔之絕緣層,3多形成於含閘極電極2〇之N· 外延層14上》金屬層32形成於絕緣層3〇之接觸孔而接觸 DMOS電晶體之閘極電極％，源極及汲極區24及26，及 P_本體區22。 據别述構造之習知DMOS電晶體中，體偏麈區,28可成 形為同時接觸金屬層32與N+源極區24及接觸金屬層g與p- 本體區22。故整體晶片大小增高，其又增加接通電阻。 發明概述 為了克服前述問題，本發明之目的係提供一種DM〇s 電晶體，其可縮小晶片尺寸而降低接通電阻（Rd)。 本發明之另一目的係提供製造前述DM〇s電晶體之適 當方法。 經濟部中央標準局員工消费合j社印製 (請先閱讀背面之注意事項再填寫本頁) 為了達成第一目的，提供一種雙重擴散厘(：);3電晶體 。雙重擴散MOS電晶體包括一層第一.導電型埋置層形成 於半導體基材上，一層第一導電型外延層形成於半導體基 材上，該半導體基材已經有一^第一導電型埋置層形成於 其上，一層閘極電極形成於第一導電型外延層上而其中插 置閘極絕緣膜，一層第一導電型源極區形成於第一導電型 外延層表面且自行對正閘極電極，一層第一導電型汲極區 形成於第一導電型外延層表面且非自行對正閘極電極，第 二導電型本體區形成於第一導電型外延層表面待由第一導 電型源極區包圍，及第二導電型體偏壓區形成於第二導電 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨〇><297公釐） 5 kl -------- B7 五、發明説^^77~^ ~ ~~ ---— 型本體區於第一導電型源極區下方e 較佳第一導電型槽區係形成於第—導電型汲極區下 方至第一導電型埋置層而減少汲極電阻。 此外，絕緣層可形成於包含閘極電極之第一導電型 外延層上，及金屬層可形成於絕緣層上供接觸閉極電極， 第導電型源極及汲極區，及第二導電型體偏壓區。 | 了達成本發明之第二目的，提供—種雙重擴散Mos 電晶體製法。雙重擴散MOS電晶體製法包含下列步驟：循 序形成一層第一導電型埋置層及一層第一導電型外延層於 半導體基材上，形成閘極電極於第一導電型外延層上而其 間插置閘極絕緣膜，經由使用光罩藉離子植入第二導電型 雜質而形成第二導電型本體區至第一導電型外延層表面， 藉離子植入第一導電型雜質至所得結構體表面而形成第一 導電型源極及没極區於第一導電型外延層表面，及經由使 用光罩離子植入第二導電型雜質至寬度比第一導電型源極 區更小之區而形成第二導電型體偏壓區於第一導電型源極 區下方。 於循序形成第一導電型埋置層及第一導電型外延層 之步驟後，第一導電型槽區可經由離子植入第一導電型雜 質至汲極形成區及擴散離子植入雜質至第一導電型埋置層 形成而減少及極電阻。 較佳形成第一導電型源極及汲極區之步驟未使用光 罩。 於形成第二導電型體偏壓區步驟後，絕緣層形成於 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~7~ m i m In 0 丨 ί~Ί----- (讀先聞讀背面之注意事項再填离本頁) • 1---1 _ 經濟部中央標準局員工消費合作社印製 iIT------A-------------------- 經 濟 中 央 標 準 消 費 合 作 社 印 製 五、發明説明（4 A7 B7 所得結構表面，絕緣層於寬度小於第一導電型源極區之區 蝕刻，第-導電型暴露外延層韻刻至第二導電型本體區， 第一導電型沒極區上之絕緣層及間極電極被钱刻，及金屬 層形成於所得結構表面上。 根據本發明可保留體偏壓區，原因為第二導電型體 偏壓區係於第一導電型源極區下方形成。故晶月尺寸縮小 及接通電阻下降。 圖式之簡單說a月 刖述本發明之目的及優點經由參照附圖說明較佳具 體例之細節將顯然易明，附圖中： 第1圖為習知DMOS電晶體之剖面圓； 第2圖為根據本發明之DM〇s電晶體之剖面圖；及 第3至9圖為剖面圖循序示例說明第2圖所示DMOS電 晶體之製程步驟。 〆·-·.. 較佳具體例之詳細說明 第2圖為根據本發明之dm〇S電晶體之剖面圖。參照 第2圖’ N+埋置層102形成於P型半導體基材1〇〇上，經由 提供由沒極接面至電晶體活性區之低電阻路徑而減低汲極 電阻。Ν'外延層1〇4形成於其上已經形成埋置層ι〇2之基 材100上。裝置隔離層1〇7形成於N-外延層1〇4上，N+槽區1〇6 係經由擴散高濃度N型雜質由汲極接觸形成區下方至n+埋 置層102而減低汲極電阻。 閘極電極11 〇形成於N-外延層1 〇4上且插置閘極氧化 物膜108。P-本體區Π2形成於N-外延層104表面，及N+源 (讀先閱讀背面之泣意事項再填寫本頁) 裝· 訂 經濟部中央標率扃貞工消费合作社印製 A7 一_______B7 _ 五、發明説明（5 ) 極區114形成為由對正閘極電極no之p-本體區112圍繞。N+ 没極區116形成於N-外延層104表面而由外侧位於閘極電極 110自行對正。如此閘極電極11〇具有補償結構。此外通路 區（未顯示）形成於P-本體區112表面部分疊置閘極電極11〇 〇 體偏壓之P+體偏壓區118形成於N+源極區114下方之P-本體區112表面。本發明中因p+體偏壓區118係形成於n+源 極區114下方，故可節省體偏壓區。 有接觸孔之絕緣層120形成於含閘極電極no之N·外 延層104。金屬層122形成於絕緣層120之接觸孔而接觸 DMO S電晶體之閘極電極11〇，n+源極及j：及極區114及116 及P+本體區118。 第3至9圖為剖面圖循序示例說明第2圖所示dm〇 S電 晶體之製程步驟。 第3圖示例說明形成外延層104之步驟。首先製備p-半導體基材100，及然後N+埋置層102形成於p-基材100上 經由Φς供由;及極接面至電晶體活性區之低電阻路徑而減低 汲極電阻。Ν+埋置層102較佳藉擴散或離子植入形成。 然後Ν·外延層1 〇4係藉外延增長而於其上已經形成Ν+ 埋置層102之Ρ-基材1〇〇上形成。 第4圖示例說明形成Ν+槽區106之步驟。形成Ν-外延 層104後，Ν+槽區106係經由擴散高濃度!^型雜質由汲極接 面形成區下方至Ν+埋置層102形成。此處n+槽區用於 VDMOS電晶體而非用於LDMOS電晶體。 ^'氏張尺度適用中國國家標準（<：呢）八4規格（2丨0\297公釐） ~ ---- (請先閱讀背面之注意事項再填寫本頁) :裝. 訂 A7 B7 經濟部中央標準局員工消费合作社印掣 五、發明説明（6 隨後裝置隔離層107藉一般裝置隔離法例wL〇c〇s( 局邛矽氧化）形成於外延層1〇4上，因此界定活性區供形 ’成電晶體。 第5圖示例說明形成ρ·本體區112之步驟。活性區界定 後，閘極氧化物膜1〇8藉熱氧化形成於活性區上。然後， 導電材科例如攙雜雜質之多晶矽膜沉積於閘極氧化物膜 108上及藉微影術製作圖樣因而形成閘極電極。 於光阻圖樣111藉微影術形成而開啟Ρ-本體區形成區 後，Ρ型雜質使用光阻圖樣lu作為離子植入先罩進行離子 植入。然後，光阻圖樣111被去除，P-本體區i 12經由於預 定加熱處理過程擴散離子植入ρ型雜質形成。 第6圖示例說明形成N+源極及汲極區丨14及丨丨6之步驟 。形成P本體區112後，N型雜質離子植入所得結構體整體 表面。如此N+源極及汲極區114及116同時形成而自行對正 及非自行對正閘極電極110。 第7圖示例說明形成P+體偏壓區U8之步驟。形成1^+ 源極及汲極區114及116後，藉微影術形成光阻圖樣117而 開啟寬度比N+源極區114更小的區域。然後，使用光阻圖 樣117作為離子植入阻罩，ρ型雜質以高能量離子植入^+ 源極區114下方。結果P+體偏壓區118形成於N+源極區114 下方。 第8圖示例說明絕緣層12〇之形成步驟。於p+體偏壓 區118形成後，去除光阻圖樣in。然後，例如藉沉積低溫 氧化物（LTO)於所得結構上形成絕緣層12〇 ^為了形成源極
(讀先閣讀背面之-注意事項再填寫本頁)
經濟部中央標率局員工消費合作社印製 A7 B7 五、發明説明（7 及本體接觸，絕緣層120藉微影術蝕刻通過寬度比N+源極 區114更小之區’然後，暴露出的N-外延層ι〇4蝕刻至p_本 體區112/因而形成第一接觸孔121供暴露N+源極區114及 P·本體區112。 第9圖示例說b月金屬層122之形成步驟。形成第一接 觸孔121後’第二接觸孔及第三接觸孔經由於n+沒極區 及閘極電極110上蝕刻絕緣層12〇而暴露N+汲極區」μ及閘 極電極110。 然後，金屬材料沉積於所得結構及藉微影術施加圖 樣。如此，形成金屬層122而透過第一接觸孔121接觸Ν+ 源極區114及Ρ-本體區120，透過第二接觸孔接觸Ν+汲極區 116，及透過第三接觸孔接觸閘極電極丨丨〇。結果完成dm〇s 電晶體。 根據前述本發明之DMOS電晶體，因第二導電型體偏 壓區係形成於第一導電型源極區下方，故保留體偏壓區。 如此#片大小及接通電阻減小。 雖然已經就特定具體例說明本發明之細節，但僅供 舉例說明之用。如此業界人士於本發明之範圍及精髓内可 做出多種變化。 (諳先閱讀背面之注意事項再填寫本頁}
A7 B7 五、發明説明（8 ) 元件標號對照 10，100 P型半導體基材 14，104 N·外延層 17，107 裝置隔離區 20，110 閘極電極 24，114 N+源極區 30，120 絕緣層 118 P+本體偏壓區 121 接觸孔 12，102 N+埋置層 16，106 N+槽區 8，108 閘極氧化物膜 22，112 P-本體區 26，116 N+汲極區 32，122 金屬層 111，117 光阻圖樣 (讀先鬩讀背面之注意事項再填寫本頁) .裝· ,ιτ 經濟部中央標準局員工消費合作社印繁 11 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）

Claims (1)

  1. 經濟部中央標隼局員工消費合作社印製 A8 B8 C8 D8 A、申請專利範圍 h 一種雙重擴散MOS電晶體，包含·· 層第導電型，埋置層形成於半導體基材上； 、層第-導電型外延層形成於半導縣材上，該 半導體基材已經有m輕埋形成於其上 9 :·一層閘極電極形成於第—導電型外延'層上.而其中 、捷置閘極絕緣膜； '層第一導電型源極區形成於第一導電型外延層 .表面且自行對丞閘板電極； 一層第一導電型汲極區形成於第—導電型外延層 表.®豆非自行對正閘極電極； 第二導電型本體區形成於第一導電型—外延層表面 待由第一導電型源極區包圍； 及第二導電型體偏壓區形成於第二導電型本體區 於第一導電型源極區下方。 〆 2·如申請專利範圍第1項之雙重擴散馗08電晶體，其又包 含第一導電型槽區係形成於第一導.電型汲極區下方至 第一導電型埋置層而減少汲極電阻。 3·如申請專利範圍第1項之雙重擴散M〇s電晶體，其又包 含絕緣層可形成於包含閘極電極之第一導電型外延層 上’及金屬層可形成於絕緣層上供接觸閘極電極.，第 一導電型源極及没極區’及第二導電型體偏壓區。 4· 一種製造雙重擴散MOS電晶體之方法，包含下列步驟： 循序形成一層第一導電型埋置層及一層第—導電 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 12 ------訂----:-----L---- (請先閱讀背面之注一意Ϋ·項#.填寫本瓦) A8 B8 C8 D8 經濟部中央標隼局員工消費合作杜印製 申請專利範圍 型外延層於半導體基材上； 形成閘極電極於第一導電型外延層上而其間 閘極絕緣膜； 經由使用光罩藉離子植U二，期則而形成 第二導電型本體區至第一導電型外延層表面； ' 藉離子楂入第一導電型雜質至所得結構體表面而 形成第一導電型源極及汲極區於第一導電型外延層表 面； 及經·虫使用光罩離子植入第二導電型雜質至寬度 比第一導電型源極區更小之區而形成第二導電型體偏 壓區轸第一導電型源極區下方， 5 如申請專利範圍第4項之製造雙重擴散M〇 s電晶體之方 法’其又包含下'列步驟··於循庫形成第一導電型埋置層 及第一導電型外延層之步驟後， % ~ .導..電型槽區可經 由離子植入第一導電型雜質至汲極形成區及擴散離子 植入雜質至第一導〜電―型埋置層形成而減少取極電阻。 6. 如申ϋ利範圍第4項之製造雙重擴散MQS電晶體之方 法，其中於形成'第一導電型源極及汲極區之步驟未使 用光罩。 7. 如申請專利範圍第4項之製造雙貪擴散MOS電晶體之方 法，於形成第二導電型之體偏壓區之步驟後，該方法 又(包含下列步驟·. 形成一層絕緣層於所得結構體表面； 蝕刻絕緣層於寬度比第一導電層之源極區寬度更 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） 13 請 先 閱 δ 之 注. I i A8 B8 C8 D8 六、申請專利範圍 窄之區，及蝕刻第一導電型之暴露外延層之第二導電 型之本體區； 蝕刻第一導電型之汲極區上之絕緣層及閘極電極 ;及 形成一層金屬層於所得結構體表面。 (請先閎讀背面之?i意Ϋ·項再灰寫本1) 經濟部中央標隼局員工消費合作社印製 14 本紙張尺度逋用中國國家標準（CNS ) Α4規格（210X297公釐）
TW087106901A 1997-12-19 1998-05-05 Double-diffused MOS transistor and method of fabricating the same TW387105B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970070439A KR100267395B1 (ko) 1997-12-19 1997-12-19 이중-확산 모스 트랜지스터 및 그 제조방법

Publications (1)

Publication Number Publication Date
TW387105B true TW387105B (en) 2000-04-11

Family

ID=19527808

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087106901A TW387105B (en) 1997-12-19 1998-05-05 Double-diffused MOS transistor and method of fabricating the same

Country Status (4)

Country Link
US (1) US6194760B1 (zh)
JP (1) JP3655467B2 (zh)
KR (1) KR100267395B1 (zh)
TW (1) TW387105B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI506781B (zh) * 2009-11-17 2015-11-01 Magnachip Semiconductor Ltd 半導體裝置

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6392274B1 (en) * 2000-04-04 2002-05-21 United Microelectronics Corp. High-voltage metal-oxide-semiconductor transistor
DE10026925C2 (de) * 2000-05-30 2002-04-18 Infineon Technologies Ag Feldeffektgesteuertes, vertikales Halbleiterbauelement
JP5183835B2 (ja) * 2000-11-02 2013-04-17 ローム株式会社 半導体装置およびその製造方法
EP1220323A3 (en) * 2000-12-31 2007-08-15 Texas Instruments Incorporated LDMOS with improved safe operating area
US6713814B1 (en) * 2002-08-05 2004-03-30 National Semiconductor Corporation DMOS transistor structure with gate electrode trench for high density integration and method of fabricating the structure
JP2005236142A (ja) * 2004-02-20 2005-09-02 Shindengen Electric Mfg Co Ltd 横型短チャネルｄｍｏｓ及びその製造方法並びに半導体装置
JP4387865B2 (ja) * 2004-05-14 2009-12-24 パナソニック株式会社 半導体装置
JP4959931B2 (ja) * 2004-09-29 2012-06-27 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
JP2006202810A (ja) 2005-01-18 2006-08-03 Sharp Corp 横型二重拡散型ｍｏｓトランジスタおよびその製造方法
KR100790257B1 (ko) * 2006-12-27 2008-01-02 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
JP5353093B2 (ja) * 2008-07-15 2013-11-27 株式会社デンソー 半導体装置の製造方法
CN102779755B (zh) * 2011-05-13 2014-12-03 北大方正集团有限公司 一种处理半导体器件的方法和系统
ITMI20121244A1 (it) * 2012-07-17 2014-01-18 St Microelectronics Srl Transistore con contatti di terminale auto-allineati
WO2015152904A1 (en) 2014-04-01 2015-10-08 Empire Technology Development Llc Vertical transistor with flashover protection
JP6455023B2 (ja) * 2014-08-27 2019-01-23 セイコーエプソン株式会社 半導体装置及びその製造方法
US9406750B2 (en) 2014-11-19 2016-08-02 Empire Technology Development Llc Output capacitance reduction in power transistors
CN106033776B (zh) * 2015-03-18 2019-03-15 北大方正集团有限公司 一种vdmos器件的制作方法及vdmos器件

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0841702A1 (en) * 1996-11-11 1998-05-13 STMicroelectronics S.r.l. Lateral or vertical DMOSFET with high breakdown voltage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI506781B (zh) * 2009-11-17 2015-11-01 Magnachip Semiconductor Ltd 半導體裝置

Also Published As

Publication number Publication date
JP3655467B2 (ja) 2005-06-02
KR19990051163A (ko) 1999-07-05
KR100267395B1 (ko) 2000-10-16
US6194760B1 (en) 2001-02-27
JPH11186550A (ja) 1999-07-09

Similar Documents

Publication Publication Date Title
TW387105B (en) Double-diffused MOS transistor and method of fabricating the same
US10608110B2 (en) I-shaped gate electrode for improved sub-threshold MOSFET performance
KR100302187B1 (ko) 반도체장치제조방법
US7687834B2 (en) Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
JP3504212B2 (ja) Ｓｏｉ構造の半導体装置
JP2009518870A (ja) 低電力接合型電界効果トランジスタの製造方法及び作動方法
JP2004111900A (ja) 超微細ｓｏｉｍｏｓｆｅｔ及びその製造方法
US6724049B2 (en) SOI semiconductor device with insulating film having different properties relative to the buried insulating film
US20090179274A1 (en) Semiconductor Device and Method for Fabricating the Same
KR100764059B1 (ko) 반도체 장치 및 그 형성 방법
TW521437B (en) Semiconductor device and process thereof
US6621118B2 (en) MOSFET, semiconductor device using the same and production process therefor
JP4027440B2 (ja) 半導体基板の製造方法
KR100232197B1 (ko) 반도체 소자의 제조 방법
US6104069A (en) Semiconductor device having an elevated active region formed in an oxide trench
JP2007123519A (ja) 半導体装置の製造方法及び半導体装置
JPH11220128A (ja) Ｍｏｓｆｅｔ及びその製造方法
US11557662B2 (en) Junction field effect transistor on silicon-on-insulator substrate
KR100362933B1 (ko) 모스전계효과트랜지스터및그제조방법
KR100214077B1 (ko) 모스트랜지스터 및 그 제조방법
TW582116B (en) MOSFET with modulated active area and manufacturing method thereof
JPH0251278A (ja) 二重拡散型電界効果半導体装置の製造方法
JP2000164877A (ja) 半導体装置及びその製造方法
Lindert Process development and device design for continued MOSFET scaling
KR20010001302A (ko) 반도체 소자 및 그 제조방법

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees