TW387095B - Method for forming a contact hole and a multi-layer circuit structure - Google Patents

Method for forming a contact hole and a multi-layer circuit structure Download PDF

Info

Publication number
TW387095B
TW387095B TW087101031A TW87101031A TW387095B TW 387095 B TW387095 B TW 387095B TW 087101031 A TW087101031 A TW 087101031A TW 87101031 A TW87101031 A TW 87101031A TW 387095 B TW387095 B TW 387095B
Authority
TW
Taiwan
Prior art keywords
contact hole
conductive film
forming
electrode wiring
treatment
Prior art date
Application number
TW087101031A
Other languages
English (en)
Chinese (zh)
Inventor
Nobuhiro Nakamura
Yukio Endoh
Masashi Ura
Osamu Itoh
Shoichi Takanabe
Original Assignee
Advanced Display Kk
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Display Kk, Mitsubishi Electric Corp filed Critical Advanced Display Kk
Application granted granted Critical
Publication of TW387095B publication Critical patent/TW387095B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
TW087101031A 1997-05-28 1998-01-26 Method for forming a contact hole and a multi-layer circuit structure TW387095B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13821397A JP4663038B2 (ja) 1997-05-28 1997-05-28 コンタクトホールの形成方法

Publications (1)

Publication Number Publication Date
TW387095B true TW387095B (en) 2000-04-11

Family

ID=15216734

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087101031A TW387095B (en) 1997-05-28 1998-01-26 Method for forming a contact hole and a multi-layer circuit structure

Country Status (4)

Country Link
US (1) US5963826A (enExample)
JP (1) JP4663038B2 (enExample)
KR (1) KR19980086488A (enExample)
TW (1) TW387095B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008540A (en) * 1997-05-28 1999-12-28 Texas Instruments Incorporated Integrated circuit dielectric and method
JPH1145779A (ja) * 1997-07-25 1999-02-16 Tdk Corp 有機el素子の製造方法および装置
US7067861B1 (en) * 1998-11-25 2006-06-27 Micron Technology, Inc. Device and method for protecting against oxidation of a conductive layer in said device
US6303972B1 (en) * 1998-11-25 2001-10-16 Micron Technology, Inc. Device including a conductive layer protected against oxidation
US6492242B1 (en) * 2000-07-03 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Method of forming of high K metallic dielectric layer
KR100556346B1 (ko) * 2001-12-28 2006-03-03 엘지.필립스 엘시디 주식회사 금속 배선 형성방법
KR100518228B1 (ko) * 2003-05-21 2005-10-04 주식회사 하이닉스반도체 반도체 소자의 제조방법
CN100362413C (zh) * 2004-09-29 2008-01-16 财团法人工业技术研究院 一种制作电子装置的方法
JP4604743B2 (ja) * 2005-02-01 2011-01-05 セイコーエプソン株式会社 機能性基板の製造方法、機能性基板、微細パターンの形成方法、導電膜配線、電子光学装置および電子機器
TWI310026B (en) * 2006-07-31 2009-05-21 Ether Precision Inc The molding die of molding glasses and its recycling method
JP5303994B2 (ja) * 2008-03-31 2013-10-02 東亞合成株式会社 エッチング方法、及び、導電性高分子を有する基板
JP2012033689A (ja) * 2010-07-30 2012-02-16 Sumitomo Electric Device Innovations Inc 半導体装置の製造方法
JP2012033688A (ja) * 2010-07-30 2012-02-16 Sumitomo Electric Ind Ltd 半導体装置の製造方法
WO2018230377A1 (ja) * 2017-06-14 2018-12-20 東京エレクトロン株式会社 基板処理方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3851161A (en) * 1973-05-07 1974-11-26 Burroughs Corp Continuity network testing and fault isolating
JPH01152648A (ja) * 1987-12-09 1989-06-15 Matsushita Electron Corp 半導体装置
US5236551A (en) * 1990-05-10 1993-08-17 Microelectronics And Computer Technology Corporation Rework of polymeric dielectric electrical interconnect by laser photoablation
JPH04253342A (ja) * 1991-01-29 1992-09-09 Oki Electric Ind Co Ltd 薄膜トランジスタアレイ基板
US5427962A (en) * 1991-11-15 1995-06-27 Casio Computer Co., Ltd. Method of making a thin film transistor
US5485019A (en) * 1992-02-05 1996-01-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
KR960012259B1 (ko) * 1993-03-13 1996-09-18 삼성전자 주식회사 반도체 장치의 제조방법
US5472913A (en) * 1994-08-05 1995-12-05 Texas Instruments Incorporated Method of fabricating porous dielectric material with a passivation layer for electronics applications
JPH0936407A (ja) * 1995-07-24 1997-02-07 Sanyo Electric Co Ltd 太陽電池
JPH10239709A (ja) * 1997-03-03 1998-09-11 Hitachi Ltd 液晶表示装置およびその製造方法

Also Published As

Publication number Publication date
KR19980086488A (ko) 1998-12-05
JP4663038B2 (ja) 2011-03-30
US5963826A (en) 1999-10-05
JPH10335452A (ja) 1998-12-18

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