TW383477B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- TW383477B TW383477B TW087107703A TW87107703A TW383477B TW 383477 B TW383477 B TW 383477B TW 087107703 A TW087107703 A TW 087107703A TW 87107703 A TW87107703 A TW 87107703A TW 383477 B TW383477 B TW 383477B
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- Taiwan
- Prior art keywords
- power supply
- aforementioned
- semiconductor wafer
- power
- semiconductor device
- Prior art date
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
經濟部中央標準局員工消費合作社印聚 A7 B7 五、發明説明(1') [發明背景] 本發明係關於一種半導體裝置,尤其是關於一種在工作 時所產生之熱得Μ迅速發散掉之半導體裝置。 [先前技術] 近年來由於有待處理之大量資訊日益增加,對於積體電 路[1C]之高速工作能力之要求亦與日益增,為達成此一高 速動作之要求起見,同時又為了要能輸入及輸出所要之訊 號起見,設於1C上之訊號插腳之數量亦隨之增加,再者, 由於IC所消耗之電力亦將增加,電源供給所需之電源插腳 之數量,也必須增加。 另一方面,就其内封人有半導體晶片之封裝體而言,為 達成高密度之裝填,必須力求其大小尺寸之儘量接近半導 體晶片之大小尺寸。 首先,針對第一種之習知技術,將其中封有半導體晶片 之封裝體包括在內之半導體裝置,參照附圖作一說明,圖 1所示者乃一採Bine-pitch ball grid Array (微間距球開 陣列構造)(Μ後一律寫作為微間距BG A]之結構),參照圔7 ,在浸含有環氧樹脂之玻璃薄片(以下稱為「料帶」)106 之某一個面上,搭接固定有一其中介存有一粘著層105之 半導體晶片102,在料帶106之毗接周圍形成有數個墊形電 極107,各墊形電極107利用金線104與半導體晶片102所定 之區域形成電氣連接狀態。 另一方面,在料帶106之另一面上形成有複數個錫鉛球 1 0 8,各該钱08可依在料帶106所形成之,所規定之之 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X 297公釐) -A - (#先閲讀背面之注意事項再填寫本頁) 衮- 訂 ,c. 經濟部中央標準局員工消費合作社印製 A7 _B7 五、發明説明(2 ) 配線而與终端電極107形成電氣連接狀態,半導體晶片102 利用成模樹脂110封固於料帶106上。 微間距BG A由於其上之作·為電極插腳之娛妫球可呈陣列狀 配置,再由於採小封裝體處理,故可形成較多之插腳,這 一點相當有利。 其次,再針對可視之為第2種習知技術之另一半導體裝 置糾|照附圖,作一說明,圔8所示者,係一晶片型標定封 裝體(CSP)之结構圖,自圖8可看出,半導體晶片102之表 面上沒有複數個外部電極1 0 外部電極1 0 9可介經金屬配 線111及终端電極107,而與半導體晶Η 102之所規定之領 域形成電氣連接狀態,半導體晶片102利用成模樹脂110封 固。 CSP之大小與半導體晶片102:大致相同,但可形成更多之 插腳2,在基板上裝配所需之面積較小,故可進行高密度 之裝置。 但,不論是上述之微間距B G Α或C S Ρ,由於消耗電力較大 ,所Μ半導體晶片所產生之熱,就成了一棘手問題,為進 行散熱處理,必須採取種種對策。 其次,茲就可視之為三類習知技術之,可將該一性質 之熱作有效之散熱處理之半導體裝置,根據日本專利特開 平7-50368號公報上所開示之半導體裝置為一示例加K說 明,圖9為該公報上所開示之半導體裝置之一斷面層,圖 10為帽蓋部份去除後之半導體裝置之一平面圖,首先,參 照圖<?,半導體120之背面固定於封裝體125上,且固封於 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X297公i ) (請先閱讀背面之注意事項再填寫本頁) -'5 A7 B7 五、發明説明(3 ) 由帽蓋部123及封裝體125所形成之空間內,是Μ,在半導 體晶片120之上側與帽蓋部123之內側之間,乃形成有一空 隙。 半導體晶片1 2 0上之電源,經由插腳1 2 9 *配線1 2 7,電 源用電極124,焊錫132,及電源用終端122,由外部電路 供應*又,外部電路與半導體晶片1 2 0間之訊號,經由插 腳130,配線128,導線126,結合電線131,结合終端121 交流之,特別值得一提的是,在半導體晶片120之表面上 所形成之電源用終端122,如圖10所示,其面積可増大。 本半導體裝置在工作時,在半導體晶片120上所產生之 熱,除可自半導體晶片120之內側朝封裝體125傳散外,亦 可經由電源用終端122,煬錫132及電源用電極124而傳導 至帽蓋部123,如此*可雙管齊下自封裝體125及帽蓋部 123同時進行散熱,故可將半導體晶片120上所產生之熱丸 份向外部釋散。 又,在設置電源用電極12 4及電源用终端122之後,可減 少經由结合终端121對半導體晶片120之電源供給,其減量 經濟部中央標準局員工消費合作社印製 (讀先閣讀背面之注意事磺再填寫本頁) 部份可轉供結合終端121在半導體晶片120與外部電路之間 之訊號通訊用,其结果,結合终端1 2 1作為訊號通訊用之 數量與往昔相較之下*自然增加不少。 但上述之第三示例之習知技術半導體裝置,有如下之困 擾存在,首先,半導體晶片1 0 2之電源供給是介經電源用 電極1 2而提供者,因此,在半導體晶片1 0 2上沒有必要設 置電源用結合終端,所Κ可加設供電源Κ外之訊號用结合 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X 297公釐) ~" A7 B7 五、發明説明(4 ) 終端,但,電源則是自在封裝體1 2 5上所設之插腳1 2 9供應 至半導體晶片102上,所Μ,在封裝體125之所規定之區域 上所設之插腳129總數並無變化,在此區域上若欲加設新 的訊號甩插腳自然有了困難。 又*傳散至帽蓋部123之熱,若帽蓋部123及封装體125 之表面積越大,則向外界散熱之效果越佳,所Κ,就比較 小之帽蓋部123及封裝體125而言,就比較無法達到充份散 熱之效果。 發明之概述 本發明之目的乃在,為了能夠解決上述之困擾問題,而 提供一能將在工作時所產生之熱充份釋散,並謀增設訊號 用插腳之半導體裝置。 本發明半導體装置,就其之一觀點而言,其上乃配置有 半導體晶片,封裝用構件,電源端子部,Μ及複數個訊號 端子,及電源配線部是也,封裝用構件上可收納半導體晶 片,電源端子部與複數之訊號端子部配置於封裝用構件上 ,並分別與半導體晶片形成電氣連接狀態。 經濟部中央標隼局貝工消費合作社印製 (讀先間讀背面之注意事項再填寫本頁) 電源配線部與電源端子部形成電氣連接狀態,並配置於 封裝用構件之外部,電源端子部與電源配線部所配置之表 面有別於訊號端子部所配屬之封裝用構件之表面。 在採此结構之後,電源端子部即可配置於一有別於其配 置有訊號端子部之封裝用構件之表面之一表面上,如此, 則在與兩者均同時配置於封裝用構件之同一表面之情況相 較之大,在配有訊號端子部之表面上,除了配置了電源端 本紙張尺度適用中國國家標準(CNS ) Α4規格(21〇Χ2<Π公釐) —7 一 A7 B7 五、發明説明(5 ) 子部之外,可同時再增設訊號端子部,又,由於其上配置 有電源端子部之表面未配置訊號端子部,所Μ接至電源端 子部之電源配線部之配線S幅可以毅兔彳|更為寬鬆,如此, 即可增大電源配線部之表面積,其结果,自半導體晶片介經 電源端子部而傳導至電源配線部之熱即可迅速有效地排散 至外界。 最好,電源端子部及電源配線部所配置之表面能面對其 上配置有訊號端子部之封裝用構件之表面,形成對峙。 在此情況下,電源配線部之配線寬幅之設定可進一步放 寬,其结果,半導體裝置之散熱可更有效率的進行。 最好,半導體裝置上納入一其上載置有封裝用構件體Μ 及形成有所規定之配線之基板,且電源配線部上涵蓋了封 裝用構件,並能與所規定之配線形成電氣連接狀態者。 在此情況下,所產生之熱可經由電源配線部傳導至印刷 電路基板上,如此,即可收進一步迅速有效地釋散熱之功 。又,在採可將封裝用構件加Μ涵蓋之電源配線部設計之 後,可收抑制電磁干涉半導體晶片之功。 經濟部中央標準局員工消費合作社印製 又,最好 > 本發明半導體裝置能納置一與各訊號端子部 分別形成電氣連接狀態,且其上形成有所規定之配線之第 一 έΓΘΙ路基板與,其上形成有電源配線部之第二印刷電路基 板,且在該第一印刷電路基板與第二印刷電路基板之間, 配置有用Μ收納半導體晶片之封裝用構件。 在採如上所敘述之結構之後,即可在有限之空間内,達 成Κ最大組装密度而行半導體裝置之裝配之目的。 一 8 (讀先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國_國家標準(CNS ) Α4規搞(210X 297公釐) Α7 Β7 五、發明説明(6 體 導 半 之 態 形 施 實 第 之 明 發 -本 採 該 出 ] 示 明顯 說M 單用 簡為 之 係 式B1 圖 圖 之 内 體 裝 封 之 置圖 裝 之 面 斷 之 取 所 較 線 A I A 之 ο 示 式所 ,圖 中 Ί 1 δ 圖 平出 示 顯Μ 用 為 係 導 半 下 態 形 施 實 第 之一 同 相 在 該 出 示 顯M 用 為 係 ο 3 式圖 圖 之 置 4 裝 圖 ΜαΜΛ 式 圖 之 面 平一 某 面 斷 之 取 所 段 線 B I B 之 示 所 3 圔 在 該 出 示 顯Μ 用 為 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 之圖式。 圖5係為用K顯示出本發明之第2實施形態之半導體裝置 中之某一側視之圔式。 圖6係為用Μ顯示出該在相同之第2實施形態下,本發明 半導體裝置之變化例之其一側面之圖式。 圖7係為用Μ顯示出採第一種先前技術之半導體裝置中 之局部斷面之立體圖。 圖8係為用Μ顯示出採第二種先前技術之半導體裝置中 之局部斷面之立體圖。 圖9係為用Μ顯示第3種先前習知技術之半導體裝置中之 某一斷面之圖式。 圖10係為用Μ顯示出圖9所示之半導體装置之某一平面 之圖式。 [較佳具體例之詳细說明] 第1實施形態: 茲參照圖1〜圖4就採本發明第一實施形態之半導體裝置 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X2Q7公筇) ^ ~ A 7 B7 五、發明説明(7 ) ,加K說明。並且,圖2為沿圖1之A-A線較所取之斷面圖 ,圖4則為沿圖3之B - B線段所取之斷面圖,首先,參照圖1 及圖2,在料帶8上衝壓聯结成形有一半導體晶片2,在半 導體晶片2之外週近接表面上成形有複數個结合终端6,又 ,料帶8之外週表面上設有複數個墊狀電極7*各结合終端 6與墊狀電極7可藉结合電籙4肜成電氣連接狀態,在半導 體晶片2之表面上形成有複數個電源用電極10,是為向半 導體晶片已供應電源之電源端子部,又,在料帶8之下方 ,形成有複數個訊號用電極12,是為供半導體晶片X與訊 號交流之訊號端子部,半導體晶片2及料帶8等,Μ成模樹 脂等封固於封装體9內。 , 再參照圖3,圖4,可知電源用電極12上接有電源配線部 之電源配線16,該電源配線16包括電源(Vcc)配線16a及 GND配線16b在内,各訊號用電極12與在印刷電路基板 (DCB)l 4a之表面上所形成之所規定之配線(圖未示)形成電 氣連接狀態,電源配線16a及GND配線16b分別與在印刷電 路基板14a之表面上所形成之印刷電路基板上Vcc配線15a 經濟部中央標隼局貝工消費合作社印製 (讀先閱讀背面之注意事項再填寫本頁) 及印刷電路基板上GND配線15b形成電氣連接狀態。 在採用如上所述之半導體裝置之後,其上配置有訊號用 電極12之封裝體9之下方就可不必再配置電源用電極10, 如此,則在封裝體9之下方所限定之區域内,除可配置電 源用電極外,尚可增設訊號用電極。 再就接至電源用電極10之電源配線16而言,由於係配置 於封裝體9之外側,故可使用較寬之配線,半導體晶片2所 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X297公# ) 10 - A7 B7 五、發明説明(s) 產生之熱,不但可經由結合電線4傳導至墊狀電極7,亦同 時可自電源用電極10傳導至電源配線16,此時,電源用配 線16a具有散熱片之功能,’可迅速有效地進行散熱,又, 由於熱亦可自電源配線1 6傳導至印刷電路基板1 4 a上,故 散熱敦率乃可進一步之提升。 再者,為使·能對半導體装置進行高密度之組装作業起見 ,封裝體之尺寸應力求與半導體晶片之尺寸接近,一致, 但,若將封装體之原有尺寸改小時,阻礙封装體內熱之流 動所需之力,亦即熱胆抗,將增加,尤其是對於其上承載 有超高速半導體晶Η之半導體装置而言,由於散熱量較大 ,故往往羌靠封裝體無法進行充份之散熱,即使在承載此 等超高速之半導體晶片之情況下,亦可經由上述之電源配 線等,而將在半導體晶片2所產生之熱有效地予Μ釋散掉。 又,在可以將封裝體9覆罩之情況下設置電源配線16之 後,電源配線1 6即可發揮有如一盾障之功能,而抑制對半 導體晶片2之電磁干擾。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 又,與结合電線栢較之下,是利用口徑較大之電源用電 極1 0將電源供給至半導體晶片2的*故不但可抑制電氣阻 抗,亦可抑制電導,而可收將穩定之電壓輸至半導體晶片 2之功。 此外,由於封装體可採用成模樹脂材料,電源用電極及 訊號電極2能作焊接處理,故可舒緩因熱之釋出而造成之 應力方面之問題。 第2實施型態 本紙張尺度適用中國國家標隼(CNS ) Μ規格(210Χ 297公嫠) .., A7 B7 五、發明説明(9 ) 茲藉圖5,就採本發明之第2實施型態之半導體装置作一 說明,參照圖5,其上載置有半導體晶片之封装體9,其本 身乃載置於印刷電路基板I4b之上者也,各訊號用電極1 2 ,分別與在印刷電路基板14b之表面上所形成之所規定之 配線(圖未示)形成電氣連接狀態,至於印刷電路基板14c 之表面上則形成有印刷電路基板上電源配線1 5,該等印刷 電路基板上之電源配線15與設於封裝體9上之電源用電極 10形成電氣連接狀態。 由於在此情況下,印刷電路基板14c之表面上可對電源 配線15之配線區域提供更寬廣之保護,所以自電源用電極 10傳導至電源用配線15上之熱可更有效地釋散,又,半導 體晶片2亦可取得更穩定之電源供給。 再者,印刷電路基板14e之其他表面,可因形成有所規 定之之印刷配線,故可在印刷電路基板14c上載置「其上 載置有半導體晶片之」封裝體9。 經濟部中央標準局員工消費合作社印製 (讀先閱讀背面之注意事項再填寫本頁) 在此情況下,可藉堆集複數個印刷電路基板1 4b , 1 4c , 1 4d ,而在有限之空間内,對半導體裝置進行高密度之組裝作 業。 Μ上乃是電源用電極10在與「其上形成有訊號用電極12 之封装體9之」下側面形成對峙之上側面成型之情況下所 作之說明,但亦可配合半導體裝置之個別組裝需求,而將 電源用電極佈速,成形於封裝體之側面等,亦無不可*在 此情況下亦可取得與上述者相同之效果。 Μ上所敘述之實施形態乃作一闊示例擧,而非用Μ限制 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公焓) _ -10- B7 五、發明説明(1〇) 本發明之應用範圍者,本發明之範圍另在申請專利範圍有 所敘述,但任何變更,在不脫離申請專利範圍之本意,或 與之相當之情況下,仍應視之為屬涵蓋於下述t辛請專利範 圚之内者。 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X297公f )
Claims (1)
- ABCD 經濟部中央標準局員工消費合作社印製 六、申請專利範圍 1 . 一種半導體裝置,係具備有:半導體晶片2 ; Μ及, 該用Μ納置前述半導體晶片1之封裝用構件9; Μ及,配置 於前述封裝用構件9之上,且分別與該半導體晶片2形成電 氣連接狀態之電源端子部1 0及複數個訊號端子部1 2 ; Μ及 與前述電源端子部10形成電氣連接狀態,而被用Μ將電 源供給至前述半導體晶片2,而設於前述封裝用構件9之外 側上之電源配線部1 6 ;並且, 前述電源端子部1 0與電源配線部1 6,係配置在該不同於 其配置有前述訊號端子部12之封裝用構件9之表面的另一 表面上。 2.如申請專利範圍第1項之半導體裝置,其中前述之電 源端子部10與前述之電源配線部16,係配置於該與其配置 有前述訊號端子部12之封裝用構件9之表面圼相對之一表 面上。 3 .如申請專利範圍第2項之半導體裝置,其中係包括有 該形成有用Μ載置著前逑封装用構件9之所規定之配線之 基板14a,並且還設置有前述電源線部16,Μ便於覆蓋住 前述封裝用構件9,同時,與所規定之前述配線,形成電 氣連接狀態。 4.如申請專利範圍第2項之半導體裝置,其中係包括有 :該形成有可分別與前述各個之訊號端子部形成著電氣連 接狀態之所規定配線的第1印刷電路基板.1 4b ; Κ及,該形 成有前述電源配線部15之第二印刷電路基板14c:並且, 該納置有前述半導體晶Η 2之前述封裝用構件9,偽配置 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) _ ·] _ (請先聞讀背面之注意事項再填寫本頁) I -裝. 訂 -ec. ABCD 六、申請專利範圍於前述第1印刷電路基板14b與前述第2印刷電路基板14c之 間。 (請先聞讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐)
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JP10002506A JPH11204679A (ja) | 1998-01-08 | 1998-01-08 | 半導体装置 |
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TW383477B true TW383477B (en) | 2000-03-01 |
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TW087107703A TW383477B (en) | 1998-01-08 | 1998-05-19 | Semiconductor device |
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US (1) | US6054759A (zh) |
JP (1) | JPH11204679A (zh) |
KR (1) | KR100301649B1 (zh) |
TW (1) | TW383477B (zh) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2758630B1 (fr) * | 1997-01-21 | 1999-04-09 | Thomson Tubes Electroniques | Procede de scellement etanche d'un detecteur de rayonnement a l'etat solide et detecteur obtenu par ce procede |
KR100294449B1 (ko) * | 1998-07-15 | 2001-07-12 | 윤종용 | 본딩패드하부에형성되는커패시터를구비한반도체집적회로장치 |
US6949822B2 (en) * | 2000-03-17 | 2005-09-27 | International Rectifier Corporation | Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance |
US6642613B1 (en) * | 2000-05-09 | 2003-11-04 | National Semiconductor Corporation | Techniques for joining an opto-electronic module to a semiconductor package |
US6707140B1 (en) * | 2000-05-09 | 2004-03-16 | National Semiconductor Corporation | Arrayable, scaleable, and stackable molded package configuration |
US6624507B1 (en) * | 2000-05-09 | 2003-09-23 | National Semiconductor Corporation | Miniature semiconductor package for opto-electronic devices |
US6916121B2 (en) * | 2001-08-03 | 2005-07-12 | National Semiconductor Corporation | Optical sub-assembly for optoelectronic modules |
US7023705B2 (en) | 2001-08-03 | 2006-04-04 | National Semiconductor Corporation | Ceramic optical sub-assembly for optoelectronic modules |
US7269027B2 (en) * | 2001-08-03 | 2007-09-11 | National Semiconductor Corporation | Ceramic optical sub-assembly for optoelectronic modules |
US6973225B2 (en) * | 2001-09-24 | 2005-12-06 | National Semiconductor Corporation | Techniques for attaching rotated photonic devices to an optical sub-assembly in an optoelectronic package |
JP4020795B2 (ja) | 2003-02-14 | 2007-12-12 | 三菱電機株式会社 | 半導体装置 |
US7185821B1 (en) * | 2003-07-07 | 2007-03-06 | Cisco Technology, Inc. | Method and apparatus for delivering high-current power and ground voltages using top side of chip package substrate |
US7156562B2 (en) * | 2003-07-15 | 2007-01-02 | National Semiconductor Corporation | Opto-electronic module form factor having adjustable optical plane height |
US6985668B2 (en) * | 2003-07-15 | 2006-01-10 | National Semiconductor Corporation | Multi-purpose optical light pipe |
TWI376756B (en) * | 2003-07-30 | 2012-11-11 | Taiwan Semiconductor Mfg | Ground arch for wirebond ball grid arrays |
US7355289B2 (en) * | 2005-07-29 | 2008-04-08 | Freescale Semiconductor, Inc. | Packaged integrated circuit with enhanced thermal dissipation |
JP5116268B2 (ja) * | 2005-08-31 | 2013-01-09 | キヤノン株式会社 | 積層型半導体装置およびその製造方法 |
US9013035B2 (en) * | 2006-06-20 | 2015-04-21 | Broadcom Corporation | Thermal improvement for hotspots on dies in integrated circuit packages |
US8058719B2 (en) * | 2007-03-23 | 2011-11-15 | Microsemi Corporation | Integrated circuit with flexible planer leads |
US8018042B2 (en) * | 2007-03-23 | 2011-09-13 | Microsemi Corporation | Integrated circuit with flexible planar leads |
ITMI20111216A1 (it) | 2011-06-30 | 2012-12-31 | St Microelectronics Srl | Dispositivo elettronico di potenza ad elevata dissipazione di calore e stabilita? |
ITMI20111218A1 (it) | 2011-06-30 | 2012-12-31 | St Microelectronics Srl | Dispositivo di potenza ad elevata velocita? di commutazione |
ITMI20111217A1 (it) | 2011-06-30 | 2012-12-31 | St Microelectronics Srl | Sistema contenitore/dissipatore per componente elettronico |
ITMI20111214A1 (it) | 2011-06-30 | 2012-12-31 | St Microelectronics Srl | Dispositivo di potenza a spessore ridotto |
ITMI20111208A1 (it) * | 2011-06-30 | 2012-12-31 | St Microelectronics Srl | Sistema con dissipatore di calore stabilizzato |
US8704341B2 (en) * | 2012-05-15 | 2014-04-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with thermal dissipation structures and EMI shielding |
US8674509B2 (en) * | 2012-05-31 | 2014-03-18 | Freescale Semiconductor, Inc. | Integrated circuit die assembly with heat spreader |
US9287227B2 (en) | 2013-11-29 | 2016-03-15 | STMicroelectronics (Shenzhen) R&D Co. Ltd | Electronic device with first and second contact pads and related methods |
DE102020108916A1 (de) * | 2020-03-31 | 2021-09-30 | Infineon Technologies Ag | Package mit Clip und Konnektor über elektronischen Komponenten |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5200362A (en) * | 1989-09-06 | 1993-04-06 | Motorola, Inc. | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
US5808357A (en) * | 1992-06-02 | 1998-09-15 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
JPH0750368A (ja) * | 1993-08-05 | 1995-02-21 | Hitachi Ltd | 半導体装置 |
JP2550902B2 (ja) * | 1993-12-24 | 1996-11-06 | 日本電気株式会社 | 半導体集積回路装置 |
JP3634048B2 (ja) * | 1996-02-28 | 2005-03-30 | 富士通株式会社 | 半導体装置 |
-
1998
- 1998-01-08 JP JP10002506A patent/JPH11204679A/ja not_active Withdrawn
- 1998-05-19 TW TW087107703A patent/TW383477B/zh not_active IP Right Cessation
- 1998-06-05 US US09/092,176 patent/US6054759A/en not_active Expired - Fee Related
- 1998-09-05 KR KR1019980036655A patent/KR100301649B1/ko not_active IP Right Cessation
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KR19990066750A (ko) | 1999-08-16 |
JPH11204679A (ja) | 1999-07-30 |
US6054759A (en) | 2000-04-25 |
KR100301649B1 (ko) | 2001-10-19 |
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