TW299564B - - Google Patents

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Publication number
TW299564B
TW299564B TW085105592A TW85105592A TW299564B TW 299564 B TW299564 B TW 299564B TW 085105592 A TW085105592 A TW 085105592A TW 85105592 A TW85105592 A TW 85105592A TW 299564 B TW299564 B TW 299564B
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Taiwan
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substrate
electronic package
patent application
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TW085105592A
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English (en)
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Ibm
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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

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五、發明説明 、本發明係有關於一種電子封裝，而且特別是有關於但不限 於一種包括基板及至少一元件的電子封裝，該至少一元件的 每個係藉由該基板表面上所具有的一導電墊而附加在該基 板上。 電子封裝通常包括一具有至少主動元件於其上的電路化基 板；僅包括一元件的封裝俗稱單晶片模組（S(：M)，而包括複 數個元件的封裝稱爲多晶片模組（M C M )。使用諸如黏膠之 類的接合材料在將元件連在基板上的電子封裝應用中是普遍 的’特別是在球形格柵陣列（B G Α)封裝中。 BGA封裝在電子封裝工業中是最近發展出來的，用以取代 目前所知的四方平坦封裝（QFp)。主要的差異是連接到印刷 電路板（PCB)的連接系統，亦稱爲第二位階連接，該連接是 藉由一基板底邊上以矩陣佈局形式排列的共晶錫鉛合金球製 成的，而不是用沿著塑膠元件本體之週邊角落放置的金屬導 線製成的。BGA及QFP封裝描述在出處爲v〇1 6 Ν〇. 3, March 1995, Pages 38·40的文章"電路組合"（(：ircuitAssembiy) 中。 每一個元件通常藉由導電墊連接至基板，該墊通常是比所 對應的文連元件稍爲大點，而該元件是在該基板的上表面。 經濟部中央標準局員工消費合作社印裳 這些墊與黏膠材料的相容性良好：此外，在某種程度上， i們可使熱量很谷易從元件的背後藉由傳導傳遞至基板。 習知技術的缺點是每一個墊會浪費基板上表面的大塊區域 而無接線而且根本無法用於連線的路線規劃。這個問題在 MCM中特別嚴重，其中被浪費掉而無法接線的區域必須乘 以元件的數目。這問題牵涉要增加電子封裝的尺寸或減少在 4- 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X29?公着） A7 A7 經濟部中央標準局員工消費合作社印製 五、發明説明f ; 相同基板上所安置的元件數 的模組數目。 ®而増加了相同應用中所需 爲了增加電子封裝料接線性，目前的方 :吏用基板的自由區域作接線;然而，此-解決之 =能惡化，特別是在有機的基板中，而其熱消散値通 、大於0.5瓦。另-個方法是修改基板，亦即不是改變 及，造成較高導電性的材料之技術，例如：陶走載體，不然 就疋增加層的數目；然而，以上兩料決之 增加整個封裝的成本。 頁向卫會 尚有—問題是：這些模組如同其他電子零件都需要與電容 解耦合’⑽減少在應職位階處或在模組基板處的信號雜 訊。 信號雜訊的最佳化作業之通常定址方法是：將電容電源與 接地儘可能與主動元件橋接的非常靠近。當這些電容是處於 封裝位階處的板上時，它們需要特定的接線圖樣而且會衝擊 對電路來説已經是相當小的區域，因而增加了整個模組的尺 寸。.對照而言，當電容係組裝在模组所在的母板上時，它們 常常只能提供剛好能被接受的雜訊減少量。 以上習知技術的缺點可以本案所請的發明加以克服。因此 本發明提供一種如上所述之電子封裝，其特徵在於該整是 由複數1固不相連的零件組成的。 這種解決之道解決了上述的問題。特別是，此法可增加基 板頂層的電氣可接線性以及提昇電子封裝的電氣信號雜訊位 準的減低力》 本案所提的解決之道可完全與現存的材料相容而不影響它 -5- 本纸張尺度賴巾U國家標準（CNS ) A4規格（210X 297公慶） 扣衣---- (請先閱讀背面之注意事^1-"'寫本莧) 訂 - Α7 Έ7 五、發明説明p ) 們的性質；本發明之方法是便宜的且極易實施。此外本發明 的封裝方法可完全地與目前的製程相容五與用於此行業的設 備相容。 這些優點是藉由本發明獲致的，且沒有整個封裝熱消散劣 化的問題；全部墊金屬表面及所提之設計間之差異所產生的 德爾他（delta)熱消散能力是可略而不計的。 在本發明的特殊實施例中，該複數個物件被該基板的可接 線區域所分離。 每一對相鄰物件間的自由區域提供了用以規刻連線路徑的 至少一條接線通道，藉此增加了有關於可用之區域或整個封 裝尺寸的基板可接線性》本發明之實施例包括了減少某一特 別應用所需的電子封裝尺寸；對照而言，它可使準備設置在 相同基板上的元件數目變多，因而減少了相同應吊所需之模 組的數目。 最好’孩元件包括四個角落，該墊由四個物件組成，而且 孩可接線區域具有從該四個角落延伸出而形成的十字形s 這種形狀是極有利的，因爲信號的密度在各角落中會大爲 增加；因此，從該元件之角落開始的接線通道使接線擴散開 來變得更容易些^ ' 在另一個有利的實施例中，該電子封裝是多晶片模組。在 一包括複數個元件的封裝中，所提出的墊設計對整個封裝成 本及性能產生最大的影響》 _ 在本發明的另一個實施例中，至少第—組該等物件連接至 一接地電位，以及至少一第二组物件是連接著—電源電位， 該第一組及第二組物件是藉由一解耦合電容相互連在一起的 ' 6 - 本紙浪尺度適用中國國家標準(CNS ) Α4規格釐） i 1— n —I— n · 批衣I {請先閲讀背面之注意事項+^寫本頁
•1T 經濟部中央標準局員工消費合作社印製 經濟部中夬標缒局員工消費合作社印製 五、發明説明（4 9 此解決 < 运提供了較佳的元件解耦合動作。它使得信號 雜訊減少，以供與主動元件非常靠近之電容電源及接地橋接 疋性能。此外，此-解決之道不會影響具有專用電路之基板 上可用區域之多寡。 取好，該基板包括至少—連接著至少該等物件之一的導電 孔。 本發明的實施例可増加封裝的熱消耗，因而擴大了電子封 裝技術的應用範圍。 有利的是，該電子封裝包括了另一個供應在該基板之另一 個表面上的墊，該另一個墊由複數個另一些不相接的物件所 組成，該等另一些物件的至少—個是藉由該等孔的至少一個 而連接至該等物件中之對應的一個。 最終的路徑是熱消散解決之道，它能增加整個封裝的熱力 性能，並且能幫助該元件有效地控制熱消散因子。結果是熱 的均勻散佈而使熱很容易就傳至母板。 在本發明某一特別有利的實施例中，該基板包括_接地層 及一電源層’該第一物件係藉由該第一組孔而連接至該接地 層，而該第二物件是藉由該第二組孔而連接至該電源層。 在此一實施例中，對解耦合電容的連接是經由誓設計上的 通道而達成的’該墊設計並沒有用以驅動内層（電源或接地） 與層狀物的上表面間之連線所需之越過該.等鑽出之孔的額外 接線作業；該等電容可組合成靠近該元件，因而増加了電氣 性能而使得元件解耦合變得理想。 此外，此一連接尚可藉由金屬接地及電源平面而増進封裝 -7 _ 尽紙伕尺度適用中國國家標準CN:S ) A4規格（210X29?公釐） •产 裝 ^ 訂- ^ 線 {請先閱讀背面之注意事項再填寫本頁) ------
的熱消散因子’而且可擴展熱消散因子的影響至所有朝向母 板介面之接地模组連線。 經濟部中央標準局員工消費合作社印製 Μ在本發明的另—個有利的實施例中，該第一物件是藉由該 等第—組另—物件的對應物件而連接至該接地電位，而該第 —物件是藉由該第二组的物件之對應物件而連接至該電源電 位。 在蔹基板的底表面上的這些另外物件可提供非常短的連線 給出現在相同侧的連接墊，而不需要爲這些連線提供鑽出之 孔這些連接墊可提供多個進接點，而具有非常低的電阻値 0 不同型式的電子封裝可用於實施本發明，例如：QFp， BGA，SCM或MCM ;通常，該電子封裝是Bga。 本發明的各種實施例將會以各種例子加以描述，並參考以 下圖式：其中： 圖1是根據習知技術的電子封裝； 圖2描繪根據本發明之一實施例的電子封裝； 圖3是具有增強之熱消散的電子封裝； 圖4a及4b顯示具有元件解耦合的電子封裝； 圖5描續另一個具有元件解搞合的電子封裝。 請參考前述之圖’特別是圖i，顯示著的是根據習知技術 的電子封裝的橫剖面圖。該圖特別描繪包含元件11〇的B(}A 100，而該元件是藉由黏膠層而附接著電路化的基板12〇。基 板120係位於帶有複數個排列成矩陣型式之連接球或突起13〇 的底側上；連接球通常是共晶焊劑，例如：錫鉛合金。這些 球130用來將BGA封裝與印刷電路板（未顯示）相連。現有二 -8 - 本纸張尺度適用令國國家標孪（CNS ) A4規格（2丨〇Χ297公釐〉 --------丨裳-----—訂·-----H旅 (請先聞讀背面之注意事項再填寫本頁) ,經濟部中央樣準局員Η消費合作.社印製 五、發明説明（6 各種BGA爲：塑膠球形格柵陣列（pBGA)、陶磁球形格柵陣 列（CBGA)以及帶狀球形格柵陣列（TBGA)，它們之間的主要 不同在於基板材料的型式。 元件100是藉由位於基板12〇上表面的導電墊14〇而附接在基 板120上。這個區域通常比元件11〇大些，而使之與黏膠材料 的相容性良好，而使熱量很容易藉由傳導而從元件丨1〇的背 後傳至基板120 = 元件110係藉由線15 〇而接至基板12 0上的電路，且是藉熱 音波線接合作業而進行，然後該組合體被蓋著—層塑膠樹脂 160 〇 現請參考圖2，顯示著的是根據本發明之一實施例的電子 封裝上視圖。該圖描繪具有附接至基板l2〇之元件11〇的Bga 200 〇 基板120可以是不同的材料，例如：塑膠材料，玻璃纖維 層狀物、陶资、聚酿胺、聚酿亞胺、箱土。特別是，最近才 發展出來的電子封裝技術包含：使用一有機基板，此一基板 是一種由層化的環氧織製的玻璃纖維片所组成的複合結構； 有機一詞的定義源自可用來構建這些層狀物的環氧樹脂化合 物（有機化學）。 元件110通常是晶片或主動元件，而其材料通常是矽、鍺 、或砷化鎵；這些元件通常大致是方形的，特別是正方形的 。元件110通常是用黏膠層而連接至基板丨20。該黏膠可以是 熱塑性的或熱固性的；通常它是環氧黏膠，且通常帶有銀粒 子以便有較好的熱消散。 元件110係藉由位於基板120上表面的導電整而連接至基板 -9 丨裝-----：—訂.-----一.成 {請先閔讀背面之注意事項再填寫本頁) 各紙ft尺度相中關家樣準 (CNS )A4 規袼（210 X 297 公釐） A7 ΒΤ 五、發明説明（7 ) 120。此墊使元件與黏膠材料有較好的相容性；而且使熱容 易從元件110的背後傳至基板12〇，此墊通常是由金屬材料製 成’通常是銅或鎳以及鍍金的銅。 在本發明的上述實施例中，該墊是由複數個不相接之物件 212-2 18組成’結果每一對相鄰的物件會被基板丨2〇的自由區 域所分離。至少一個絕緣通道222_228會供應在該墊中，特別 是在越過元件110處》顯示在該圖中的通道222_228是寬得足 以作爲供連線作線路規劃用的接線通道，藉此增加與該封裝 的可用區域或整個尺寸有關之基板可接線性。通常，接線通 道222-228的每一通道可容納四條1〇〇"111寬（1〇〇#111間隔）或六 條75"m寬（75 "m間隔）的線。熟習此項技藝的人士會了解一 塾設計包括減少某一特定應用所需之電子封裝尺寸；對照而 言’它使得準備設置在相同基板上的元件數目變多，因而減 少了相同應用所需的模组數目。上述的解決之道完全可與現 存的材料相容，而不會影響它們的性質；它是便宜的且極易 實施。此外’本發明的封裝方法可與目前的製程及本行業中 的相關設備完全相容。所應注意的是完全墊金屬表面與上述 設計間的差異所獲致的德爾他熱消散能力可略而不計。 經濟部中央標準局員工消費合作·社印製 --------.(-_ 裝— (請先閲讀背面之注意事項再填考本頁) 碌 在本發明的較佳實施例中，該墊被分成四個分離的物件。 在圖2所描繪的實施例中，該墊已經被分成四個不同的區域 或島212-218 ’而其形狀像馬爾他十字（Maltese Cross)。四條 接線通道222-228的每一條從元件1丨〇的對應角落延伸出來至 其中央區域。中央區域可用來規劃從某一通道至其他通道的 路徑，如在多層基板的情況中，或經由孔道（盲孔或通孔）至 内層。這種形狀特別有利，因爲準備送至元件110的信號密 - _____- 10 - 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇κ29?公釐） ^^9564 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（8 ) ·'一—- 度在角落處會增加；因此’從元件11〇之角落開始的接線通 道使得源自元件110的擴展變得更容易些。 熟習此項技藝的人士會了解相同的塾設計可應用到包括複 數個元件的電子封裝中，例如：多晶片模組。每—個元件藉 由對應的整附接至基板。每_個冬被分成複數個不相接的: 件，而由基板的自由區域所隔開，藉此提供至少—條絕緣通 道2接線用。所應注意的是本發明的解決之道對多晶片模組 而言特別有利，其中所述㈣料可對整個封裝成本及性能 產生最大的影響。 現請參考第3圖，顯示著的是具有增加的熱消散之 裝的橫剖面圖。 ’ BGA 300包括附接至基板31〇的元件11〇。在本發明之實施 例中，基板3 10是一包括複數層3 12_318的多層結構，通 用於多晶片模組中。 疋件π〇是藉由上述的導電墊而附接至基板31〇 ;特別是， 分離的物件218、216及214在圖中是可見的。如前所述，完 全墊金屬纟面與上述設計間的差異所獲致的德爾他熱消散= 力可略而不計。 匕 然而，即使用了導電墊，這些電子封裝的熱消散會受限於 基板的不良熱料性質；此-問題使得電子封裝技術所得瓦 數受限在1.3W而無法作更廣泛的應用， 爲了増加封裝的熱控制，在本發明的實施例中，基板3⑺ 包括至少-導電孔’通常是鑽出的且是金屬化的孔，並連接 至基板310上表面的墊；在此實施例中，熱孔道326係連著物 件216，而熱孔道328係連接物件218。這些熱孔道可再連接 -—--------- -11-
本纸張尺度賴 ) A4^ ( 2lOX29'7iTT j— 裝-----^—訂·------S1線 (請先閱靖背面之注意事項再填寫本Ϊ) 經濟部中央標準局員工消費合作社印製 A7 _____— B7_____ 五7發明説明（9 ) " ·~~~--- 至相同基板310之底表面上的墊。在較佳實施例中，這另— 個墊與基板310上表面的墊之形狀相同。特別是，它包括複 數個分離的物件334-338 ·，在所述之封裝30〇中，熱孔道可^ 以將基板3 10上表面的物件216連接至底表面上的對應物件 336，以及孔328可將物件218連接至對應物件338。 在基板3 10底側上的墊係連接著用以連接B G Α封裝及印刷 電路板（未顯示）的共晶球130。結果是熱均勻散布，該熱是 藉由整個球陣列130而散逸至母板。熱消散會增加整個封裝 熱性能，其熱消散値通常大約爲2 W。 在圖中的實施例中，多層的基板310包括接&(GND)層3芯 及電源（VCC)層344。熱孔道326及328係連接著（^〇層342 及VCC層344。所應注意的是：GND層342及vcc層344這 兩者通常是全金屬平面，它們再次提昇封裝3〇〇的消散因子 。此外，對GN D層342的連接可延伸熱消散因子的效果至朝 著主板介面的全部GND模組連接。 現請參考圖4a及圖4b，顯示著的是具有元件解耦合的電子 封裝》 現特別參考圖4a，所描繪的是BGA 4〇〇的上視圖。BGa 400包括藉由上述之導電墊而附接至基板12〇的元件11〇 ;特 別是’該墊被分成四個不同的物件212_218。 爲了提供較佳的元件解耦合動作，至少墊的第一物件，例 如：物件216，係連接至接地電位，而至少第二物件，例如 •物件218係連著電源電位；這兩個物件216及218彼此藉著 解耦合電容410而互連。在本發明的較佳實施例中，四個物 件212-2 18係連接成介面對偶在不同的電位gnd及vcc ί請先聞讀背面之注意事唄再填寫本頁} • I. . * 、" —1 .^ϋ ·
經濟部中央標準局員工消费合作社印製 -A7 B7- 五、發明説明（10 ) 顯示）處。在所述的實施例中，對電容的連接是藉由從整的 每一物件至對應電容的線而達成的《所應注意的是：此解決 之道可爲電氣性能提供信號雜訊位準的減少》熟習此項技藝 的人士將會明瞭：即使這些物件212-218是由不可連線的窄區 域分離，此解搞合動作也可達成；在本發明的較佳實施例中 ，這些物件是由一夠寬的區域所分開以便提供上述的接線通 道。 如第4b圖的橫剖面圖所示，在基板120上表面的整係連著 基板120底表面上的替；特別是，物件216是藉由導電孔3 26 而連著另一物件336 ’而物件218是藉由熱孔道328而連接塾 3 3 8。這些在基板120底表面上的物件提供非常短的連線给接 合墊（VCC或GND)，這些墊是出現在不需供這些連線用的 錯出孔之相同側。在G N D及V C C區域中的連接球是最後其 電阻値非常低的多個進接點。 具有元件解耦合之電子封裝的實施例係顯示在圖5中。 BGA 500是一種包括接地層342及電源層344的多層結構； 金屬化的孔326係連接著導電墊的物件2 16，而孔328係連接 著物件2 18 => 在圖5之特別有利的實施例中，在不同電位G N D及V C C處 的成介面對偶的連線是在相同的晶片載體上達成的，並使用 墊的每一物件之熱孔道作爲VCC或GND平面的連線，而且 電容們都組合成很靠近元件。在所述的實..施例中，物件216 是藉由孔326而連著接地平面342，而物件218是藉著孔328而 連著電源層344。 對電容5 10的連線是藉由金屬化的孔而達成的·，特別是， -13- 本纸法尺度適用中國國家標隼（CNS ) μ規格I: 210X 297公釐） ^各 ^JT. ^ 線 (請先閱讀背面之注意事項再填寫太頁) 五、發明説明（11 ) 電容510是藉由孔520而連接著接地居， _ 向错著另一孔530而 連著電源層344。本發明的實施例提昇 开；几件的電氣性能， 因而有了理想的元件解耦合，而不需要越過鑽出之孔而額外 接線來驅動從内層（VCC或GND)至層狀物上表面。 ' 一 裝 ； 、.1Tj 線 (請先閲讀背面之注意Ϋ項再填寫本頁) 經濟部中央標準局—工消費合作社印製 14- 本紙倀尺度適用中國國家標準（CNS ) A4规格（2l〇X 297公釐）

Claims (1)

  1. 經濟部中央標隼局員工消費合作社印製 A8 B8 C8 六、申請專利範圍 ι· 一種電子封裝（200)，包括一基板（120)及至少一元件（ιι〇) 玄至少一元件（110)的每一個是藉由該基板（12〇)某一表 面上的導電墊而連接至該基板（12〇)，其特徵在：該墊是 由複數個不相接的物件（212-218 )所組成。 2. 根據申請專利範圍第i項之電子封裝（2〇〇)，其中該等物 件U12-218)是被該基板（120)的可接線區域（222_228)所 分開。 3. 根據申請專利範圍第2項之電子封裝（2〇〇)，其中該元件 〇1〇)包括四個角落，該墊是由四個物件（212_218)所组成 ，而該可接線區域（222-228)具有從該等角落延伸出之十 字形。 4. 根據申請專利範圍第丨至3項中任一項之電子封裝，其中 該電子封裝是多晶片模組。 5. 根據申請專利範圍第1至3項中任一項的電子封裝， 其中至少該等物件的第一物件（216)係連著接地電位，而 至少該等物件的第二物件（218)係連著—電源電位，該第 —及第二物件（216、218)彼此藉由—解耦合電容（41〇)而 互連。 6. 根據申請專利範圍第i至3項中任一項之電子封裝（3〇〇)， 其中該基板（310)包括至少一與該等物件（212·218)中的至 少一物件（216)相連的導電孔（326)。 7·根據申請專利範圍第6項之電子封裝（3〇〇)，尚包括供應 在该基板（310)另一表面上的另一墊，該另—墊是由複數 個不相接的物件（334-338 )組成，該等物件的至少一個物 件（3 3 6 )係藉由至少該等孔之一個孔（3 2 6 )而連著該等物件 15- $紙》^中國國家梯準（CNS)八娜_ (21〇Χ29爾） (請先；8讀背面之注意事項再填寫本頁) 袈 訂 經濟部中央標隼局貝工消費合作社印製 A8 B8 -C8 六、申請專利範圍 中的對應物件（216)。 8. 根據中請專利範圍第6項之電子封裝（)，其中該基板 (310)包，一接地層（342)及電源層（344)，該第一物件 (2 16)是藉由孩等孔的第一孔而連著該接地層（342)，而該 第一物件（218)疋藉由該等孔中的第二個孔（328)而接著該 電源層（344) » 9. 根據申請專利範圍第7項之電子封裝（4〇〇)，其中該第一 物件（216 )是藉由該等物件的對應物件（3 26 )而連著該接地 電位’而該第二物件（218)係藉由該等物件的第二物件 (328 )而連著該電源電位。 10. 根據申請專利範圍第1、2、3、7、8或9項之電子封裝， 其中該電子封裝是球栅陣列構裝（B G A)。 -16- 本紙》尺度適用中國國家標準（CNS ) A4洗格（210 X 297公釐） (请先閲讀背面之注意事項再填寫本I) 3·
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