TW373181B - Integrated memory having a de-activatable data output - Google Patents

Integrated memory having a de-activatable data output

Info

Publication number
TW373181B
TW373181B TW086101482A TW86101482A TW373181B TW 373181 B TW373181 B TW 373181B TW 086101482 A TW086101482 A TW 086101482A TW 86101482 A TW86101482 A TW 86101482A TW 373181 B TW373181 B TW 373181B
Authority
TW
Taiwan
Prior art keywords
data output
detection signal
change detection
integrated memory
address
Prior art date
Application number
TW086101482A
Other languages
English (en)
Chinese (zh)
Inventor
Thomas Kristoffersson
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW373181B publication Critical patent/TW373181B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G11C7/1024—Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address

Landscapes

  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Static Random-Access Memory (AREA)
TW086101482A 1996-02-13 1997-02-11 Integrated memory having a de-activatable data output TW373181B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19605250 1996-02-13

Publications (1)

Publication Number Publication Date
TW373181B true TW373181B (en) 1999-11-01

Family

ID=7785273

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086101482A TW373181B (en) 1996-02-13 1997-02-11 Integrated memory having a de-activatable data output

Country Status (2)

Country Link
TW (1) TW373181B (de)
WO (1) WO1997030450A1 (de)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817037B2 (ja) * 1987-12-03 1996-02-21 松下電子工業株式会社 スタティックｒａｍの出力回路
US5325330A (en) * 1993-02-11 1994-06-28 Micron Semiconductor, Inc. Memory circuit with foreshortened data output signal
JPH07182864A (ja) * 1993-12-21 1995-07-21 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
WO1997030450A1 (de) 1997-08-21

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