TW373180B - Integrated memory having a de-activatable output - Google Patents

Integrated memory having a de-activatable output

Info

Publication number
TW373180B
TW373180B TW086101481A TW86101481A TW373180B TW 373180 B TW373180 B TW 373180B TW 086101481 A TW086101481 A TW 086101481A TW 86101481 A TW86101481 A TW 86101481A TW 373180 B TW373180 B TW 373180B
Authority
TW
Taiwan
Prior art keywords
detection signal
change detection
address
driver
integrated memory
Prior art date
Application number
TW086101481A
Other languages
Chinese (zh)
Inventor
Thomas Kristoffersson
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW373180B publication Critical patent/TW373180B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

A dynamic memory in which changes in the bit address BADR are detected by an address change detection signal ATD. Its data output DOUT driven by a tristate driver T is deactivated as a function of the address change detection signal ATD, if at the same time as the activation of the latter, a column address control signal CASN is in a low level state. This avoids a short circuit between the power Vcc and grounding of the driver T, during the two successive read-out of different data in the extended data out mode.
TW086101481A 1996-02-13 1997-02-11 Integrated memory having a de-activatable output TW373180B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19605249 1996-02-13

Publications (1)

Publication Number Publication Date
TW373180B true TW373180B (en) 1999-11-01

Family

ID=7785272

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086101481A TW373180B (en) 1996-02-13 1997-02-11 Integrated memory having a de-activatable output

Country Status (2)

Country Link
TW (1) TW373180B (en)
WO (1) WO1997030451A1 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817037B2 (en) * 1987-12-03 1996-02-21 松下電子工業株式会社 Static RAM output circuit
US5325330A (en) * 1993-02-11 1994-06-28 Micron Semiconductor, Inc. Memory circuit with foreshortened data output signal
JPH07182864A (en) * 1993-12-21 1995-07-21 Mitsubishi Electric Corp Semiconductor memory

Also Published As

Publication number Publication date
WO1997030451A1 (en) 1997-08-21

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