WO1997030451A1

WO1997030451A1 - Integrated memory with de-activatable data output

Info

Publication number: WO1997030451A1
Application number: PCT/DE1997/000250
Authority: WO
Inventors: Thomas Kristoffersson
Original assignee: Siemens Aktiengesellschaft
Priority date: 1996-02-13
Filing date: 1997-02-10
Publication date: 1997-08-21
Also published as: TW373180B

Abstract

The invention relates to a dynamic memory in which changes in the bit address BADR are detected by an address change detection signal ATD. Its data output DOUT driven by a tristate driver T is de-activated as a function of the address change detection signal ATD when, at the same time as the activation thereof, a column address control signal CASN has a low level. In this way, there is no short circuiting of the supply potentials VCC, or earth of the driver T when two divergent data are read out in succession in extended data out mode.

Description

description

Integrated memory with data output that can be deactivated

The invention relates to an integrated memory with a deactivatable data output.

Integrated memories organized in matrix form have word lines (rows) and bit lines (columns) with memory cells arranged at their crossing points. It is known to control dynamic, matrix-shaped integrated memories (DRAMs) by means of a row address control signal (Row Address Strobe, RASN) that can be fed to the memory and an externally feedable column address control signal (Column Address Strobe, CASN) (in the following, the after a "N" after an abbreviation or a reference character denotes a signal which is active at its low level). As a rule, negative edges of RASN and CASN serve to determine times at which word or bit addresses that can be applied to the memory are switched or accepted, and then control of the word addressed by the addresses adopted - or bit lines is initiated. The content of the memory cell addressed in each case can then be evaluated, for example as a differential signal, and transmitted to a data output via a differential amplifier.

In the simplest case ("standard mode"), a read cycle in a DRAM provides for the addressing of only one memory cell. Then only a negative edge of both RASN and CASN occurs during a read cycle. After reading out a memory cell, the output is deactivated each time by switching it to a high-resistance state. As is well known, this happens through the positive edges of CASN. In addition, in standard mode during a read cycle, the data output is generally deactivated each time the bit address changes. In the so-called "fast page mode", a word address is first determined for reading out memory cells by a falling edge of RASN. A bit address is then defined by several successive falling edges of CASN, whereby a memory cell is selected in each case. In fast page mode, this retention of the word address while reading out several memory cells means that the access times can be significantly reduced. However, the minimum access time is limited by the deactivation of the data output, even in the fast page mode, after each memory cell has been read out, depending on the rising edge of CASN.

A further reduction in the access times in the case of DRAMs of conventional architecture is achieved by operating in the so-called "Extended Data Out (EDO) Mode" or "Hyper Page Mode". In order to make this possible, only minor changes to the memory design are necessary. Above all, a buffer (a data latch) must be provided, which stores the current data to be output in each case. The data latch is usually switched to transparent during the low level of CASN, i.e. Data at its input are immediately transferred to the data latch. In contrast, the data latch is non-transparent during the high level of CASN, i.e. Data changes at its input are irrelevant and the data value last read is held by it.

In EDO mode, control is similar to that in fast page mode, but the data output is no longer deactivated by the positive edges of CASN during a read cycle, so that data is constantly present at the data output during a read cycle. There is therefore no deactivation of the data output. _Since the output driver is usually implemented as a tri-state driver (which can generate one of two logical values or a high-resistance state at the data output), it can be used in EDO mode during the successive readout of two different data (for example, logical one to lo¬ gisch Null) briefly come that the two supply potentials of the output driver are connected to each other via this. The reason for this is that the data output in EDO mode is no longer switched off (as in Fast Page Mode) with the positive edge of CASN.

The consequence of this is a leakage current as well as - possibly very strong - impairment of the stability of the supply potential.

In addition, in the EDO mode there is no deactivation as a function of a change in the bit address, as a result of which the problems described can also occur.

Furthermore, since, as described above, the data latch is transparent during the active phase of CASN (active low), a possible change in the data to be read out (from logic zero to logic one or vice versa) caused by a change in the bit address also occurs during this period the data latch is passed on to the data output. This means that the described problems (leakage current, instability of the supply potentials) can occur even after the falling edge of CASN during its low level.

The integrated memory according to claim 1 enables improved operation of an integrated memory in EDO mode while - at least partially - avoiding the disadvantages mentioned.

The invention provides for the data output to be deactivated as a function of an address change detection signal in order to detect a change in the bit address, provided that the column address control signal has a certain state. namely a first level. However, if the column address control signal has a second level, there is no deactivation.

In the prior art, when operating a DRAM in standard mode during a read cycle, the data output is deactivated each time the bit address changes, regardless of the column address control signal and in particular regardless of its level (see above).

A further development of the invention provides that the data output can additionally be deactivated by the same edge of the column address control signal, depending on which a bit address present in the memory can be adopted. In this way it is achieved, for example, that a tristate driver for driving the data output can be switched into a high-resistance state whenever a new bit address is accepted during a read cycle. As a result, it is ensured that the data output is in any case high-impedance before driving another logic state and only then is it reactivated in a clear manner.

This avoids any leakage current between the supply potentials of the tristate driver, since here too the driver first becomes high-resistance before a change from driving a logic state to driving another logic state.

In the prior art, when a dynamic memory is operated in EDO mode, as described above, the data output is not deactivated at all during a read cycle. In the standard mode, the data output is deactivated with a different edge of the column address control signal than the acceptance of a new bit address.

The Tristate driver should only be deactivated for a short time, but long enough that an even Switching the driver to drive a different logic level has already been completed. At least one of the control signals of the tristate driver is therefore always deactivated. This has the advantage that due to the necessary, only brief deactivation, there is almost no impairment of the minimum access time compared to the EDO mode known hitherto, but at the same time the supply potential is not impaired by the function of the tristate driver and also No leakage current occurs, even if different logic levels are read out one after the other within a read cycle.

The invention is explained in more detail below with reference to the figures. 1 shows an exemplary embodiment of the invention,

FIG. 2 shows a time diagram for signal profiles, as can occur in the prior art,

3 shows a time diagram for signal curves in the exemplary embodiment according to FIG. 1, FIG. 4 shows an exemplary embodiment of a circuit for generating signals shown in FIG. 1,

FIG. 5 shows a time diagram for the signals drawn in FIG. 4.

FIG. 1 shows a memory according to the invention in the form of a dynamic memory (DRAM), in which only the elements essential for understanding the invention are shown. For example, evaluators or sense amplifiers for the data to be read out and other components which are known to be necessary for the operation of a memory and whose structure is known to the person skilled in the art are not shown.

Word addresses WADR and bit addresses BADR can be applied to the memory (on separate or multiplexed connections). They are used to address word lines WL or bit lines BL of a memory matrix M, in which memory cells MC are arranged. For this purpose, the word WADR and bit addresses BADR can be read into a word address buffer WADRB or into a bit address buffer BADRB, to which a row address control signal RASN or a column address control signal CASN can be applied. The latter are used to determine the point in time at which activation of the respectively addressed word WL or bit lines BL is initiated. This point in time is referred to here as "takeover". In the case of conventional dynamic memories, the release is generally effected by the falling edges of the row address control signal RASN or the column address control signal CASN and this is also to be assumed for the exemplary embodiment under consideration.

The word WADR and bit addresses BADR can be decoded by corresponding decoders WDEC, BDEC. In this exemplary embodiment of the invention, the contents of addressed memory cells SC are evaluated by means of a difference signal between the addressed bit line BL and an inverted bit line BLN, which have inverse logical levels when reading the corresponding memory cell SC and which have corresponding data lines DL, DLN are connectable.

The data lines DL, DLN are connected to the inputs of a data latch L, which is connected on the output side to a differential amplifier DAMP via further data lines DL ', DLN'. The differential amplifier DAMP activates one of two control signals OUTH, OUTL as a function of a differential signal UDL 'between the further data lines DL', DLN 'to control a tristate driver T which drives a data output DOUT of the memory. The generation of such control signals for the control of a tristate driver by a differential amplifier or in another way is known to the person skilled in the art.

The data latch L is used to hold data to be read and is controlled by means of a latch signal DPN, the generation of which tion is explained below with reference to Figure 4. The latch signal DPN switches the data latch L transparent in the activated state (low level), ie its content then corresponds to the data present on its input on the data lines DL, DLN. If the latch signal DPN is inactive (high level), the data latch L is switched non-transparently, ie the data value previously present at its input is held by it, but changes to the data at its input have no effect on the content of the data latch L.

In order to accomplish the deactivation of the data output DOUT according to the invention, two transistors T1, T2 are provided in this exemplary embodiment, which serve to connect the further data lines DL ', DLN' to a supply potential VCC of the memory as a function of a deactivation signal CRN. The generation of the deactivation signal CRN is also described below with reference to FIG. 4. If both transistors T1, T2 are switched through by a low level of the deactivation signal CRN, the difference signal UDL 'has a value of 0 volts. As a result, the differential amplifier DAMP deactivates both control signals OUTL, OUTH, i.e. switches to a low level. Then none of the transistors of the tristate driver T is turned on, so that it is high-impedance.

By means of an OR gate OR, the inputs of which are connected to the outputs of the bit address buffer BADRB, an address change detection signal ATD can also be generated via an activation circuit AKT. This is always briefly at a high level or is activated when the bit address BADR changes. The generation of such a signal and its use for the control of a dynamic memory are known to the person skilled in the art. However, the address change detection signal ATD is used here in a new way to generate the latch signal DPN as well as the de Activation signal CRN, which is also described with reference to FIG. 4.

The arrangement of the elements shown in Figure 1 is only an example. The differential amplifier DAMP can thus also be connected before the data latch L and / or the transistors T1, T2 can be connected directly to the inputs of the tristate driver T or to the inputs of the data latch L. In addition, the invention is not limited to memories in which the memory cell contents are evaluated using difference signals. It is only important that the data output DOUT can be deactivated.

FIG. 2 shows the curves for some of the signals shown in FIG. 1 in the event that the data output DOUT is not deactivated in the manner according to the invention. A signal curve is then obtained as in the execution of the EDO mode in DRAMs according to the prior art. The beginning of a read cycle in EDO mode is shown. This is initiated by a falling edge of the row address control signal RASN. With the following falling edges of the column address control signal CASN, one memory cell SC is then read out, it being assumed that first a logic zero and then a logic one is read out. The course of the difference signal UDL 'shown is therefore obtained.

The differential amplifier DAMP in FIG. 1 now activates the two control signals OUTL, OUTΗ for the tristate driver T as a function of the differential signal UDL ', so that the signal curve shown results at the data output DOUT. After the second falling edge of the column address control signal CASN - due to an assumed change of the bit address BADR, which is expressed in a pulse of the address change detection signal ATD and occurs in the example shown after the first rising edge of the column address control signal CASN - there is a change from one to be sent Zero to one to be read out. The differential amplifier DAMP then deactivates one control signal OUTL and activates the other control signal OUTH. In this case (as shown in FIG. 2) it can happen that both transistors of the tristate driver T in FIG. 1 are at least partially open at the same time, so that the problems of a leakage current between the supply potentials VCC mentioned in the introduction to the description arise , Mass of the driver T and a disturbance of its stability comes. In FIG. 2, an activation of the address change detection signal ATD by an assumed change of the bit address BADR with respect to the control of the driver T remains irrelevant.

The curves for the same signals as in FIG. 2 are now shown in FIG. 3, but in the event that the data output DOUT is now deactivated according to the invention. After each falling edge of the column address control signal CASN, the previously activated of the two control signals OUTL, OUTH is first deactivated via the deactivation signal CRN, which is still to be described, before one of them is reactivated. In this way, the leakage current between the supply potentials VCC, ground of the tristate driver T is avoided and both supply potentials remain stable.

It can be seen from FIG. 3 that the differential signal UDL 'is briefly brought to 0 volts by switching the transistors T1, T2 on each falling edge of the column address control signal CASN, so that the differential amplifier DAMP initially deactivates both control signals OUTL, OUTH. Only after both control signals OUTL, OUTH have been safely deactivated can one of these two signals be reactivated in order to transmit the data to be read out to the data output DOUT.

If the bit address BADR now changes and the address change detection signal ATD is activated, this only has an effect on the data output according to the invention. gang DOUT, if the column address control signal CASN has a first, in this case low, level. In this case, the data output DOUT is deactivated, as shown in FIG. 3. However, if the column address control signal CASN has a second, in this case high, level, the data output DOUT is not deactivated despite activation of the address change detection signal ATD.

In the signal curve shown it is assumed that after the second falling edge of the column address control signal CASN an address change takes place and thus another memory cell SC is read out, but both memory cells SC contain the same data value (logical one), so that after the deactivation of the driver T there is again a logical one at the DOUT output.

The deactivation of the respectively activated control signals OUTL, OUTH can be carried out quickly, so that the resulting deactivation of the data output DOUT is correspondingly short-lived and almost the same minimum access times can be realized as without the deactivation according to the invention, with simultaneous achievement the advantages according to the invention.

FIG. 4 shows, by way of example, a circuit for generating the deactivation signal CRN and the latch signal DPN from the column address control signal CASN and the address change detection signal ATD via nand gates N and inverters I, which are also embodied here as nand gates. The corresponding signal curves are shown in FIG. 5. In this exemplary embodiment, the data output DOUT is deactivated both as a function of the column address control signal CASN and of the address change detection signal ATD, as will now be explained with reference to FIG. 5.

FIG. 5 shows the mode of operation of the circuit from FIG. 4. The course of the latch signal DPN largely corresponds to substantially that of the column address control signal CASN. If there is a change in the bit address BADR, the address change detection signal ATD is temporarily activated by the activation circuit AKT (FIG. 1), so that it has a pulse. If the column address control signal CASN is then simultaneously at its high second level, the latch signal DPN and the deactivation signal CRN remain unaffected. However, if the column address control signal CASN is at its low first level, the latch signal DPN is deactivated (high level) and the deactivation signal CRN is activated (low level).

However, the deactivation signal CRN is not only activated by the address change detection signal ATD with a simultaneous (low) first level of the column address control signal CASN. In addition, it is activated by every falling edge of the column address control signal CASN, so that the signal curve shown results at the data output DOUT.

The exemplary embodiment shown in FIG. 4 is particularly favorable, since the data output DOUT is deactivated by the deactivation signal CRN on a falling edge of the column address control signal CASN and also when the address change detection signal ATD is activated, provided that the (low) first level of the column address control signal ATD is present ¬ lies. Since the data latch L is transparent at the low level of the latch signal DPN, as described with reference to FIG. 1, data changes occurring on the data lines DL, DLN during the same period due to a change in the bit addresses BADR result in such data changes on the further ones ren data lines DL ', DLN'. Therefore, without deactivating the data output DOUT according to the invention when activating the address change detection signal ATD when reading different data at the data output DOUT in succession, an undesirable cross-current between the supply potentials VCC, mass of Tristate driver T come. In the described embodiment, such cross currents are completely prevented.

Of course, circuits are also possible in which the address change detection signal ATD is not used to generate the deactivation signal CRN and the latch signal DPN. In FIG. 4, for example, an inverter can then also be used instead of the upper Nand gate N. In this case, the DOUT data output is only deactivated when the falling edges of the column address control signal CASN occur. As explained, these falling edges, as explained, have the effect of releasing the bit addresses BADR, so that a new memory cell SC is triggered.

On the other hand, it is also possible to deactivate the data output DOUT only as a function of the address change detection signal ATD and not by the falling edge of the column address control signal CASN. In the circuit shown in FIG. 4, this can be achieved in that the deactivation signal CRN is generated from the latch signal DPN by an additional inverter instead of the NAND gate shown.

Claims

claims

1. Integrated memory which has a memory matrix (M) having word lines (WL) and bit lines (BL) with the following features:

A row address control signal (RASN) can be applied to it to take over a word address (WADR) that can be applied,

a column address control signal (CASN) can be applied to it, which has an edge, depending on which an applicable bit address (BADR) can be adopted,

the content of a memory cell (SC) addressed by the adopted word (WADR) and bit address (BADR) can be transferred to a data output (DOUT),

an address change detection signal (ATD) can be activated when the bit address (BADR) changes,

- Depending on the column address control signal (CASN), the data output (DOUT) is deactivated when the address change detection signal (ATD) is activated.

2. Memory according to claim 1,

the column address control signal (CASN) has a first and a second logic level,

- In which the data output (DOUT) is deactivated by activating the address change detection signal (ATD) only when the first logical level of the column address control signal (CASN) is present.

3. The memory of claim 2, wherein the first logic level is a low level of the column address control signal (CASN).

4. Memory according to one of the preceding claims, in which when the edge of the column address control signal (CASN) occurs, the data output (DOUT) is deactivated.

5. The memory of claim 4, wherein the edge of the column address control signal (CASN) is a falling edge.

6. Memory according to one of claims 4 or 5,

in which a word address (WADR) can be adopted by the row address control signal (RASN), whereupon a plurality of bit addresses (BADR) can be adopted successively by a plurality of similar edges of the column address control signal (CASN),

- in which when each of the edges occurs, the data output (DOUT) is deactivated.

7. Memory according to one of the preceding claims with the following features:

The data output (DOUT) is connected to the output of a tristate driver (T) controlled by two control signals (OUTH, OUTL),

- To deactivate the data output (DOUT), the two control signals (OUTH, OUTL) can be deactivated, as a result of which the tri-state driver (T) can be switched to a high-resistance state.

8. Memory according to claim 7, in which the duration of the deactivation of the control signals (OUTH, OUTL) is dimensioned such that at least one of the two control signals (OUTH, OUTL) is deactivated at any time.