TW323388B - - Google Patents

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Publication number
TW323388B
TW323388B TW085109796A TW85109796A TW323388B TW 323388 B TW323388 B TW 323388B TW 085109796 A TW085109796 A TW 085109796A TW 85109796 A TW85109796 A TW 85109796A TW 323388 B TW323388 B TW 323388B
Authority
TW
Taiwan
Prior art keywords
oxide film
wafer
patent application
forming
silicon
Prior art date
Application number
TW085109796A
Other languages
English (en)
Chinese (zh)
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019950025649A external-priority patent/KR970012991A/ko
Priority claimed from KR1019950066069A external-priority patent/KR100197656B1/ko
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW323388B publication Critical patent/TW323388B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
TW085109796A 1995-08-21 1996-08-13 TW323388B (https=)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019950025649A KR970012991A (ko) 1995-08-21 1995-08-21 에스. 오. 아이 (soi) 웨이퍼 제조방법
KR1019950066069A KR100197656B1 (ko) 1995-12-29 1995-12-29 반도체 에스.오.아이.소자의 제조방법

Publications (1)

Publication Number Publication Date
TW323388B true TW323388B (https=) 1997-12-21

Family

ID=26631210

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085109796A TW323388B (https=) 1995-08-21 1996-08-13

Country Status (2)

Country Link
US (1) US5899712A (https=)
TW (1) TW323388B (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5811350A (en) 1996-08-22 1998-09-22 Micron Technology, Inc. Method of forming contact openings and an electronic component formed from the same and other methods
US6261948B1 (en) 1998-07-31 2001-07-17 Micron Technology, Inc. Method of forming contact openings
US6380023B2 (en) * 1998-09-02 2002-04-30 Micron Technology, Inc. Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits
US6326285B1 (en) 2000-02-24 2001-12-04 International Business Machines Corporation Simultaneous multiple silicon on insulator (SOI) wafer production
JP4776755B2 (ja) * 2000-06-08 2011-09-21 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4139105B2 (ja) * 2001-12-20 2008-08-27 株式会社ルネサステクノロジ 半導体装置の製造方法
DE102004060363B4 (de) * 2004-12-15 2010-12-16 Austriamicrosystems Ag Halbleitersubstrat mit pn-Übergang und Verfahren zur Herstellung

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091334A (en) * 1980-03-03 1992-02-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US4851078A (en) * 1987-06-29 1989-07-25 Harris Corporation Dielectric isolation process using double wafer bonding
JPH01152638A (ja) * 1987-12-10 1989-06-15 Sony Corp 半導体装置用基板の製造方法
JPH0355822A (ja) * 1989-07-25 1991-03-11 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法
JP3181695B2 (ja) * 1992-07-08 2001-07-03 ローム株式会社 Ｓｏｉ基板を用いた半導体装置の製造方法
US5359219A (en) * 1992-12-04 1994-10-25 Texas Instruments Incorporated Silicon on insulator device comprising improved substrate doping
JPH0766424A (ja) * 1993-08-20 1995-03-10 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP3427114B2 (ja) * 1994-06-03 2003-07-14 コマツ電子金属株式会社 半導体デバイス製造方法
JP3249892B2 (ja) * 1994-11-28 2002-01-21 三菱電機株式会社 Ｓｏｉ構造を有する半導体装置の製造方法
US5532175A (en) * 1995-04-17 1996-07-02 Motorola, Inc. Method of adjusting a threshold voltage for a semiconductor device fabricated on a semiconductor on insulator substrate
KR0172548B1 (ko) * 1995-06-30 1999-02-01 김주용 반도체 소자 및 그 제조방법

Also Published As

Publication number Publication date
US5899712A (en) 1999-05-04

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees